Lines Matching +full:0 +full:xf007
62 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define OCP_STD_PHY_BASE 0xa400
146 { PCI_VDEVICE(REALTEK, 0x2502) },
147 { PCI_VDEVICE(REALTEK, 0x2600) },
148 { PCI_VDEVICE(REALTEK, 0x8129) },
149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
150 { PCI_VDEVICE(REALTEK, 0x8161) },
151 { PCI_VDEVICE(REALTEK, 0x8162) },
152 { PCI_VDEVICE(REALTEK, 0x8167) },
153 { PCI_VDEVICE(REALTEK, 0x8168) },
154 { PCI_VDEVICE(NCUBE, 0x8168) },
155 { PCI_VDEVICE(REALTEK, 0x8169) },
156 { PCI_VENDOR_ID_DLINK, 0x4300,
157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
158 { PCI_VDEVICE(DLINK, 0x4300) },
159 { PCI_VDEVICE(DLINK, 0x4302) },
160 { PCI_VDEVICE(AT, 0xc107) },
161 { PCI_VDEVICE(USR, 0x0116) },
162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
164 { PCI_VDEVICE(REALTEK, 0x8125) },
165 { PCI_VDEVICE(REALTEK, 0x8126) },
166 { PCI_VDEVICE(REALTEK, 0x3000) },
173 MAC0 = 0, /* Ethernet hardware address. */
176 CounterAddrLow = 0x10,
177 CounterAddrHigh = 0x14,
178 TxDescStartAddrLow = 0x20,
179 TxDescStartAddrHigh = 0x24,
180 TxHDescStartAddrLow = 0x28,
181 TxHDescStartAddrHigh = 0x2c,
182 FLASH = 0x30,
183 ERSR = 0x36,
184 ChipCmd = 0x37,
185 TxPoll = 0x38,
186 IntrMask = 0x3c,
187 IntrStatus = 0x3e,
189 TxConfig = 0x40,
193 RxConfig = 0x44,
205 Cfg9346 = 0x50,
206 Config0 = 0x51,
207 Config1 = 0x52,
208 Config2 = 0x53,
211 Config3 = 0x54,
212 Config4 = 0x55,
213 Config5 = 0x56,
214 PHYAR = 0x60,
215 PHYstatus = 0x6c,
216 RxMaxSize = 0xda,
217 CPlusCmd = 0xe0,
218 IntrMitigate = 0xe2,
223 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
225 #define RTL_COALESCE_T_MAX 0x0fU
228 RxDescAddrLow = 0xe4,
229 RxDescAddrHigh = 0xe8,
230 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
232 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
234 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
237 #define EarlySize 0x27
239 FuncEvent = 0xf0,
240 FuncEventMask = 0xf4,
241 FuncPresetState = 0xf8,
242 IBCR0 = 0xf8,
243 IBCR2 = 0xf9,
244 IBIMR0 = 0xfa,
245 IBISR0 = 0xfb,
246 FuncForceEvent = 0xfc,
250 CSIDR = 0x64,
251 CSIAR = 0x68,
252 #define CSIAR_FLAG 0x80000000
253 #define CSIAR_WRITE_CMD 0x80000000
254 #define CSIAR_BYTE_ENABLE 0x0000f000
255 #define CSIAR_ADDR_MASK 0x00000fff
256 PMCH = 0x6f,
260 EPHYAR = 0x80,
261 #define EPHYAR_FLAG 0x80000000
262 #define EPHYAR_WRITE_CMD 0x80000000
263 #define EPHYAR_REG_MASK 0x1f
265 #define EPHYAR_DATA_MASK 0xffff
266 DLLPR = 0xd0,
269 DBG_REG = 0xd1,
272 TWSI = 0xd2,
273 MCU = 0xd3,
281 EFUSEAR = 0xdc,
282 #define EFUSEAR_FLAG 0x80000000
283 #define EFUSEAR_WRITE_CMD 0x80000000
284 #define EFUSEAR_READ_CMD 0x00000000
285 #define EFUSEAR_REG_MASK 0x03ff
287 #define EFUSEAR_DATA_MASK 0xff
288 MISC_1 = 0xf2,
293 LED_CTRL = 0x18,
294 LED_FREQ = 0x1a,
295 EEE_LED = 0x1b,
296 ERIDR = 0x70,
297 ERIAR = 0x74,
298 #define ERIAR_FLAG 0x80000000
299 #define ERIAR_WRITE_CMD 0x80000000
300 #define ERIAR_READ_CMD 0x00000000
303 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
304 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
305 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
306 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
308 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
309 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
310 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
311 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
312 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
313 EPHY_RXER_NUM = 0x7c,
314 OCPDR = 0xb0, /* OCP GPHY access */
315 #define OCPDR_WRITE_CMD 0x80000000
316 #define OCPDR_READ_CMD 0x00000000
317 #define OCPDR_REG_MASK 0x7f
319 #define OCPDR_DATA_MASK 0xffff
320 OCPAR = 0xb4,
321 #define OCPAR_FLAG 0x80000000
322 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
323 #define OCPAR_GPHY_READ_CMD 0x0000f060
324 GPHY_OCP = 0xb8,
325 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
326 MISC = 0xf0, /* 8168e only. */
335 LEDSEL0 = 0x18,
336 INT_CFG0_8125 = 0x34,
337 #define INT_CFG0_ENABLE_8125 BIT(0)
339 IntrMask_8125 = 0x38,
340 IntrStatus_8125 = 0x3c,
341 INT_CFG1_8125 = 0x7a,
342 LEDSEL2 = 0x84,
343 LEDSEL1 = 0x86,
344 TxPoll_8125 = 0x90,
345 LEDSEL3 = 0x96,
346 MAC0_BKP = 0x19e0,
347 EEE_TXIDLE_TIMER_8125 = 0x6048,
350 #define LEDSEL_MASK_8125 0x23f
360 SYSErr = 0x8000,
361 PCSTimeout = 0x4000,
362 SWInt = 0x0100,
363 TxDescUnavail = 0x0080,
364 RxFIFOOver = 0x0040,
365 LinkChg = 0x0020,
366 RxOverflow = 0x0010,
367 TxErr = 0x0008,
368 TxOK = 0x0004,
369 RxErr = 0x0002,
370 RxOK = 0x0001,
379 StopReq = 0x80,
380 CmdReset = 0x10,
381 CmdRxEnb = 0x08,
382 CmdTxEnb = 0x04,
383 RxBufEmpty = 0x01,
386 HPQ = 0x80, /* Poll cmd on the high prio queue */
387 NPQ = 0x40, /* Poll cmd on the low prio queue */
388 FSWInt = 0x01, /* Forced software interrupt */
391 Cfg9346_Lock = 0x00,
392 Cfg9346_Unlock = 0xc0,
395 AcceptErr = 0x20,
396 AcceptRunt = 0x10,
397 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
398 AcceptBroadcast = 0x08,
399 AcceptMulticast = 0x04,
400 AcceptMyPhys = 0x02,
401 AcceptAllPhys = 0x01,
402 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
403 #define RX_CONFIG_ACCEPT_MASK 0x3f
407 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
416 PMEnable = (1 << 0), /* Power Management Enable */
421 PCI_Clock_66MHz = 0x01,
422 PCI_Clock_33MHz = 0x00,
429 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
440 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
441 ASPM_en = (1 << 0), /* ASPM enable */
454 Mac_dbgo_sel = 0x001c, // 8168
459 #define INTT_MASK GENMASK(1, 0)
463 TBI_Enable = 0x80,
464 TxFlowCtrl = 0x40,
465 RxFlowCtrl = 0x20,
466 _1000bpsF = 0x10,
467 _100bps = 0x08,
468 _10bps = 0x04,
469 LinkStatus = 0x02,
470 FullDup = 0x01,
473 CounterReset = 0x1,
476 CounterDump = 0x8,
494 #define TD_MSS_MAX 0x07ffu /* MSS value */
515 #define GTTCPHO_MAX 0x7f
519 #define TCPHO_MAX 0x3ff
530 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
620 RTL_FLAG_TASK_ENABLED = 0,
789 for (i = 0; i < ETH_ALEN; i++) in rtl_read_mac_from_reg()
803 for (i = 0; i < n; i++) { in rtl_loop_wait()
845 if (ret < 0) in rtl8168_led_mod_ctrl()
854 return 0; in rtl8168_led_mod_ctrl()
863 if (ret < 0) in rtl8168_get_led_mode()
888 if (ret < 0) in rtl8125_set_led_mode()
898 return 0; in rtl8125_set_led_mode()
908 if (ret < 0) in rtl8125_get_led_mode()
929 pdom[0] = '\0'; in r8169_get_led_name()
934 pfun[0] = '\0'; in r8169_get_led_name()
946 *cmd |= 0xf70 << 18; in r8168fp_adjust_ocp_cmd()
959 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) in _rtl_eri_write()
983 RTL_R32(tp, ERIDR) : ~0; in _rtl_eri_read()
1000 rtl_w0w1_eri(tp, addr, p, 0); in rtl_eri_set_bits()
1005 rtl_w0w1_eri(tp, addr, 0, m); in rtl_eri_clear_bits()
1010 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); in rtl_ocp_reg_failure()
1031 return 0; in r8168_phy_ocp_read()
1036 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; in r8168_phy_ocp_read()
1059 return 0; in __r8168_mac_ocp_read()
1098 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
1100 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
1109 if (reg == 0x1f) { in r8168g_mdio_write()
1115 reg -= 0x10; in r8168g_mdio_write()
1125 if (reg == 0x1f) in r8168g_mdio_read()
1126 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; in r8168g_mdio_read()
1129 reg -= 0x10; in r8168g_mdio_read()
1136 if (reg == 0x1f) { in mac_mcu_write()
1151 return RTL_R32(tp, PHYAR) & 0x80000000; in DECLARE_RTL_COND()
1156 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
1170 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
1173 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; in r8169_mdio_read()
1189 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1193 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
1198 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1216 return 0xc912; in r8168dp_2_mdio_read()
1276 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; in rtl_ephy_read()
1281 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1283 RTL_R32(tp, OCPDR) : ~0; in r8168dp_ocp_read()
1295 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1302 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, in r8168ep_ocp_write()
1308 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); in r8168dp_oob_notify()
1310 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); in r8168dp_oob_notify()
1313 #define OOB_CMD_RESET 0x00
1314 #define OOB_CMD_DRIVER_START 0x05
1315 #define OOB_CMD_DRIVER_STOP 0x06
1319 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; in rtl8168_get_ocp_reg()
1328 return r8168dp_ocp_read(tp, reg) & 0x00000800; in DECLARE_RTL_COND()
1333 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; in DECLARE_RTL_COND()
1338 return RTL_R8(tp, IBISR0) & 0x20; in DECLARE_RTL_COND()
1343 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); in rtl8168ep_stop_cmac()
1345 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); in rtl8168ep_stop_cmac()
1346 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); in rtl8168ep_stop_cmac()
1380 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); in rtl8168ep_driver_start()
1381 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_start()
1402 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); in rtl8168ep_driver_stop()
1403 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_stop()
1424 return r8168ep_ocp_read(tp, 0x128) & BIT(0); in r8168ep_check_dash()
1471 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1472 rtl_eri_set_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1485 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; in rtl8168d_efuse_read()
1507 RTL_W32(tp, IntrMask_8125, 0); in rtl_irq_disable()
1509 RTL_W16(tp, IntrMask, 0); in rtl_irq_disable()
1523 rtl_ack_events(tp, 0xffffffff); in rtl8169_irq_mask_and_ack()
1534 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1535 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1537 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1538 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1540 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1541 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1547 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1548 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1550 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1551 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1555 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); in rtl_link_chg_patch()
1556 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); in rtl_link_chg_patch()
1558 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_link_chg_patch()
1596 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1598 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1602 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); in __rtl8169_set_wol()
1604 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); in __rtl8169_set_wol()
1608 for (i = 0; i < tmp; i++) { in __rtl8169_set_wol()
1627 rtl_mod_config2(tp, 0, PME_SIGNAL); in __rtl8169_set_wol()
1629 rtl_mod_config2(tp, PME_SIGNAL, 0); in __rtl8169_set_wol()
1641 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; in __rtl8169_set_wol()
1655 return 0; in rtl8169_set_wol()
1734 return 0; in rtl8169_set_features()
1740 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; in rtl8169_tx_vlan_tag()
1748 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); in rtl8169_rx_vlan_tag()
1759 for (i = 0; i < R8169_REGS_SIZE; i += 4) in rtl8169_get_regs()
1812 * is disabled. If 0xff chip may be in a PCI power-save state. in rtl8169_update_counters()
1814 if (val & CmdRxEnb && val != 0xff) in rtl8169_update_counters()
1862 data[0] = le64_to_cpu(counters->tx_packets); in rtl8169_get_ethtool_stats()
1889 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1897 * (0xe0) bit 1 and bit 0.
1900 * bit[1:0] \ speed 1000M 100M 10M
1901 * 0 0 320ns 2.56us 40.96us
1902 * 0 1 2.56us 20.48us 327.7us
1903 * 1 0 5.12us 40.96us 655.4us
1907 * bit[1:0] \ speed 1000M 100M 10M
1908 * 0 0 5us 2.56us 40.96us
1909 * 0 1 40us 20.48us 327.7us
1910 * 1 0 80us 40.96us 655.4us
1914 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1927 { 0 },
1934 { 0 },
1974 memset(ec, 0, sizeof(*ec)); in rtl_get_coalesce()
1976 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ in rtl_get_coalesce()
1989 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ in rtl_get_coalesce()
1998 return 0; in rtl_get_coalesce()
2001 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
2012 for (i = 0; i < 4; i++) { in rtl_coalesce_choose_scale()
2031 u16 w = 0, cp01 = 0; in rtl_set_coalesce()
2042 if (scale < 0) in rtl_set_coalesce()
2046 * not only when usecs=0 because of e.g. the following scenario: in rtl_set_coalesce()
2048 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) in rtl_set_coalesce()
2049 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 in rtl_set_coalesce()
2053 * if we want to ignore rx_frames then it has to be set to 0. in rtl_set_coalesce()
2056 rx_fr = 0; in rtl_set_coalesce()
2058 tx_fr = 0; in rtl_set_coalesce()
2088 return 0; in rtl_set_coalesce()
2093 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; in rtl_set_eee_txidle_timer()
2099 r8168_mac_ocp_write(tp, 0xe048, timer_val); in rtl_set_eee_txidle_timer()
2119 return 0; in r8169_get_tx_lpi_timer_us()
2139 return 0; in rtl8169_get_eee()
2172 data->tx_pause = tx_pause ? 1 : 0; in rtl8169_get_pauseparam()
2173 data->rx_pause = rx_pause ? 1 : 0; in rtl8169_get_pauseparam()
2186 return 0; in rtl8169_set_pauseparam()
2221 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be in rtl8169_get_mac_version()
2225 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec in rtl8169_get_mac_version()
2233 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 }, in rtl8169_get_mac_version()
2234 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, in rtl8169_get_mac_version()
2237 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, in rtl8169_get_mac_version()
2240 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, in rtl8169_get_mac_version()
2242 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, in rtl8169_get_mac_version()
2243 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, in rtl8169_get_mac_version()
2247 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, in rtl8169_get_mac_version()
2248 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, in rtl8169_get_mac_version()
2251 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, in rtl8169_get_mac_version()
2254 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, in rtl8169_get_mac_version()
2255 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, in rtl8169_get_mac_version()
2259 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, in rtl8169_get_mac_version()
2262 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, in rtl8169_get_mac_version()
2265 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, in rtl8169_get_mac_version()
2268 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, in rtl8169_get_mac_version()
2269 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, in rtl8169_get_mac_version()
2272 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, in rtl8169_get_mac_version()
2274 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, in rtl8169_get_mac_version()
2277 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, in rtl8169_get_mac_version()
2278 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, in rtl8169_get_mac_version()
2279 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, in rtl8169_get_mac_version()
2282 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, in rtl8169_get_mac_version()
2283 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, in rtl8169_get_mac_version()
2284 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, in rtl8169_get_mac_version()
2287 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, in rtl8169_get_mac_version()
2288 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, in rtl8169_get_mac_version()
2293 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, in rtl8169_get_mac_version()
2295 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, in rtl8169_get_mac_version()
2296 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, in rtl8169_get_mac_version()
2299 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, in rtl8169_get_mac_version()
2300 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, in rtl8169_get_mac_version()
2301 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, in rtl8169_get_mac_version()
2302 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, in rtl8169_get_mac_version()
2303 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, in rtl8169_get_mac_version()
2304 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, in rtl8169_get_mac_version()
2305 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, in rtl8169_get_mac_version()
2308 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, in rtl8169_get_mac_version()
2310 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, in rtl8169_get_mac_version()
2314 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, in rtl8169_get_mac_version()
2315 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, in rtl8169_get_mac_version()
2316 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, in rtl8169_get_mac_version()
2317 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, in rtl8169_get_mac_version()
2318 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
2319 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
2320 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
2321 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
2322 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, in rtl8169_get_mac_version()
2323 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
2324 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
2325 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, in rtl8169_get_mac_version()
2328 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, in rtl8169_get_mac_version()
2329 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, in rtl8169_get_mac_version()
2330 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, in rtl8169_get_mac_version()
2331 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, in rtl8169_get_mac_version()
2332 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, in rtl8169_get_mac_version()
2335 { 0x000, 0x000, RTL_GIGA_MAC_NONE } in rtl8169_get_mac_version()
2384 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); in rtl8168_config_eee_mac()
2386 rtl_eri_set_bits(tp, 0x1b0, 0x0003); in rtl8168_config_eee_mac()
2391 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125a_config_eee_mac()
2392 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); in rtl8125a_config_eee_mac()
2397 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125b_config_eee_mac()
2402 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); in rtl_rar_exgmac_set()
2403 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); in rtl_rar_exgmac_set()
2404 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); in rtl_rar_exgmac_set()
2405 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); in rtl_rar_exgmac_set()
2412 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); in rtl8168h_2_get_adc_bias_ioffset()
2413 data1 = r8168_mac_ocp_read(tp, 0xdd02); in rtl8168h_2_get_adc_bias_ioffset()
2414 data2 = r8168_mac_ocp_read(tp, 0xdd00); in rtl8168h_2_get_adc_bias_ioffset()
2416 ioffset = (data2 >> 1) & 0x7ff8; in rtl8168h_2_get_adc_bias_ioffset()
2417 ioffset |= data2 & 0x0007; in rtl8168h_2_get_adc_bias_ioffset()
2438 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); in rtl8169_init_phy()
2439 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); in rtl8169_init_phy()
2440 /* set undocumented MAC Reg C+CR Offset 0x82h */ in rtl8169_init_phy()
2441 RTL_W8(tp, 0x82, 0x01); in rtl8169_init_phy()
2446 tp->pci_dev->subsystem_device == 0xe000) in rtl8169_init_phy()
2447 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); in rtl8169_init_phy()
2482 return 0; in rtl_set_mac_address()
2517 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; in rtl8169_init_ring_indexes()
2544 RTL_W8(tp, MaxTxPacketSize, 0x24); in r8168e_hw_jumbo_enable()
2546 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); in r8168e_hw_jumbo_enable()
2551 RTL_W8(tp, MaxTxPacketSize, 0x3f); in r8168e_hw_jumbo_disable()
2553 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); in r8168e_hw_jumbo_disable()
2558 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); in r8168b_1_hw_jumbo_enable()
2563 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); in r8168b_1_hw_jumbo_disable()
2679 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; in DECLARE_RTL_COND()
2731 rtl_ephy_write(tp, 0x19, 0xff64); in rtl_prepare_power_down()
2774 val = 0x000fff00; in rtl8169_set_magic_reg()
2776 val = 0x00ffff00; in rtl8169_set_magic_reg()
2781 val |= 0xff; in rtl8169_set_magic_reg()
2783 RTL_W32(tp, 0x7c, val); in rtl8169_set_magic_reg()
2790 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; in rtl_set_rx_mode()
2806 mc_filter[1] = mc_filter[0] = 0; in rtl_set_rx_mode()
2813 tmp = mc_filter[0]; in rtl_set_rx_mode()
2814 mc_filter[0] = swab32(mc_filter[1]); in rtl_set_rx_mode()
2820 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
2850 RTL_R32(tp, CSIDR) : ~0; in rtl_csi_read()
2858 /* According to Realtek the value at config space address 0x070f in rtl_set_aspm_entry_latency()
2861 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) in rtl_set_aspm_entry_latency()
2862 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us in rtl_set_aspm_entry_latency()
2864 if (pdev->cfg_size > 0x070f && in rtl_set_aspm_entry_latency()
2865 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) in rtl_set_aspm_entry_latency()
2870 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; in rtl_set_aspm_entry_latency()
2871 rtl_csi_write(tp, 0x070c, csi | val << 24); in rtl_set_aspm_entry_latency()
2877 rtl_set_aspm_entry_latency(tp, 0x27); in rtl_set_def_aspm_entry_latency()
2891 while (len-- > 0) { in __rtl_ephy_init()
2930 rtl_eri_set_bits(tp, 0xd4, 0x1f00); in rtl_enable_exit_l1()
2933 rtl_eri_set_bits(tp, 0xd4, 0x0c00); in rtl_enable_exit_l1()
2936 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); in rtl_enable_exit_l1()
2947 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); in rtl_disable_exit_l1()
2950 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); in rtl_disable_exit_l1()
2973 rtl_mod_config5(tp, 0, ASPM_en); in rtl_hw_aspm_clkreq_enable()
2981 rtl_mod_config2(tp, 0, ClkReqEn); in rtl_hw_aspm_clkreq_enable()
2989 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); in rtl_hw_aspm_clkreq_enable()
2991 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); in rtl_hw_aspm_clkreq_enable()
3000 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); in rtl_hw_aspm_clkreq_enable()
3013 rtl_mod_config2(tp, ClkReqEn, 0); in rtl_hw_aspm_clkreq_enable()
3016 rtl_mod_config5(tp, ASPM_en, 0); in rtl_hw_aspm_clkreq_enable()
3026 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); in rtl_set_fifo_size()
3027 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); in rtl_set_fifo_size()
3034 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); in rtl8168g_set_pause_thresholds()
3035 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); in rtl8168g_set_pause_thresholds()
3055 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168cp_1()
3056 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168cp_1()
3057 { 0x03, 0, 0x0042 }, in rtl_hw_start_8168cp_1()
3058 { 0x06, 0x0080, 0x0000 }, in rtl_hw_start_8168cp_1()
3059 { 0x07, 0, 0x2000 } in rtl_hw_start_8168cp_1()
3083 RTL_W8(tp, DBG_REG, 0x20); in rtl_hw_start_8168cp_3()
3089 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168c_1()
3090 { 0x03, 0, 0x0002 }, in rtl_hw_start_8168c_1()
3091 { 0x06, 0x0080, 0x0000 } in rtl_hw_start_8168c_1()
3096 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); in rtl_hw_start_8168c_1()
3106 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168c_2()
3107 { 0x03, 0x0400, 0x0020 } in rtl_hw_start_8168c_2()
3134 { 0x0b, 0x0000, 0x0048 }, in rtl_hw_start_8168d_4()
3135 { 0x19, 0x0020, 0x0050 }, in rtl_hw_start_8168d_4()
3136 { 0x0c, 0x0100, 0x0020 }, in rtl_hw_start_8168d_4()
3137 { 0x10, 0x0004, 0x0000 }, in rtl_hw_start_8168d_4()
3150 { 0x00, 0x0200, 0x0100 }, in rtl_hw_start_8168e_1()
3151 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_1()
3152 { 0x06, 0x0002, 0x0001 }, in rtl_hw_start_8168e_1()
3153 { 0x06, 0x0000, 0x0030 }, in rtl_hw_start_8168e_1()
3154 { 0x07, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
3155 { 0x00, 0x0000, 0x0020 }, in rtl_hw_start_8168e_1()
3156 { 0x03, 0x5800, 0x2000 }, in rtl_hw_start_8168e_1()
3157 { 0x03, 0x0000, 0x0001 }, in rtl_hw_start_8168e_1()
3158 { 0x01, 0x0800, 0x1000 }, in rtl_hw_start_8168e_1()
3159 { 0x07, 0x0000, 0x4000 }, in rtl_hw_start_8168e_1()
3160 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
3161 { 0x19, 0xffff, 0xfe6c }, in rtl_hw_start_8168e_1()
3162 { 0x0a, 0x0000, 0x0040 } in rtl_hw_start_8168e_1()
3175 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_1()
3181 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168e_2()
3182 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168e_2()
3183 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_2()
3184 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168e_2()
3191 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168e_2()
3192 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168e_2()
3193 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168e_2()
3194 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); in rtl_hw_start_8168e_2()
3196 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168e_2()
3197 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168e_2()
3198 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); in rtl_hw_start_8168e_2()
3208 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_2()
3215 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168f()
3216 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168f()
3217 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168f()
3219 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168f()
3220 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); in rtl_hw_start_8168f()
3221 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168f()
3222 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); in rtl_hw_start_8168f()
3229 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168f()
3237 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8168f_1()
3238 { 0x08, 0x0001, 0x0002 }, in rtl_hw_start_8168f_1()
3239 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168f_1()
3240 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168f_1()
3241 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8168f_1()
3242 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168f_1()
3253 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8411()
3254 { 0x0f, 0xffff, 0x5200 }, in rtl_hw_start_8411()
3255 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8411()
3256 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8411()
3257 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8411()
3268 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168g()
3269 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168g()
3274 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); in rtl_hw_start_8168g()
3278 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3279 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3283 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168g()
3284 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168g()
3292 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_1()
3293 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_1()
3294 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8168g_1()
3295 { 0x19, 0x8000, 0x0000 } in rtl_hw_start_8168g_1()
3305 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_2()
3306 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_2()
3307 { 0x19, 0xffff, 0x7c00 }, in rtl_hw_start_8168g_2()
3308 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8168g_2()
3309 { 0x0d, 0xffff, 0x1666 }, in rtl_hw_start_8168g_2()
3310 { 0x00, 0xffff, 0x10a3 }, in rtl_hw_start_8168g_2()
3311 { 0x06, 0xffff, 0xf050 }, in rtl_hw_start_8168g_2()
3312 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8168g_2()
3313 { 0x1d, 0x4000, 0x0000 }, in rtl_hw_start_8168g_2()
3323 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, in rtl8411b_fix_phy_down()
3324 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, in rtl8411b_fix_phy_down()
3325 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, in rtl8411b_fix_phy_down()
3326 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, in rtl8411b_fix_phy_down()
3327 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, in rtl8411b_fix_phy_down()
3328 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, in rtl8411b_fix_phy_down()
3329 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, in rtl8411b_fix_phy_down()
3330 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, in rtl8411b_fix_phy_down()
3331 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, in rtl8411b_fix_phy_down()
3332 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, in rtl8411b_fix_phy_down()
3333 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, in rtl8411b_fix_phy_down()
3334 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, in rtl8411b_fix_phy_down()
3335 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, in rtl8411b_fix_phy_down()
3336 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 in rtl8411b_fix_phy_down()
3342 for (i = 0; i < ARRAY_SIZE(fix_data); i++) in rtl8411b_fix_phy_down()
3343 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); in rtl8411b_fix_phy_down()
3350 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8411_2()
3351 { 0x0c, 0x37d0, 0x0820 }, in rtl_hw_start_8411_2()
3352 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8411_2()
3353 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8411_2()
3354 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8411_2()
3355 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8411_2()
3356 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8411_2()
3357 { 0x06, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3358 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3359 { 0x1d, 0x0000, 0x4000 }, in rtl_hw_start_8411_2()
3369 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); in rtl_hw_start_8411_2()
3370 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); in rtl_hw_start_8411_2()
3371 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); in rtl_hw_start_8411_2()
3372 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); in rtl_hw_start_8411_2()
3373 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); in rtl_hw_start_8411_2()
3374 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); in rtl_hw_start_8411_2()
3375 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); in rtl_hw_start_8411_2()
3376 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); in rtl_hw_start_8411_2()
3378 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); in rtl_hw_start_8411_2()
3382 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); in rtl_hw_start_8411_2()
3384 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); in rtl_hw_start_8411_2()
3385 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); in rtl_hw_start_8411_2()
3386 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); in rtl_hw_start_8411_2()
3387 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); in rtl_hw_start_8411_2()
3388 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); in rtl_hw_start_8411_2()
3389 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); in rtl_hw_start_8411_2()
3390 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); in rtl_hw_start_8411_2()
3396 { 0x1e, 0x0800, 0x0001 }, in rtl_hw_start_8168h_1()
3397 { 0x1d, 0x0000, 0x0800 }, in rtl_hw_start_8168h_1()
3398 { 0x05, 0xffff, 0x2089 }, in rtl_hw_start_8168h_1()
3399 { 0x06, 0xffff, 0x5881 }, in rtl_hw_start_8168h_1()
3400 { 0x04, 0xffff, 0x854a }, in rtl_hw_start_8168h_1()
3401 { 0x01, 0xffff, 0x068b } in rtl_hw_start_8168h_1()
3407 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168h_1()
3408 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168h_1()
3414 rtl_eri_set_bits(tp, 0xdc, 0x001c); in rtl_hw_start_8168h_1()
3416 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168h_1()
3420 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3421 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3430 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168h_1()
3434 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8168h_1()
3435 if (rg_saw_cnt > 0) { in rtl_hw_start_8168h_1()
3439 sw_cnt_1ms_ini &= 0x0fff; in rtl_hw_start_8168h_1()
3440 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8168h_1()
3443 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8168h_1()
3444 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); in rtl_hw_start_8168h_1()
3445 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); in rtl_hw_start_8168h_1()
3446 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8168h_1()
3448 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8168h_1()
3449 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8168h_1()
3450 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8168h_1()
3451 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8168h_1()
3458 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168ep()
3459 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8168ep()
3465 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168ep()
3469 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3470 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3474 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168ep()
3484 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8168ep_3()
3485 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8168ep_3()
3486 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8168ep_3()
3487 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168ep_3()
3497 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); in rtl_hw_start_8168ep_3()
3498 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8168ep_3()
3499 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8168ep_3()
3505 { 0x19, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3506 { 0x59, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3513 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8117()
3514 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8117()
3520 rtl_eri_set_bits(tp, 0xd4, 0x0010); in rtl_hw_start_8117()
3522 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8117()
3526 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3527 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3536 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8117()
3540 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8117()
3541 if (rg_saw_cnt > 0) { in rtl_hw_start_8117()
3544 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; in rtl_hw_start_8117()
3545 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8117()
3548 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8117()
3549 r8168_mac_ocp_write(tp, 0xea80, 0x0003); in rtl_hw_start_8117()
3550 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); in rtl_hw_start_8117()
3551 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8117()
3553 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8117()
3554 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8117()
3555 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8117()
3556 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8117()
3565 { 0x01, 0, 0x6e65 }, in rtl_hw_start_8102e_1()
3566 { 0x02, 0, 0x091f }, in rtl_hw_start_8102e_1()
3567 { 0x03, 0, 0xc2f9 }, in rtl_hw_start_8102e_1()
3568 { 0x06, 0, 0xafb5 }, in rtl_hw_start_8102e_1()
3569 { 0x07, 0, 0x0e00 }, in rtl_hw_start_8102e_1()
3570 { 0x19, 0, 0xec80 }, in rtl_hw_start_8102e_1()
3571 { 0x01, 0, 0x2e65 }, in rtl_hw_start_8102e_1()
3572 { 0x01, 0, 0x6e65 } in rtl_hw_start_8102e_1()
3603 rtl_ephy_write(tp, 0x03, 0xc2f9); in rtl_hw_start_8102e_3()
3609 { 0x01, 0xffff, 0x6fe5 }, in rtl_hw_start_8401()
3610 { 0x03, 0xffff, 0x0599 }, in rtl_hw_start_8401()
3611 { 0x06, 0xffff, 0xaf25 }, in rtl_hw_start_8401()
3612 { 0x07, 0xffff, 0x8e68 }, in rtl_hw_start_8401()
3622 { 0x07, 0, 0x4000 }, in rtl_hw_start_8105e_1()
3623 { 0x19, 0, 0x0200 }, in rtl_hw_start_8105e_1()
3624 { 0x19, 0, 0x0020 }, in rtl_hw_start_8105e_1()
3625 { 0x1e, 0, 0x2000 }, in rtl_hw_start_8105e_1()
3626 { 0x03, 0, 0x0001 }, in rtl_hw_start_8105e_1()
3627 { 0x19, 0, 0x0100 }, in rtl_hw_start_8105e_1()
3628 { 0x19, 0, 0x0004 }, in rtl_hw_start_8105e_1()
3629 { 0x0a, 0, 0x0020 } in rtl_hw_start_8105e_1()
3633 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
3636 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
3649 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); in rtl_hw_start_8105e_2()
3655 { 0x19, 0xffff, 0xff64 }, in rtl_hw_start_8402()
3656 { 0x1e, 0, 0x4000 } in rtl_hw_start_8402()
3662 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
3668 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); in rtl_hw_start_8402()
3670 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3671 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3672 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); in rtl_hw_start_8402()
3675 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3683 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
3690 rtl_set_aspm_entry_latency(tp, 0x2f); in rtl_hw_start_8106()
3692 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3695 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3702 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); in DECLARE_RTL_COND()
3709 RTL_W16(tp, 0x382, 0x221b); in rtl_hw_start_8125_common()
3710 RTL_W8(tp, 0x4500, 0); in rtl_hw_start_8125_common()
3711 RTL_W16(tp, 0x4800, 0); in rtl_hw_start_8125_common()
3714 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); in rtl_hw_start_8125_common()
3716 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); in rtl_hw_start_8125_common()
3718 r8168_mac_ocp_write(tp, 0xc140, 0xffff); in rtl_hw_start_8125_common()
3719 r8168_mac_ocp_write(tp, 0xc142, 0xffff); in rtl_hw_start_8125_common()
3721 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); in rtl_hw_start_8125_common()
3722 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8125_common()
3723 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8125_common()
3726 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3730 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); in rtl_hw_start_8125_common()
3734 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); in rtl_hw_start_8125_common()
3736 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); in rtl_hw_start_8125_common()
3738 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); in rtl_hw_start_8125_common()
3741 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); in rtl_hw_start_8125_common()
3743 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); in rtl_hw_start_8125_common()
3745 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); in rtl_hw_start_8125_common()
3746 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); in rtl_hw_start_8125_common()
3747 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); in rtl_hw_start_8125_common()
3748 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); in rtl_hw_start_8125_common()
3749 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); in rtl_hw_start_8125_common()
3750 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); in rtl_hw_start_8125_common()
3753 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); in rtl_hw_start_8125_common()
3755 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3756 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); in rtl_hw_start_8125_common()
3757 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); in rtl_hw_start_8125_common()
3758 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); in rtl_hw_start_8125_common()
3760 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3761 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); in rtl_hw_start_8125_common()
3763 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3764 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); in rtl_hw_start_8125_common()
3766 r8168_mac_ocp_write(tp, 0xe098, 0xc302); in rtl_hw_start_8125_common()
3781 { 0x04, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3782 { 0x0a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3783 { 0x23, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3784 { 0x20, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3785 { 0x21, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3786 { 0x29, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3788 { 0x44, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3789 { 0x4a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3790 { 0x63, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3791 { 0x60, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3792 { 0x61, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3793 { 0x69, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3804 { 0x0b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3805 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3806 { 0x4b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3807 { 0x5e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3808 { 0x22, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3809 { 0x62, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3877 RTL_W8(tp, INT_CFG0_8125, 0x00); in rtl_hw_start_8125()
3882 for (i = 0xa00; i < 0xb00; i += 4) in rtl_hw_start_8125()
3883 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3888 for (i = 0xa00; i < 0xa80; i += 4) in rtl_hw_start_8125()
3889 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3890 RTL_W16(tp, INT_CFG1_8125, 0x0000); in rtl_hw_start_8125()
3909 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8168()
3927 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8169()
3974 return 0; in rtl8169_change_mtu()
3981 desc->opts2 = 0; in rtl8169_mark_to_asic()
3999 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); in rtl8169_alloc_rx_data()
4016 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { in rtl8169_rx_clear()
4022 tp->RxDescArray[i].addr = 0; in rtl8169_rx_clear()
4023 tp->RxDescArray[i].opts1 = 0; in rtl8169_rx_clear()
4031 for (i = 0; i < NUM_RX_DESC; i++) { in rtl8169_rx_fill()
4045 return 0; in rtl8169_rx_fill()
4052 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); in rtl8169_init_ring()
4053 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); in rtl8169_init_ring()
4065 memset(desc, 0, sizeof(*desc)); in rtl8169_unmap_tx_skb()
4066 memset(tx_skb, 0, sizeof(*tx_skb)); in rtl8169_unmap_tx_skb()
4074 for (i = 0; i < n; i++) { in rtl8169_tx_clear_range()
4140 for (i = 0; i < NUM_RX_DESC; i++) in rtl_reset_work()
4174 opts1 = opts[0] | len; in rtl8169_tx_map()
4183 return 0; in rtl8169_tx_map()
4192 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { in rtl8169_xmit_frags()
4203 return 0; in rtl8169_xmit_frags()
4234 unsigned int padto = 0, len = skb->len; in rtl8125_quirk_udp_padto()
4282 opts[0] |= TD_LSO; in rtl8169_tso_csum_v1()
4283 opts[0] |= mss << TD0_MSS_SHIFT; in rtl8169_tso_csum_v1()
4288 opts[0] |= TD0_IP_CS | TD0_TCP_CS; in rtl8169_tso_csum_v1()
4290 opts[0] |= TD0_IP_CS | TD0_UDP_CS; in rtl8169_tso_csum_v1()
4304 opts[0] |= TD1_GTSENV4; in rtl8169_tso_csum_v2()
4306 if (skb_cow_head(skb, 0)) in rtl8169_tso_csum_v2()
4310 opts[0] |= TD1_GTSENV6; in rtl8169_tso_csum_v2()
4315 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; in rtl8169_tso_csum_v2()
4374 RTL_W16(tp, TxPoll_8125, BIT(0)); in rtl8169_doorbell()
4397 opts[0] = 0; in rtl8169_start_xmit()
4435 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), in rtl8169_start_xmit()
4523 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", in rtl8169_pcierr_interrupt()
4532 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; in rtl_tx()
4560 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, in rtl_tx()
4596 for (count = 0; count < budget; count++, tp->cur_rx++) { in rtl_rx()
4630 pkt_size = status & GENMASK(13, 0); in rtl_rx()
4682 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) in rtl8169_interrupt()
4722 if (RTL_R32(tp, TxConfig) == ~0) { in rtl_task()
4724 if (ret < 0) { in rtl_task()
4804 return 0; in r8169_phy_connect()
4869 return 0; in rtl8169_close()
4905 if (retval < 0) in rtl_open()
4912 if (retval < 0) in rtl_open()
4998 return 0; in rtl8169_runtime_resume()
5011 return 0; in rtl8169_suspend()
5034 return 0; in rtl8169_runtime_suspend()
5042 return 0; in rtl8169_runtime_suspend()
5163 value = rtl_eri_read(tp, 0xe0); in rtl_read_mac_address()
5165 value = rtl_eri_read(tp, 0xe4); in rtl_read_mac_address()
5186 if (phyaddr > 0) in r8169_mdio_read_reg()
5197 if (phyaddr > 0) in r8169_mdio_write_reg()
5202 return 0; in r8169_mdio_write_reg()
5218 r8169_mdio_write(tp, 0x1f, 0); in r8169_mdio_register()
5227 new_bus->irq[0] = PHY_MAC_INTERRUPT; in r8169_mdio_register()
5238 tp->phydev = mdiobus_get_phy(new_bus, 0); in r8169_mdio_register()
5245 …dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be… in r8169_mdio_register()
5258 return 0; in r8169_mdio_register()
5269 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8168g()
5272 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); in rtl_hw_init_8168g()
5284 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8125()
5287 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); in rtl_hw_init_8125()
5288 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); in rtl_hw_init_8125()
5289 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); in rtl_hw_init_8125()
5314 return 0; in rtl_jumbo_max()
5362 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) in rtl_aspm_is_safe()
5386 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; in rtl_init_one()
5401 if (rc < 0) in rtl_init_one()
5404 if (pcim_set_mwi(pdev) < 0) in rtl_init_one()
5409 if (region < 0) in rtl_init_one()
5413 if (rc < 0) in rtl_init_one()
5419 if (txconfig == ~0U) in rtl_init_one()
5422 xid = (txconfig >> 20) & 0xfcf; in rtl_init_one()
5436 rc = 0; in rtl_init_one()
5459 if (rc < 0) in rtl_init_one()
5462 tp->irq = pci_irq_vector(pdev, 0); in rtl_init_one()
5570 return 0; in rtl_init_one()