Lines Matching +full:0 +full:x349
66 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77 #define OCP_STD_PHY_BASE 0xa400
103 { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 },
106 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 },
107 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 },
110 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 },
113 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 },
114 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 },
117 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 },
120 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 },
123 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" },
124 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117",
128 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" },
131 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h",
134 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 },
137 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 },
138 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu",
140 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g",
144 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 },
145 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f",
147 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f",
151 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl",
153 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e",
155 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e",
159 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d",
161 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d",
165 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" },
166 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" },
169 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" },
170 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" },
171 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" },
172 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" },
173 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" },
174 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" },
175 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" },
178 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" },
180 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" },
184 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 },
185 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 },
186 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 },
187 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 },
188 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" },
189 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" },
190 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" },
191 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" },
192 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" },
193 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" },
194 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" },
195 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" },
198 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" },
199 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" },
200 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" },
201 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" },
202 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" },
205 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
209 { PCI_VDEVICE(REALTEK, 0x2502) },
210 { PCI_VDEVICE(REALTEK, 0x2600) },
211 { PCI_VDEVICE(REALTEK, 0x8129) },
212 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
213 { PCI_VDEVICE(REALTEK, 0x8161) },
214 { PCI_VDEVICE(REALTEK, 0x8162) },
215 { PCI_VDEVICE(REALTEK, 0x8167) },
216 { PCI_VDEVICE(REALTEK, 0x8168) },
217 { PCI_VDEVICE(NCUBE, 0x8168) },
218 { PCI_VDEVICE(REALTEK, 0x8169) },
219 { PCI_VDEVICE(DLINK, 0x4300) },
220 { PCI_VDEVICE(DLINK, 0x4302) },
221 { PCI_VDEVICE(AT, 0xc107) },
222 { PCI_VDEVICE(USR, 0x0116) },
223 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
224 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
225 { PCI_VDEVICE(REALTEK, 0x8125) },
226 { PCI_VDEVICE(REALTEK, 0x8126) },
227 { PCI_VDEVICE(REALTEK, 0x8127) },
228 { PCI_VDEVICE(REALTEK, 0x3000) },
229 { PCI_VDEVICE(REALTEK, 0x5000) },
230 { PCI_VDEVICE(REALTEK, 0x0e10) },
237 MAC0 = 0, /* Ethernet hardware address. */
240 CounterAddrLow = 0x10,
241 CounterAddrHigh = 0x14,
242 TxDescStartAddrLow = 0x20,
243 TxDescStartAddrHigh = 0x24,
244 TxHDescStartAddrLow = 0x28,
245 TxHDescStartAddrHigh = 0x2c,
246 FLASH = 0x30,
247 ERSR = 0x36,
248 ChipCmd = 0x37,
249 TxPoll = 0x38,
250 IntrMask = 0x3c,
251 IntrStatus = 0x3e,
253 TxConfig = 0x40,
257 RxConfig = 0x44,
269 Cfg9346 = 0x50,
270 Config0 = 0x51,
271 Config1 = 0x52,
272 Config2 = 0x53,
275 Config3 = 0x54,
276 Config4 = 0x55,
277 Config5 = 0x56,
278 PHYAR = 0x60,
279 PHYstatus = 0x6c,
280 RxMaxSize = 0xda,
281 CPlusCmd = 0xe0,
282 IntrMitigate = 0xe2,
287 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
289 #define RTL_COALESCE_T_MAX 0x0fU
292 RxDescAddrLow = 0xe4,
293 RxDescAddrHigh = 0xe8,
294 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
296 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
298 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
301 #define EarlySize 0x27
303 FuncEvent = 0xf0,
304 FuncEventMask = 0xf4,
305 FuncPresetState = 0xf8,
306 IBCR0 = 0xf8,
307 IBCR2 = 0xf9,
308 IBIMR0 = 0xfa,
309 IBISR0 = 0xfb,
310 FuncForceEvent = 0xfc,
314 CSIDR = 0x64,
315 CSIAR = 0x68,
316 #define CSIAR_FLAG 0x80000000
317 #define CSIAR_WRITE_CMD 0x80000000
318 #define CSIAR_BYTE_ENABLE 0x0000f000
319 #define CSIAR_ADDR_MASK 0x00000fff
320 PMCH = 0x6f,
324 EPHYAR = 0x80,
325 #define EPHYAR_FLAG 0x80000000
326 #define EPHYAR_WRITE_CMD 0x80000000
327 #define EPHYAR_REG_MASK 0x1f
329 #define EPHYAR_DATA_MASK 0xffff
330 DLLPR = 0xd0,
333 DBG_REG = 0xd1,
336 TWSI = 0xd2,
337 MCU = 0xd3,
345 EFUSEAR = 0xdc,
346 #define EFUSEAR_FLAG 0x80000000
347 #define EFUSEAR_WRITE_CMD 0x80000000
348 #define EFUSEAR_READ_CMD 0x00000000
349 #define EFUSEAR_REG_MASK 0x03ff
351 #define EFUSEAR_DATA_MASK 0xff
352 MISC_1 = 0xf2,
357 LED_CTRL = 0x18,
358 LED_FREQ = 0x1a,
359 EEE_LED = 0x1b,
360 ERIDR = 0x70,
361 ERIAR = 0x74,
362 #define ERIAR_FLAG 0x80000000
363 #define ERIAR_WRITE_CMD 0x80000000
364 #define ERIAR_READ_CMD 0x00000000
367 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
368 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
369 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
370 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
373 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
374 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
375 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
377 EPHY_RXER_NUM = 0x7c,
378 OCPDR = 0xb0, /* OCP GPHY access */
379 #define OCPDR_WRITE_CMD 0x80000000
380 #define OCPDR_READ_CMD 0x00000000
381 #define OCPDR_REG_MASK 0x7f
383 #define OCPDR_DATA_MASK 0xffff
384 OCPAR = 0xb4,
385 #define OCPAR_FLAG 0x80000000
386 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
387 #define OCPAR_GPHY_READ_CMD 0x0000f060
388 GPHY_OCP = 0xb8,
389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
399 LEDSEL0 = 0x18,
400 INT_CFG0_8125 = 0x34,
401 #define INT_CFG0_ENABLE_8125 BIT(0)
403 IntrMask_8125 = 0x38,
404 IntrStatus_8125 = 0x3c,
405 INT_CFG1_8125 = 0x7a,
406 LEDSEL2 = 0x84,
407 LEDSEL1 = 0x86,
408 TxPoll_8125 = 0x90,
409 LEDSEL3 = 0x96,
410 MAC0_BKP = 0x19e0,
411 RSS_CTRL_8125 = 0x4500,
412 Q_NUM_CTRL_8125 = 0x4800,
413 EEE_TXIDLE_TIMER_8125 = 0x6048,
416 #define LEDSEL_MASK_8125 0x23f
426 SYSErr = 0x8000,
427 PCSTimeout = 0x4000,
428 SWInt = 0x0100,
429 TxDescUnavail = 0x0080,
430 RxFIFOOver = 0x0040,
431 LinkChg = 0x0020,
432 RxOverflow = 0x0010,
433 TxErr = 0x0008,
434 TxOK = 0x0004,
435 RxErr = 0x0002,
436 RxOK = 0x0001,
445 StopReq = 0x80,
446 CmdReset = 0x10,
447 CmdRxEnb = 0x08,
448 CmdTxEnb = 0x04,
449 RxBufEmpty = 0x01,
452 HPQ = 0x80, /* Poll cmd on the high prio queue */
453 NPQ = 0x40, /* Poll cmd on the low prio queue */
454 FSWInt = 0x01, /* Forced software interrupt */
457 Cfg9346_Lock = 0x00,
458 Cfg9346_Unlock = 0xc0,
461 AcceptErr = 0x20,
462 AcceptRunt = 0x10,
463 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
468 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
469 #define RX_CONFIG_ACCEPT_MASK 0x3f
473 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
482 PMEnable = (1 << 0), /* Power Management Enable */
487 PCI_Clock_66MHz = 0x01,
488 PCI_Clock_33MHz = 0x00,
495 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
506 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
507 ASPM_en = (1 << 0), /* ASPM enable */
520 Mac_dbgo_sel = 0x001c, // 8168
525 #define INTT_MASK GENMASK(1, 0)
529 TBI_Enable = 0x80,
530 TxFlowCtrl = 0x40,
531 RxFlowCtrl = 0x20,
532 _1000bpsF = 0x10,
533 _100bps = 0x08,
534 _10bps = 0x04,
535 LinkStatus = 0x02,
536 FullDup = 0x01,
539 CounterReset = 0x1,
542 CounterDump = 0x8,
560 #define TD_MSS_MAX 0x07ffu /* MSS value */
581 #define GTTCPHO_MAX 0x7f
585 #define TCPHO_MAX 0x3ff
596 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
852 for (i = 0; i < ETH_ALEN; i++) in rtl_read_mac_from_reg()
866 for (i = 0; i < n; i++) { in rtl_loop_wait()
908 if (ret < 0) in rtl8168_led_mod_ctrl()
917 return 0; in rtl8168_led_mod_ctrl()
926 if (ret < 0) in rtl8168_get_led_mode()
951 if (ret < 0) in rtl8125_set_led_mode()
961 return 0; in rtl8125_set_led_mode()
971 if (ret < 0) in rtl8125_get_led_mode()
992 pdom[0] = '\0'; in r8169_get_led_name()
997 pfun[0] = '\0'; in r8169_get_led_name()
1007 *cmd |= 0xf70 << 18; in r8168fp_adjust_ocp_cmd()
1020 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) in _rtl_eri_write()
1044 RTL_R32(tp, ERIDR) : ~0; in _rtl_eri_read()
1061 rtl_w0w1_eri(tp, addr, p, 0); in rtl_eri_set_bits()
1066 rtl_w0w1_eri(tp, addr, 0, m); in rtl_eri_clear_bits()
1071 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); in rtl_ocp_reg_failure()
1092 return 0; in r8168_phy_ocp_read()
1097 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; in r8168_phy_ocp_read()
1120 return 0; in __r8168_mac_ocp_read()
1159 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
1161 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
1170 if (reg == 0x1f) { in r8168g_mdio_write()
1176 reg -= 0x10; in r8168g_mdio_write()
1186 if (reg == 0x1f) in r8168g_mdio_read()
1187 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; in r8168g_mdio_read()
1190 reg -= 0x10; in r8168g_mdio_read()
1197 if (reg == 0x1f) { in mac_mcu_write()
1212 return RTL_R32(tp, PHYAR) & 0x80000000; in DECLARE_RTL_COND()
1217 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
1231 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
1234 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; in r8169_mdio_read()
1250 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1254 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
1259 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1277 return 0xc912; in r8168dp_2_mdio_read()
1337 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; in rtl_ephy_read()
1342 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1344 RTL_R32(tp, OCPDR) : ~0; in r8168dp_ocp_read()
1356 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1363 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, in r8168ep_ocp_write()
1369 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); in r8168dp_oob_notify()
1371 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); in r8168dp_oob_notify()
1374 #define OOB_CMD_RESET 0x00
1375 #define OOB_CMD_DRIVER_START 0x05
1376 #define OOB_CMD_DRIVER_STOP 0x06
1380 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; in rtl8168_get_ocp_reg()
1389 return r8168dp_ocp_read(tp, reg) & 0x00000800; in DECLARE_RTL_COND()
1394 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; in DECLARE_RTL_COND()
1399 return RTL_R8(tp, IBISR0) & 0x20; in DECLARE_RTL_COND()
1404 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); in rtl8168ep_stop_cmac()
1406 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); in rtl8168ep_stop_cmac()
1407 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); in rtl8168ep_stop_cmac()
1419 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); in rtl8168ep_driver_start()
1420 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_start()
1427 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START); in rtl8125bp_driver_start()
1428 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); in rtl8125bp_driver_start()
1429 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); in rtl8125bp_driver_start()
1452 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); in rtl8168ep_driver_stop()
1453 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_stop()
1460 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP); in rtl8125bp_driver_stop()
1461 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); in rtl8125bp_driver_stop()
1462 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); in rtl8125bp_driver_stop()
1484 return r8168ep_ocp_read(tp, 0x128) & BIT(0); in r8168ep_check_dash()
1526 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1527 rtl_eri_set_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1540 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; in rtl8168d_efuse_read()
1562 RTL_W32(tp, IntrMask_8125, 0); in rtl_irq_disable()
1564 RTL_W16(tp, IntrMask, 0); in rtl_irq_disable()
1578 rtl_ack_events(tp, 0xffffffff); in rtl8169_irq_mask_and_ack()
1589 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1590 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1592 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1593 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1595 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1596 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1602 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1603 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1605 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1606 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1610 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); in rtl_link_chg_patch()
1611 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); in rtl_link_chg_patch()
1613 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_link_chg_patch()
1634 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1636 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1639 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); in __rtl8169_set_wol()
1641 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); in __rtl8169_set_wol()
1649 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, in __rtl8169_set_wol()
1650 wolopts & WAKE_PHY ? 0x13 : 0); in __rtl8169_set_wol()
1675 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; in __rtl8169_set_wol()
1689 return 0; in rtl8169_set_wol()
1768 return 0; in rtl8169_set_features()
1774 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; in rtl8169_tx_vlan_tag()
1782 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); in rtl8169_rx_vlan_tag()
1793 for (i = 0; i < R8169_REGS_SIZE; i += 4) in rtl8169_get_regs()
1846 * is disabled. If 0xff chip may be in a PCI power-save state. in rtl8169_update_counters()
1848 if (val & CmdRxEnb && val != 0xff) in rtl8169_update_counters()
1896 data[0] = le64_to_cpu(counters->tx_packets); in rtl8169_get_ethtool_stats()
1923 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1931 * (0xe0) bit 1 and bit 0.
1934 * bit[1:0] \ speed 1000M 100M 10M
1935 * 0 0 320ns 2.56us 40.96us
1936 * 0 1 2.56us 20.48us 327.7us
1937 * 1 0 5.12us 40.96us 655.4us
1941 * bit[1:0] \ speed 1000M 100M 10M
1942 * 0 0 5us 2.56us 40.96us
1943 * 0 1 40us 20.48us 327.7us
1944 * 1 0 80us 40.96us 655.4us
1948 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1961 { 0 },
1968 { 0 },
2008 memset(ec, 0, sizeof(*ec)); in rtl_get_coalesce()
2010 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ in rtl_get_coalesce()
2023 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ in rtl_get_coalesce()
2032 return 0; in rtl_get_coalesce()
2035 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
2046 for (i = 0; i < 4; i++) { in rtl_coalesce_choose_scale()
2065 u16 w = 0, cp01 = 0; in rtl_set_coalesce()
2076 if (scale < 0) in rtl_set_coalesce()
2080 * not only when usecs=0 because of e.g. the following scenario: in rtl_set_coalesce()
2082 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) in rtl_set_coalesce()
2083 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 in rtl_set_coalesce()
2087 * if we want to ignore rx_frames then it has to be set to 0. in rtl_set_coalesce()
2090 rx_fr = 0; in rtl_set_coalesce()
2092 tx_fr = 0; in rtl_set_coalesce()
2122 return 0; in rtl_set_coalesce()
2127 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; in rtl_set_eee_txidle_timer()
2133 r8168_mac_ocp_write(tp, 0xe048, timer_val); in rtl_set_eee_txidle_timer()
2150 return 0; in r8169_get_tx_lpi_timer_us()
2170 return 0; in rtl8169_get_eee()
2216 data->tx_pause = tx_pause ? 1 : 0; in rtl8169_get_pauseparam()
2217 data->rx_pause = rx_pause ? 1 : 0; in rtl8169_get_pauseparam()
2230 return 0; in rtl8169_set_pauseparam()
2380 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); in rtl8168_config_eee_mac()
2382 rtl_eri_set_bits(tp, 0x1b0, 0x0003); in rtl8168_config_eee_mac()
2387 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125a_config_eee_mac()
2388 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); in rtl8125a_config_eee_mac()
2393 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125b_config_eee_mac()
2398 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); in rtl_rar_exgmac_set()
2399 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); in rtl_rar_exgmac_set()
2400 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); in rtl_rar_exgmac_set()
2401 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); in rtl_rar_exgmac_set()
2408 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); in rtl8168h_2_get_adc_bias_ioffset()
2409 data1 = r8168_mac_ocp_read(tp, 0xdd02); in rtl8168h_2_get_adc_bias_ioffset()
2410 data2 = r8168_mac_ocp_read(tp, 0xdd00); in rtl8168h_2_get_adc_bias_ioffset()
2412 ioffset = (data2 >> 1) & 0x7ff8; in rtl8168h_2_get_adc_bias_ioffset()
2413 ioffset |= data2 & 0x0007; in rtl8168h_2_get_adc_bias_ioffset()
2432 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); in rtl8169_init_phy()
2433 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); in rtl8169_init_phy()
2434 /* set undocumented MAC Reg C+CR Offset 0x82h */ in rtl8169_init_phy()
2435 RTL_W8(tp, 0x82, 0x01); in rtl8169_init_phy()
2440 tp->pci_dev->subsystem_device == 0xe000) in rtl8169_init_phy()
2441 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); in rtl8169_init_phy()
2476 return 0; in rtl_set_mac_address()
2509 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; in rtl8169_init_ring_indexes()
2524 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); in rtl_jumbo_config()
2534 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); in rtl_jumbo_config()
2536 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); in rtl_jumbo_config()
2616 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; in DECLARE_RTL_COND()
2668 rtl_ephy_write(tp, 0x19, 0xff64); in rtl_prepare_power_down()
2711 val = 0x000fff00; in rtl8169_set_magic_reg()
2713 val = 0x00ffff00; in rtl8169_set_magic_reg()
2718 val |= 0xff; in rtl8169_set_magic_reg()
2720 RTL_W32(tp, 0x7c, val); in rtl8169_set_magic_reg()
2727 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; in rtl_set_rx_mode()
2743 mc_filter[1] = mc_filter[0] = 0; in rtl_set_rx_mode()
2750 tmp = mc_filter[0]; in rtl_set_rx_mode()
2751 mc_filter[0] = swab32(mc_filter[1]); in rtl_set_rx_mode()
2757 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
2787 RTL_R32(tp, CSIDR) : ~0; in rtl_csi_read()
2810 #define RTL_GEN3_RELATED_OFF 0x0890 in rtl_disable_zrxdc_timeout()
2811 #define RTL_GEN3_ZRXDC_NONCOMPL 0x1 in rtl_disable_zrxdc_timeout()
2823 rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0); in rtl_disable_zrxdc_timeout()
2830 /* According to Realtek the value at config space address 0x070f in rtl_set_aspm_entry_latency()
2833 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) in rtl_set_aspm_entry_latency()
2834 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us in rtl_set_aspm_entry_latency()
2836 if (pdev->cfg_size > 0x070f && in rtl_set_aspm_entry_latency()
2837 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) in rtl_set_aspm_entry_latency()
2840 rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24); in rtl_set_aspm_entry_latency()
2846 rtl_set_aspm_entry_latency(tp, 0x27); in rtl_set_def_aspm_entry_latency()
2860 while (len-- > 0) { in __rtl_ephy_init()
2899 rtl_eri_set_bits(tp, 0xd4, 0x1f00); in rtl_enable_exit_l1()
2902 rtl_eri_set_bits(tp, 0xd4, 0x0c00); in rtl_enable_exit_l1()
2905 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); in rtl_enable_exit_l1()
2916 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); in rtl_disable_exit_l1()
2919 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); in rtl_disable_exit_l1()
2942 rtl_mod_config5(tp, 0, ASPM_en); in rtl_hw_aspm_clkreq_enable()
2950 rtl_mod_config2(tp, 0, ClkReqEn); in rtl_hw_aspm_clkreq_enable()
2958 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); in rtl_hw_aspm_clkreq_enable()
2960 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); in rtl_hw_aspm_clkreq_enable()
2969 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); in rtl_hw_aspm_clkreq_enable()
2982 rtl_mod_config2(tp, ClkReqEn, 0); in rtl_hw_aspm_clkreq_enable()
2985 rtl_mod_config5(tp, ASPM_en, 0); in rtl_hw_aspm_clkreq_enable()
2995 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); in rtl_set_fifo_size()
2996 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); in rtl_set_fifo_size()
3003 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); in rtl8168g_set_pause_thresholds()
3004 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); in rtl8168g_set_pause_thresholds()
3024 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168cp_1()
3025 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168cp_1()
3026 { 0x03, 0, 0x0042 }, in rtl_hw_start_8168cp_1()
3027 { 0x06, 0x0080, 0x0000 }, in rtl_hw_start_8168cp_1()
3028 { 0x07, 0, 0x2000 } in rtl_hw_start_8168cp_1()
3052 RTL_W8(tp, DBG_REG, 0x20); in rtl_hw_start_8168cp_3()
3058 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168c_1()
3059 { 0x03, 0, 0x0002 }, in rtl_hw_start_8168c_1()
3060 { 0x06, 0x0080, 0x0000 } in rtl_hw_start_8168c_1()
3065 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); in rtl_hw_start_8168c_1()
3075 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168c_2()
3076 { 0x03, 0x0400, 0x0020 } in rtl_hw_start_8168c_2()
3103 { 0x0b, 0x0000, 0x0048 }, in rtl_hw_start_8168d_4()
3104 { 0x19, 0x0020, 0x0050 }, in rtl_hw_start_8168d_4()
3105 { 0x0c, 0x0100, 0x0020 }, in rtl_hw_start_8168d_4()
3106 { 0x10, 0x0004, 0x0000 }, in rtl_hw_start_8168d_4()
3119 { 0x00, 0x0200, 0x0100 }, in rtl_hw_start_8168e_1()
3120 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_1()
3121 { 0x06, 0x0002, 0x0001 }, in rtl_hw_start_8168e_1()
3122 { 0x06, 0x0000, 0x0030 }, in rtl_hw_start_8168e_1()
3123 { 0x07, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
3124 { 0x00, 0x0000, 0x0020 }, in rtl_hw_start_8168e_1()
3125 { 0x03, 0x5800, 0x2000 }, in rtl_hw_start_8168e_1()
3126 { 0x03, 0x0000, 0x0001 }, in rtl_hw_start_8168e_1()
3127 { 0x01, 0x0800, 0x1000 }, in rtl_hw_start_8168e_1()
3128 { 0x07, 0x0000, 0x4000 }, in rtl_hw_start_8168e_1()
3129 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
3130 { 0x19, 0xffff, 0xfe6c }, in rtl_hw_start_8168e_1()
3131 { 0x0a, 0x0000, 0x0040 } in rtl_hw_start_8168e_1()
3144 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_1()
3150 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168e_2()
3151 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168e_2()
3152 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_2()
3153 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168e_2()
3160 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168e_2()
3161 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168e_2()
3162 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168e_2()
3163 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); in rtl_hw_start_8168e_2()
3165 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168e_2()
3166 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168e_2()
3167 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); in rtl_hw_start_8168e_2()
3177 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_2()
3184 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168f()
3185 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168f()
3186 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168f()
3188 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168f()
3189 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); in rtl_hw_start_8168f()
3190 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168f()
3191 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); in rtl_hw_start_8168f()
3198 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168f()
3206 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8168f_1()
3207 { 0x08, 0x0001, 0x0002 }, in rtl_hw_start_8168f_1()
3208 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168f_1()
3209 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168f_1()
3210 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8168f_1()
3211 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168f_1()
3222 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8411()
3223 { 0x0f, 0xffff, 0x5200 }, in rtl_hw_start_8411()
3224 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8411()
3225 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8411()
3226 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8411()
3237 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168g()
3238 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168g()
3243 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); in rtl_hw_start_8168g()
3247 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3248 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3252 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168g()
3253 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168g()
3261 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_1()
3262 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_1()
3263 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8168g_1()
3264 { 0x19, 0x8000, 0x0000 } in rtl_hw_start_8168g_1()
3274 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_2()
3275 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_2()
3276 { 0x19, 0xffff, 0x7c00 }, in rtl_hw_start_8168g_2()
3277 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8168g_2()
3278 { 0x0d, 0xffff, 0x1666 }, in rtl_hw_start_8168g_2()
3279 { 0x00, 0xffff, 0x10a3 }, in rtl_hw_start_8168g_2()
3280 { 0x06, 0xffff, 0xf050 }, in rtl_hw_start_8168g_2()
3281 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8168g_2()
3282 { 0x1d, 0x4000, 0x0000 }, in rtl_hw_start_8168g_2()
3292 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, in rtl8411b_fix_phy_down()
3293 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, in rtl8411b_fix_phy_down()
3294 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, in rtl8411b_fix_phy_down()
3295 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, in rtl8411b_fix_phy_down()
3296 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, in rtl8411b_fix_phy_down()
3297 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, in rtl8411b_fix_phy_down()
3298 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, in rtl8411b_fix_phy_down()
3299 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, in rtl8411b_fix_phy_down()
3300 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, in rtl8411b_fix_phy_down()
3301 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, in rtl8411b_fix_phy_down()
3302 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, in rtl8411b_fix_phy_down()
3303 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, in rtl8411b_fix_phy_down()
3304 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, in rtl8411b_fix_phy_down()
3305 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 in rtl8411b_fix_phy_down()
3311 for (i = 0; i < ARRAY_SIZE(fix_data); i++) in rtl8411b_fix_phy_down()
3312 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); in rtl8411b_fix_phy_down()
3319 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8411_2()
3320 { 0x0c, 0x37d0, 0x0820 }, in rtl_hw_start_8411_2()
3321 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8411_2()
3322 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8411_2()
3323 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8411_2()
3324 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8411_2()
3325 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8411_2()
3326 { 0x06, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3327 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3328 { 0x1d, 0x0000, 0x4000 }, in rtl_hw_start_8411_2()
3338 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); in rtl_hw_start_8411_2()
3339 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); in rtl_hw_start_8411_2()
3340 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); in rtl_hw_start_8411_2()
3341 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); in rtl_hw_start_8411_2()
3342 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); in rtl_hw_start_8411_2()
3343 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); in rtl_hw_start_8411_2()
3344 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); in rtl_hw_start_8411_2()
3345 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); in rtl_hw_start_8411_2()
3347 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); in rtl_hw_start_8411_2()
3351 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); in rtl_hw_start_8411_2()
3353 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); in rtl_hw_start_8411_2()
3354 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); in rtl_hw_start_8411_2()
3355 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); in rtl_hw_start_8411_2()
3356 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); in rtl_hw_start_8411_2()
3357 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); in rtl_hw_start_8411_2()
3358 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); in rtl_hw_start_8411_2()
3359 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); in rtl_hw_start_8411_2()
3365 { 0x1e, 0x0800, 0x0001 }, in rtl_hw_start_8168h_1()
3366 { 0x1d, 0x0000, 0x0800 }, in rtl_hw_start_8168h_1()
3367 { 0x05, 0xffff, 0x2089 }, in rtl_hw_start_8168h_1()
3368 { 0x06, 0xffff, 0x5881 }, in rtl_hw_start_8168h_1()
3369 { 0x04, 0xffff, 0x854a }, in rtl_hw_start_8168h_1()
3370 { 0x01, 0xffff, 0x068b } in rtl_hw_start_8168h_1()
3376 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168h_1()
3377 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168h_1()
3383 rtl_eri_set_bits(tp, 0xdc, 0x001c); in rtl_hw_start_8168h_1()
3385 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168h_1()
3389 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3390 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3399 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168h_1()
3403 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8168h_1()
3404 if (rg_saw_cnt > 0) { in rtl_hw_start_8168h_1()
3408 sw_cnt_1ms_ini &= 0x0fff; in rtl_hw_start_8168h_1()
3409 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8168h_1()
3412 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8168h_1()
3413 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); in rtl_hw_start_8168h_1()
3414 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); in rtl_hw_start_8168h_1()
3415 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8168h_1()
3417 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8168h_1()
3418 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8168h_1()
3419 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8168h_1()
3420 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8168h_1()
3427 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168ep()
3428 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8168ep()
3434 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168ep()
3438 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3439 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3443 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168ep()
3453 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8168ep_3()
3454 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8168ep_3()
3455 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8168ep_3()
3456 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168ep_3()
3466 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); in rtl_hw_start_8168ep_3()
3467 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8168ep_3()
3468 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8168ep_3()
3474 { 0x19, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3475 { 0x59, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3482 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8117()
3483 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8117()
3489 rtl_eri_set_bits(tp, 0xd4, 0x0010); in rtl_hw_start_8117()
3491 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8117()
3495 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3496 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3505 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8117()
3509 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8117()
3510 if (rg_saw_cnt > 0) { in rtl_hw_start_8117()
3513 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; in rtl_hw_start_8117()
3514 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8117()
3517 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8117()
3518 r8168_mac_ocp_write(tp, 0xea80, 0x0003); in rtl_hw_start_8117()
3519 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); in rtl_hw_start_8117()
3520 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8117()
3522 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8117()
3523 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8117()
3524 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8117()
3525 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8117()
3534 { 0x01, 0, 0x6e65 }, in rtl_hw_start_8102e_1()
3535 { 0x02, 0, 0x091f }, in rtl_hw_start_8102e_1()
3536 { 0x03, 0, 0xc2f9 }, in rtl_hw_start_8102e_1()
3537 { 0x06, 0, 0xafb5 }, in rtl_hw_start_8102e_1()
3538 { 0x07, 0, 0x0e00 }, in rtl_hw_start_8102e_1()
3539 { 0x19, 0, 0xec80 }, in rtl_hw_start_8102e_1()
3540 { 0x01, 0, 0x2e65 }, in rtl_hw_start_8102e_1()
3541 { 0x01, 0, 0x6e65 } in rtl_hw_start_8102e_1()
3572 rtl_ephy_write(tp, 0x03, 0xc2f9); in rtl_hw_start_8102e_3()
3578 { 0x01, 0xffff, 0x6fe5 }, in rtl_hw_start_8401()
3579 { 0x03, 0xffff, 0x0599 }, in rtl_hw_start_8401()
3580 { 0x06, 0xffff, 0xaf25 }, in rtl_hw_start_8401()
3581 { 0x07, 0xffff, 0x8e68 }, in rtl_hw_start_8401()
3591 { 0x07, 0, 0x4000 }, in rtl_hw_start_8105e_1()
3592 { 0x19, 0, 0x0200 }, in rtl_hw_start_8105e_1()
3593 { 0x19, 0, 0x0020 }, in rtl_hw_start_8105e_1()
3594 { 0x1e, 0, 0x2000 }, in rtl_hw_start_8105e_1()
3595 { 0x03, 0, 0x0001 }, in rtl_hw_start_8105e_1()
3596 { 0x19, 0, 0x0100 }, in rtl_hw_start_8105e_1()
3597 { 0x19, 0, 0x0004 }, in rtl_hw_start_8105e_1()
3598 { 0x0a, 0, 0x0020 } in rtl_hw_start_8105e_1()
3602 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
3605 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
3618 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); in rtl_hw_start_8105e_2()
3624 { 0x19, 0xffff, 0xff64 }, in rtl_hw_start_8402()
3625 { 0x1e, 0, 0x4000 } in rtl_hw_start_8402()
3631 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
3637 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); in rtl_hw_start_8402()
3639 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3640 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3641 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); in rtl_hw_start_8402()
3644 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3652 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
3659 rtl_set_aspm_entry_latency(tp, 0x2f); in rtl_hw_start_8106()
3661 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3664 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3671 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); in DECLARE_RTL_COND()
3678 RTL_W16(tp, 0x382, 0x221b); in rtl_hw_start_8125_common()
3679 RTL_W32(tp, RSS_CTRL_8125, 0); in rtl_hw_start_8125_common()
3680 RTL_W16(tp, Q_NUM_CTRL_8125, 0); in rtl_hw_start_8125_common()
3683 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); in rtl_hw_start_8125_common()
3685 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); in rtl_hw_start_8125_common()
3687 r8168_mac_ocp_write(tp, 0xc140, 0xffff); in rtl_hw_start_8125_common()
3688 r8168_mac_ocp_write(tp, 0xc142, 0xffff); in rtl_hw_start_8125_common()
3690 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); in rtl_hw_start_8125_common()
3691 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8125_common()
3692 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8125_common()
3695 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3699 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); in rtl_hw_start_8125_common()
3702 r8168_mac_ocp_modify(tp, 0xe614, 0x0f00, 0x0f00); in rtl_hw_start_8125_common()
3704 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); in rtl_hw_start_8125_common()
3706 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); in rtl_hw_start_8125_common()
3708 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); in rtl_hw_start_8125_common()
3711 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); in rtl_hw_start_8125_common()
3713 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); in rtl_hw_start_8125_common()
3715 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); in rtl_hw_start_8125_common()
3716 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); in rtl_hw_start_8125_common()
3717 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); in rtl_hw_start_8125_common()
3718 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); in rtl_hw_start_8125_common()
3719 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); in rtl_hw_start_8125_common()
3720 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); in rtl_hw_start_8125_common()
3723 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); in rtl_hw_start_8125_common()
3725 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3726 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); in rtl_hw_start_8125_common()
3727 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); in rtl_hw_start_8125_common()
3728 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); in rtl_hw_start_8125_common()
3730 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3731 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); in rtl_hw_start_8125_common()
3733 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3734 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); in rtl_hw_start_8125_common()
3736 r8168_mac_ocp_write(tp, 0xe098, 0xc302); in rtl_hw_start_8125_common()
3751 { 0x04, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3752 { 0x0a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3753 { 0x23, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3754 { 0x20, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3755 { 0x21, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3756 { 0x29, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3758 { 0x44, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3759 { 0x4a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3760 { 0x63, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3761 { 0x60, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3762 { 0x61, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3763 { 0x69, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3774 { 0x0b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3775 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3776 { 0x4b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3777 { 0x5e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3778 { 0x22, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3779 { 0x62, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3860 RTL_W8(tp, INT_CFG0_8125, 0x00); in rtl_hw_start_8125()
3868 for (i = 0xa00; i < 0xb00; i += 4) in rtl_hw_start_8125()
3869 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3871 RTL_W16(tp, INT_CFG1_8125, 0x0000); in rtl_hw_start_8125()
3875 for (i = 0xa00; i < 0xa80; i += 4) in rtl_hw_start_8125()
3876 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3877 RTL_W16(tp, INT_CFG1_8125, 0x0000); in rtl_hw_start_8125()
3884 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); in rtl_hw_start_8125()
3899 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8168()
3917 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8169()
3964 return 0; in rtl8169_change_mtu()
3971 desc->opts2 = 0; in rtl8169_mark_to_asic()
3989 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); in rtl8169_alloc_rx_data()
4006 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { in rtl8169_rx_clear()
4012 tp->RxDescArray[i].addr = 0; in rtl8169_rx_clear()
4013 tp->RxDescArray[i].opts1 = 0; in rtl8169_rx_clear()
4021 for (i = 0; i < NUM_RX_DESC; i++) { in rtl8169_rx_fill()
4035 return 0; in rtl8169_rx_fill()
4042 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); in rtl8169_init_ring()
4043 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); in rtl8169_init_ring()
4055 memset(desc, 0, sizeof(*desc)); in rtl8169_unmap_tx_skb()
4056 memset(tx_skb, 0, sizeof(*tx_skb)); in rtl8169_unmap_tx_skb()
4064 for (i = 0; i < n; i++) { in rtl8169_tx_clear_range()
4130 for (i = 0; i < NUM_RX_DESC; i++) in rtl_reset_work()
4164 opts1 = opts[0] | len; in rtl8169_tx_map()
4173 return 0; in rtl8169_tx_map()
4182 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { in rtl8169_xmit_frags()
4193 return 0; in rtl8169_xmit_frags()
4224 unsigned int padto = 0, len = skb->len; in rtl8125_quirk_udp_padto()
4251 unsigned int padto = 0; in rtl_quirk_packet_padto()
4278 opts[0] |= TD_LSO; in rtl8169_tso_csum_v1()
4279 opts[0] |= mss << TD0_MSS_SHIFT; in rtl8169_tso_csum_v1()
4284 opts[0] |= TD0_IP_CS | TD0_TCP_CS; in rtl8169_tso_csum_v1()
4286 opts[0] |= TD0_IP_CS | TD0_UDP_CS; in rtl8169_tso_csum_v1()
4300 opts[0] |= TD1_GTSENV4; in rtl8169_tso_csum_v2()
4302 if (skb_cow_head(skb, 0)) in rtl8169_tso_csum_v2()
4306 opts[0] |= TD1_GTSENV6; in rtl8169_tso_csum_v2()
4311 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; in rtl8169_tso_csum_v2()
4370 RTL_W16(tp, TxPoll_8125, BIT(0)); in rtl8169_doorbell()
4393 opts[0] = 0; in rtl8169_start_xmit()
4431 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), in rtl8169_start_xmit()
4519 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", in rtl8169_pcierr_interrupt()
4528 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; in rtl_tx()
4556 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, in rtl_tx()
4592 for (count = 0; count < budget; count++, tp->cur_rx++) { in rtl_rx()
4626 pkt_size = status & GENMASK(13, 0); in rtl_rx()
4678 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) in rtl8169_interrupt()
4707 if (RTL_R32(tp, TxConfig) == ~0) { in rtl_task()
4709 if (ret < 0) { in rtl_task()
4781 return 0; in r8169_phy_connect()
4845 return 0; in rtl8169_close()
4881 if (retval < 0) in rtl_open()
4888 if (retval < 0) in rtl_open()
4974 return 0; in rtl8169_runtime_resume()
4987 return 0; in rtl8169_suspend()
5010 return 0; in rtl8169_runtime_suspend()
5018 return 0; in rtl8169_runtime_suspend()
5134 value = rtl_eri_read(tp, 0xe0); in rtl_read_mac_address()
5136 value = rtl_eri_read(tp, 0xe4); in rtl_read_mac_address()
5157 if (phyaddr > 0) in r8169_mdio_read_reg()
5168 if (phyaddr > 0) in r8169_mdio_write_reg()
5173 return 0; in r8169_mdio_write_reg()
5181 if (addr > 0) in r8169_mdio_read_reg_c45()
5187 return 0; in r8169_mdio_read_reg_c45()
5195 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2) in r8169_mdio_write_reg_c45()
5200 return 0; in r8169_mdio_write_reg_c45()
5216 r8169_mdio_write(tp, 0x1f, 0); in r8169_mdio_register()
5225 new_bus->irq[0] = PHY_MAC_INTERRUPT; in r8169_mdio_register()
5242 tp->phydev = mdiobus_get_phy(new_bus, 0); in r8169_mdio_register()
5249 …dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be… in r8169_mdio_register()
5267 return 0; in r8169_mdio_register()
5278 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8168g()
5281 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); in rtl_hw_init_8168g()
5293 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8125()
5296 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); in rtl_hw_init_8125()
5297 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); in rtl_hw_init_8125()
5298 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); in rtl_hw_init_8125()
5323 return 0; in rtl_jumbo_max()
5373 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) in rtl_aspm_is_safe()
5397 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; in rtl_init_one()
5410 if (rc < 0) in rtl_init_one()
5413 if (pcim_set_mwi(pdev) < 0) in rtl_init_one()
5418 if (region < 0) in rtl_init_one()
5427 if (txconfig == ~0U) in rtl_init_one()
5430 xid = (txconfig >> 20) & 0xfcf; in rtl_init_one()
5445 rc = 0; in rtl_init_one()
5468 if (rc < 0) in rtl_init_one()
5471 tp->irq = pci_irq_vector(pdev, 0); in rtl_init_one()
5584 return 0; in rtl_init_one()