Lines Matching +full:0 +full:xc8000
41 #define QLCNIC_DRV_IDC_VER 0x01
46 #define _major(v) (((v) >> 24) & 0xff)
47 #define _minor(v) (((v) >> 16) & 0xff)
48 #define _build(v) ((v) & 0xffff)
51 * 7:0 - major
56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
75 #define QLCNIC_P3P_A0 0x50
76 #define QLCNIC_P3P_C0 0x58
80 #define FIRST_PAGE_GROUP_START 0
81 #define FIRST_PAGE_GROUP_END 0x100000
115 #define QLCNIC_VNIC_MODE 0xFF
116 #define QLCNIC_DEFAULT_MODE 0x0
126 #define PHAN_INITIALIZE_FAILED 0xffff
127 #define PHAN_INITIALIZE_COMPLETE 0xff01
130 #define PHAN_INITIALIZE_ACK 0xf00f
131 #define PHAN_PEG_RCV_INITIALIZED 0xff01
135 #define RCV_RING_NORMAL 0
165 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
166 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
174 * 3 Inner L4 type, TCP=0, UDP=1,
175 * 2 Inner L3 type, IPv4=0, IPv6=1,
176 * 1 Outer L3 type,IPv4=0, IPv6=1,
177 * 0 type of encapsulation, GRE=0, VXLAN=1
180 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
212 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
213 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
214 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
215 #define QLCNIC_UNI_DIR_SECT_FW 0x7
238 #define QLCNIC_FLT_LOCATION 0x3F1000
239 #define QLCNIC_FDT_LOCATION 0x3F0000
240 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
241 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
242 #define QLCNIC_BOOTLD_REGION 0X72
291 #define QLCNIC_BDINFO_MAGIC 0x12345678
293 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
294 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
295 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
296 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
297 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
298 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
299 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
300 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
301 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
302 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
303 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
304 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
305 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
306 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
308 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
311 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
312 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
313 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
314 #define QLCNIC_USER_START 0x3E8000 /* Firmware info */
316 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
317 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
318 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
319 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
321 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
322 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
324 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
325 #define QLCNIC_UNIFIED_ROMIMAGE 0
327 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
352 #define QLCNIC_BUFFER_FREE 0
374 #define QLCNIC_GBE 0x01
375 #define QLCNIC_XGBE 0x02
391 #define QLCNIC_INTR_DEFAULT 0x04
658 #define QLCNIC_CDRP_CMD_BIT 0x80000000
665 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
667 #define QLCNIC_CDRP_RSP_OK 0x00000001
668 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
669 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
677 #define QLCNIC_RCODE_SUCCESS 0
684 #define QLCNIC_DESTROY_CTX_RESET 0
701 #define QLCNIC_HOST_CTX_STATE_FREED 0
727 /* These ring offsets are relative to data[0] below */
754 /* These ring offsets are relative to data[0] below */
826 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
831 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
842 #define QLCNIC_MAC_NOOP 0
862 #define NO_MAC_LEARN 0
866 #define QLCNIC_HOST_REQUEST 0x13
867 #define QLCNIC_REQUEST 0x14
869 #define QLCNIC_MAC_EVENT 0x1
874 #define QLCNIC_ILB_MODE 0x1
875 #define QLCNIC_ELB_MODE 0x2
876 #define QLCNIC_LB_MODE_MASK 0x3
878 #define QLCNIC_LINKEVENT 0x1
879 #define QLCNIC_LB_RESPONSE 0x2
886 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
887 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
888 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
889 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
890 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
891 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
893 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
894 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
895 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
896 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
902 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
903 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
904 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90
906 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
947 #define LINKSPEED_ENCODED_10MBPS 0
951 #define LINKEVENT_AUTONEG_DISABLED 0
954 #define LINKEVENT_HALF_DUPLEX 0
957 #define LINKEVENT_LINKSPEED_MBPS 0
971 ((msg_hdr >> 32) & 0xFF)
1005 #define QLCNIC_MSI_ENABLED 0x02
1006 #define QLCNIC_MSIX_ENABLED 0x04
1007 #define QLCNIC_LRO_ENABLED 0x01
1008 #define QLCNIC_LRO_DISABLED 0x00
1009 #define QLCNIC_BRIDGE_ENABLED 0X10
1010 #define QLCNIC_DIAG_ENABLED 0x20
1011 #define QLCNIC_ESWITCH_ENABLED 0x40
1012 #define QLCNIC_ADAPTER_INITIALIZED 0x80
1013 #define QLCNIC_TAGGING_ENABLED 0x100
1014 #define QLCNIC_MACSPOOF 0x200
1015 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
1016 #define QLCNIC_PROMISC_DISABLED 0x800
1017 #define QLCNIC_NEED_FLR 0x1000
1018 #define QLCNIC_FW_RESET_OWNER 0x2000
1019 #define QLCNIC_FW_HANG 0x4000
1020 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
1021 #define QLCNIC_TX_INTR_SHARED 0x10000
1022 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
1023 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000
1024 #define QLCNIC_TSS_RSS 0x80000
1026 #define QLCNIC_VLAN_FILTERING 0x800000
1033 #define QLCNIC_BEACON_EANBLE 0xC
1034 #define QLCNIC_BEACON_DISABLE 0xD
1037 #define QLCNIC_BEACON_OFF 0
1040 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
1045 #define __QLCNIC_FW_ATTACHED 0
1190 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1376 #define QLCNIC_QUERY_RX_COUNTER 0
1378 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1380 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1392 } while (0)
1507 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1508 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1509 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1510 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1511 #define QLCNIC_SET_QUIESCENT 0xadd00010
1512 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1562 qlcnic_pcie_sem_lock((a), 6, 0)
1570 #define __QLCNIC_MAX_LED_RATE 0xf
1571 #define __QLCNIC_MAX_LED_STATE 0x2
1831 return adapter->ahw->extra_capability[0] & in qlcnic_83xx_encap_tx_offload()
1837 return adapter->ahw->extra_capability[0] & in qlcnic_83xx_encap_rx_offload()
2168 writel(0x0, tx_ring->crb_intr_mask); in qlcnic_82xx_enable_tx_intr()
2184 writel(0, tx_ring->crb_intr_mask); in qlcnic_83xx_enable_tx_intr()
2199 writel(0, sds_ring->crb_intr_mask); in qlcnic_83xx_enable_sds_intr()
2216 /* When operating in a muti tx mode, driver needs to write 0x1
2217 * to src register, instead of 0x0 to disable receiving interrupt.
2226 writel(0x1, sds_ring->crb_intr_mask); in qlcnic_82xx_disable_sds_intr()
2228 writel(0, sds_ring->crb_intr_mask); in qlcnic_82xx_disable_sds_intr()
2260 /* When operating in a muti tx mode, driver needs to write 0x0
2261 * to src register, instead of 0x1 to enable receiving interrupts.
2270 writel(0, sds_ring->crb_intr_mask); in qlcnic_82xx_enable_sds_intr()
2272 writel(0x1, sds_ring->crb_intr_mask); in qlcnic_82xx_enable_sds_intr()
2275 writel(0xfbff, adapter->tgt_mask_reg); in qlcnic_82xx_enable_sds_intr()
2302 } while (0)
2304 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
2305 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
2306 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
2307 #define PCI_DEVICE_ID_QLOGIC_QLE8830 0x8830
2308 #define PCI_DEVICE_ID_QLOGIC_VF_QLE8C30 0x8C30
2309 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040
2310 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
2397 for (i = 0; i < count; i++) { in qlcnic_swap32_buffer()