Lines Matching +full:de +full:- +full:assertion
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
12 #include <linux/dma-mapping.h>
92 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); in qed_mcp_attn_cb()
95 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", in qed_mcp_attn_cb()
97 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, in qed_mcp_attn_cb()
118 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_pswhst_attn_cb()
124 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_pswhst_attn_cb()
126 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_pswhst_attn_cb()
128 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_pswhst_attn_cb()
131 DP_INFO(p_hwfn->cdev, in qed_pswhst_attn_cb()
132 …"Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%… in qed_pswhst_attn_cb()
187 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_grc_attn_cb()
193 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_grc_attn_cb()
195 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_grc_attn_cb()
198 DP_INFO(p_hwfn->cdev, in qed_grc_attn_cb()
199 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", in qed_grc_attn_cb()
211 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, in qed_grc_attn_cb()
301 snprintf(msg, sizeof(msg), "ICPL error - %08x", tmp); in qed_pglueb_rbc_attn_handler()
318 DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", in qed_pglueb_rbc_attn_handler()
334 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", in qed_pglueb_rbc_attn_handler()
346 return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false); in qed_pglueb_rbc_attn_cb()
351 qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT, in qed_fw_assertion()
352 "FW assertion!\n"); in qed_fw_assertion()
355 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MISC_REG_AEU_GENERAL_ATTN_32, 0); in qed_fw_assertion()
357 return -EINVAL; in qed_fw_assertion()
395 while (count-- && usage) { in qed_db_rec_flush_queue()
402 DP_NOTICE(p_hwfn->cdev, in qed_db_rec_flush_queue()
405 return -EBUSY; in qed_db_rec_flush_queue()
417 &p_hwfn->db_recovery_info.overflow); in qed_db_rec_handler()
425 if (cur_ovfl && !p_hwfn->db_bar_no_edpm) { in qed_db_rec_handler()
442 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; in qed_dorq_attn_overflow()
451 set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow); in qed_dorq_attn_overflow()
453 if (!p_hwfn->db_bar_no_edpm) { in qed_dorq_attn_overflow()
468 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; in qed_dorq_attn_int_sts()
472 DP_NOTICE(p_hwfn->cdev, in qed_dorq_attn_int_sts()
486 DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); in qed_dorq_attn_int_sts()
502 DP_NOTICE(p_hwfn->cdev, in qed_dorq_attn_int_sts()
533 /* Some other indication was present - non recoverable */ in qed_dorq_attn_int_sts()
536 return -EINVAL; in qed_dorq_attn_int_sts()
541 if (p_hwfn->cdev->recov_in_prog) in qed_dorq_attn_cb()
544 p_hwfn->db_recovery_info.dorq_attn = true; in qed_dorq_attn_cb()
552 if (p_hwfn->db_recovery_info.dorq_attn) in qed_dorq_attn_handler()
558 p_hwfn->db_recovery_info.dorq_attn = false; in qed_dorq_attn_handler()
561 /* Instead of major changes to the data-structure, we have a some 'special'
652 {"MSTAT per-path", ATTENTION_PAR_INT,
756 {"PERST_B assertion", ATTENTION_SINGLE,
785 if (!QED_IS_BB(p_hwfn->cdev)) in qed_int_aeu_translate()
788 if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) in qed_int_aeu_translate()
791 return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> in qed_int_aeu_translate()
798 return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & in qed_int_is_parity_flag()
830 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); in qed_attn_update_idx()
831 if (p_sb_desc->index != index) { in qed_attn_update_idx()
832 p_sb_desc->index = index; in qed_attn_update_idx()
840 * qed_int_assertion() - Handle asserted attention bits.
849 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; in qed_int_assertion()
853 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); in qed_int_assertion()
854 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", in qed_int_assertion()
857 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); in qed_int_assertion()
860 "inner known ATTN state: 0x%04x --> 0x%04x\n", in qed_int_assertion()
861 sb_attn_sw->known_attn, in qed_int_assertion()
862 sb_attn_sw->known_attn | asserted_bits); in qed_int_assertion()
863 sb_attn_sw->known_attn |= asserted_bits; in qed_int_assertion()
867 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); in qed_int_assertion()
869 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, in qed_int_assertion()
870 sb_attn_sw->mfw_attn_addr, 0); in qed_int_assertion()
873 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + in qed_int_assertion()
875 ((IGU_CMD_ATTN_BIT_SET_UPPER - in qed_int_assertion()
894 status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, in qed_int_attn_print()
905 * qed_int_deassertion_aeu_bit() - Handles the effects of a single
924 int rc = -EINVAL; in qed_int_deassertion_aeu_bit()
931 if (p_aeu->cb) { in qed_int_deassertion_aeu_bit()
934 rc = p_aeu->cb(p_hwfn); in qed_int_deassertion_aeu_bit()
941 if (p_aeu->block_index != MAX_BLOCK_ID) in qed_int_deassertion_aeu_bit()
942 qed_int_attn_print(p_hwfn, p_aeu->block_index, in qed_int_deassertion_aeu_bit()
945 /* Reach assertion if attention is fatal */ in qed_int_deassertion_aeu_bit()
947 qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_HW_ATTN, in qed_int_deassertion_aeu_bit()
954 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); in qed_int_deassertion_aeu_bit()
955 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); in qed_int_deassertion_aeu_bit()
956 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", in qed_int_deassertion_aeu_bit()
959 /* Re-enable FW aassertion (Gen 32) interrupts */ in qed_int_deassertion_aeu_bit()
960 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_int_deassertion_aeu_bit()
963 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, in qed_int_deassertion_aeu_bit()
971 * qed_int_deassertion_parity() - Handle a single parity AEU source.
976 * @bit_index: Index (0-31) of an AEU bit.
982 u32 block_id = p_aeu->block_index, mask, val; in qed_int_deassertion_parity()
984 DP_NOTICE(p_hwfn->cdev, in qed_int_deassertion_parity()
986 p_aeu->bit_name, aeu_en_reg, bit_index); in qed_int_deassertion_parity()
1000 /* Prevent this parity error from being re-asserted */ in qed_int_deassertion_parity()
1002 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); in qed_int_deassertion_parity()
1003 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); in qed_int_deassertion_parity()
1004 DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", in qed_int_deassertion_parity()
1005 p_aeu->bit_name); in qed_int_deassertion_parity()
1009 * qed_int_deassertion() - Handle deassertion of previously asserted
1020 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; in qed_int_deassertion()
1027 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, in qed_int_deassertion()
1037 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; in qed_int_deassertion()
1041 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); in qed_int_deassertion()
1044 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; in qed_int_deassertion()
1049 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; in qed_int_deassertion()
1056 bit_idx += ATTENTION_LENGTH(p_bit->flags); in qed_int_deassertion()
1060 /* Find non-parity cause for attention and act */ in qed_int_deassertion()
1075 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); in qed_int_deassertion()
1084 * previous assertion. in qed_int_deassertion()
1090 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; in qed_int_deassertion()
1094 bit_len = ATTENTION_LENGTH(p_aeu->flags); in qed_int_deassertion()
1098 bit_len--; in qed_int_deassertion()
1101 bitmask = bits & (((1 << bit_len) - 1) << bit); in qed_int_deassertion()
1105 u32 flags = p_aeu->flags; in qed_int_deassertion()
1120 p_aeu->bit_name, num); in qed_int_deassertion()
1123 p_aeu->bit_name, 30); in qed_int_deassertion()
1138 bit_idx += ATTENTION_LENGTH(p_aeu->flags); in qed_int_deassertion()
1147 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + in qed_int_deassertion()
1149 ((IGU_CMD_ATTN_BIT_CLR_UPPER - in qed_int_deassertion()
1154 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); in qed_int_deassertion()
1156 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); in qed_int_deassertion()
1159 sb_attn_sw->known_attn &= ~deasserted_bits; in qed_int_deassertion()
1166 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; in qed_int_attentions()
1167 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; in qed_int_attentions()
1173 /* Read current attention bits/acks - safeguard against attentions in qed_int_attentions()
1177 index = p_sb_attn->sb_index; in qed_int_attentions()
1180 attn_bits = le32_to_cpu(p_sb_attn->atten_bits); in qed_int_attentions()
1181 attn_acks = le32_to_cpu(p_sb_attn->atten_ack); in qed_int_attentions()
1182 } while (index != p_sb_attn->sb_index); in qed_int_attentions()
1183 p_sb_attn->sb_index = index; in qed_int_attentions()
1186 * only when they differ and consistent with known state - deassertion in qed_int_attentions()
1187 * when previous attention & current ack, and assertion when current in qed_int_attentions()
1191 ~p_sb_attn_sw->known_attn; in qed_int_attentions()
1193 p_sb_attn_sw->known_attn; in qed_int_attentions()
1197 …"Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev.… in qed_int_attentions()
1199 deasserted_bits, p_sb_attn_sw->known_attn); in qed_int_attentions()
1234 * Need to guarantee all commands will be received (in-order) by HW. in qed_sb_ack_attn()
1248 if (!p_hwfn->p_sp_sb) { in qed_int_sp_dpc()
1249 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); in qed_int_sp_dpc()
1253 sb_info = &p_hwfn->p_sp_sb->sb_info; in qed_int_sp_dpc()
1254 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); in qed_int_sp_dpc()
1256 DP_ERR(p_hwfn->cdev, in qed_int_sp_dpc()
1257 "Status block is NULL - cannot ack interrupts\n"); in qed_int_sp_dpc()
1261 if (!p_hwfn->p_sb_attn) { in qed_int_sp_dpc()
1262 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); in qed_int_sp_dpc()
1265 sb_attn = p_hwfn->p_sb_attn; in qed_int_sp_dpc()
1268 p_hwfn, p_hwfn->my_id); in qed_int_sp_dpc()
1271 * inta in non-mask mode, in inta does no harm. in qed_int_sp_dpc()
1276 if (!sb_info->sb_virt) { in qed_int_sp_dpc()
1277 DP_ERR(p_hwfn->cdev, in qed_int_sp_dpc()
1278 "Interrupt Status block is NULL - cannot check for new interrupts!\n"); in qed_int_sp_dpc()
1280 u32 tmp_index = sb_info->sb_ack; in qed_int_sp_dpc()
1283 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, in qed_int_sp_dpc()
1284 "Interrupt indices: 0x%08x --> 0x%08x\n", in qed_int_sp_dpc()
1285 tmp_index, sb_info->sb_ack); in qed_int_sp_dpc()
1288 if (!sb_attn || !sb_attn->sb_attn) { in qed_int_sp_dpc()
1289 DP_ERR(p_hwfn->cdev, in qed_int_sp_dpc()
1290 "Attentions Status block is NULL - cannot check for new attentions!\n"); in qed_int_sp_dpc()
1292 u16 tmp_index = sb_attn->index; in qed_int_sp_dpc()
1295 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, in qed_int_sp_dpc()
1296 "Attention indices: 0x%08x --> 0x%08x\n", in qed_int_sp_dpc()
1297 tmp_index, sb_attn->index); in qed_int_sp_dpc()
1307 if (!p_hwfn->p_dpc_ptt) { in qed_int_sp_dpc()
1308 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); in qed_int_sp_dpc()
1321 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; in qed_int_sp_dpc()
1322 if (pi_info->comp_cb) in qed_int_sp_dpc()
1323 pi_info->comp_cb(p_hwfn, pi_info->cookie); in qed_int_sp_dpc()
1331 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); in qed_int_sp_dpc()
1338 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; in qed_int_sb_attn_free()
1343 if (p_sb->sb_attn) in qed_int_sb_attn_free()
1344 dma_free_coherent(&p_hwfn->cdev->pdev->dev, in qed_int_sb_attn_free()
1346 p_sb->sb_attn, p_sb->sb_phys); in qed_int_sb_attn_free()
1348 p_hwfn->p_sb_attn = NULL; in qed_int_sb_attn_free()
1354 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; in qed_int_sb_attn_setup()
1356 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); in qed_int_sb_attn_setup()
1358 sb_info->index = 0; in qed_int_sb_attn_setup()
1359 sb_info->known_attn = 0; in qed_int_sb_attn_setup()
1363 lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); in qed_int_sb_attn_setup()
1365 upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); in qed_int_sb_attn_setup()
1372 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; in qed_int_sb_attn_init()
1375 sb_info->sb_attn = sb_virt_addr; in qed_int_sb_attn_init()
1376 sb_info->sb_phys = sb_phy_addr; in qed_int_sb_attn_init()
1379 sb_info->p_aeu_desc = aeu_descs; in qed_int_sb_attn_init()
1382 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); in qed_int_sb_attn_init()
1390 sb_info->parity_mask[i] |= 1 << k; in qed_int_sb_attn_init()
1392 k += ATTENTION_LENGTH(p_aeu->flags); in qed_int_sb_attn_init()
1396 i, sb_info->parity_mask[i]); in qed_int_sb_attn_init()
1400 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + in qed_int_sb_attn_init()
1409 struct qed_dev *cdev = p_hwfn->cdev; in qed_int_sb_attn_alloc()
1417 return -ENOMEM; in qed_int_sb_attn_alloc()
1420 p_virt = dma_alloc_coherent(&cdev->pdev->dev, in qed_int_sb_attn_alloc()
1426 return -ENOMEM; in qed_int_sb_attn_alloc()
1430 p_hwfn->p_sb_attn = p_sb; in qed_int_sb_attn_alloc()
1444 struct qed_dev *cdev = p_hwfn->cdev; in qed_init_cau_sb_entry()
1458 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { in qed_init_cau_sb_entry()
1460 if (!cdev->rx_coalesce_usecs) in qed_init_cau_sb_entry()
1461 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; in qed_init_cau_sb_entry()
1462 if (!cdev->tx_coalesce_usecs) in qed_init_cau_sb_entry()
1463 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; in qed_init_cau_sb_entry()
1466 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ in qed_init_cau_sb_entry()
1467 if (cdev->rx_coalesce_usecs <= 0x7F) in qed_init_cau_sb_entry()
1469 else if (cdev->rx_coalesce_usecs <= 0xFF) in qed_init_cau_sb_entry()
1476 if (cdev->tx_coalesce_usecs <= 0x7F) in qed_init_cau_sb_entry()
1478 else if (cdev->tx_coalesce_usecs <= 0xFF) in qed_init_cau_sb_entry()
1484 p_sb_entry->params = cpu_to_le32(params); in qed_init_cau_sb_entry()
1488 p_sb_entry->data = cpu_to_le32(data); in qed_init_cau_sb_entry()
1501 if (IS_VF(p_hwfn->cdev)) in qed_int_cau_conf_pi()
1513 if (p_hwfn->hw_init_done) in qed_int_cau_conf_pi()
1528 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, in qed_int_cau_conf_sb()
1531 if (p_hwfn->hw_init_done) { in qed_int_cau_conf_sb()
1532 /* Wide-bus, initialize via DMAE */ in qed_int_cau_conf_sb()
1555 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { in qed_int_cau_conf_sb()
1556 u8 num_tc = p_hwfn->hw_info.num_hw_tc; in qed_int_cau_conf_sb()
1560 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ in qed_int_cau_conf_sb()
1561 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) in qed_int_cau_conf_sb()
1563 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) in qed_int_cau_conf_sb()
1567 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); in qed_int_cau_conf_sb()
1571 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) in qed_int_cau_conf_sb()
1573 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) in qed_int_cau_conf_sb()
1577 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); in qed_int_cau_conf_sb()
1591 sb_info->sb_ack = 0; in qed_int_sb_setup()
1592 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); in qed_int_sb_setup()
1594 if (IS_PF(p_hwfn->cdev)) in qed_int_sb_setup()
1595 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, in qed_int_sb_setup()
1596 sb_info->igu_sb_id, 0, 0); in qed_int_sb_setup()
1604 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); in qed_get_igu_free_sb()
1606 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; in qed_get_igu_free_sb()
1608 if (!(p_block->status & QED_IGU_STATUS_VALID) || in qed_get_igu_free_sb()
1609 !(p_block->status & QED_IGU_STATUS_FREE)) in qed_get_igu_free_sb()
1612 if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) in qed_get_igu_free_sb()
1624 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); in qed_get_pf_igu_sb_id()
1626 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; in qed_get_pf_igu_sb_id()
1628 if (!(p_block->status & QED_IGU_STATUS_VALID) || in qed_get_pf_igu_sb_id()
1629 !p_block->is_pf || in qed_get_pf_igu_sb_id()
1630 p_block->vector_number != vector_id) in qed_get_pf_igu_sb_id()
1645 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; in qed_get_igu_sb_id()
1646 else if (IS_PF(p_hwfn->cdev)) in qed_get_igu_sb_id()
1656 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); in qed_get_igu_sb_id()
1666 sb_info->sb_virt = sb_virt_addr; in qed_int_sb_init()
1667 sb_info->sb_phys = sb_phy_addr; in qed_int_sb_init()
1669 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); in qed_int_sb_init()
1672 if (IS_PF(p_hwfn->cdev)) { in qed_int_sb_init()
1676 p_info = p_hwfn->hw_info.p_igu_info; in qed_int_sb_init()
1677 p_block = &p_info->entry[sb_info->igu_sb_id]; in qed_int_sb_init()
1679 p_block->sb_info = sb_info; in qed_int_sb_init()
1680 p_block->status &= ~QED_IGU_STATUS_FREE; in qed_int_sb_init()
1681 p_info->usage.free_cnt--; in qed_int_sb_init()
1687 sb_info->cdev = p_hwfn->cdev; in qed_int_sb_init()
1692 if (IS_PF(p_hwfn->cdev)) { in qed_int_sb_init()
1693 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + in qed_int_sb_init()
1695 (sb_info->igu_sb_id << 3); in qed_int_sb_init()
1697 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + in qed_int_sb_init()
1700 sb_info->igu_sb_id) << 3); in qed_int_sb_init()
1703 sb_info->flags |= QED_SB_INFO_INIT; in qed_int_sb_init()
1720 sb_info->sb_ack = 0; in qed_int_sb_release()
1721 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); in qed_int_sb_release()
1723 if (IS_VF(p_hwfn->cdev)) { in qed_int_sb_release()
1728 p_info = p_hwfn->hw_info.p_igu_info; in qed_int_sb_release()
1729 p_block = &p_info->entry[sb_info->igu_sb_id]; in qed_int_sb_release()
1732 if (!p_block->vector_number) { in qed_int_sb_release()
1734 return -EINVAL; in qed_int_sb_release()
1738 p_block->sb_info = NULL; in qed_int_sb_release()
1739 p_block->status |= QED_IGU_STATUS_FREE; in qed_int_sb_release()
1740 p_info->usage.free_cnt++; in qed_int_sb_release()
1747 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; in qed_int_sp_sb_free()
1752 if (p_sb->sb_info.sb_virt) in qed_int_sp_sb_free()
1753 dma_free_coherent(&p_hwfn->cdev->pdev->dev, in qed_int_sp_sb_free()
1755 p_sb->sb_info.sb_virt, in qed_int_sp_sb_free()
1756 p_sb->sb_info.sb_phys); in qed_int_sp_sb_free()
1758 p_hwfn->p_sp_sb = NULL; in qed_int_sp_sb_free()
1770 return -ENOMEM; in qed_int_sp_sb_alloc()
1773 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, in qed_int_sp_sb_alloc()
1778 return -ENOMEM; in qed_int_sp_sb_alloc()
1782 p_hwfn->p_sp_sb = p_sb; in qed_int_sp_sb_alloc()
1783 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, in qed_int_sp_sb_alloc()
1786 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); in qed_int_sp_sb_alloc()
1795 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; in qed_int_register_cb()
1796 int rc = -ENOMEM; in qed_int_register_cb()
1800 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { in qed_int_register_cb()
1801 if (p_sp_sb->pi_info_arr[pi].comp_cb) in qed_int_register_cb()
1804 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; in qed_int_register_cb()
1805 p_sp_sb->pi_info_arr[pi].cookie = cookie; in qed_int_register_cb()
1807 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; in qed_int_register_cb()
1817 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; in qed_int_unregister_cb()
1819 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) in qed_int_unregister_cb()
1820 return -ENOMEM; in qed_int_unregister_cb()
1822 p_sp_sb->pi_info_arr[pi].comp_cb = NULL; in qed_int_unregister_cb()
1823 p_sp_sb->pi_info_arr[pi].cookie = NULL; in qed_int_unregister_cb()
1830 return p_hwfn->p_sp_sb->sb_info.igu_sb_id; in qed_int_get_sp_sb_id()
1838 p_hwfn->cdev->int_mode = int_mode; in qed_int_igu_enable_int()
1839 switch (p_hwfn->cdev->int_mode) { in qed_int_igu_enable_int()
1886 return -EINVAL; in qed_int_igu_enable()
1888 p_hwfn->b_int_requested = true; in qed_int_igu_enable()
1892 p_hwfn->b_int_enabled = 1; in qed_int_igu_enable()
1899 p_hwfn->b_int_enabled = 0; in qed_int_igu_disable_int()
1901 if (IS_VF(p_hwfn->cdev)) in qed_int_igu_disable_int()
1947 } while (--sleep_cnt); in qed_int_igu_cleanup_sb()
1962 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; in qed_int_igu_init_pure_rt_single()
1966 p_block->function_id, in qed_int_igu_init_pure_rt_single()
1967 p_block->is_pf, p_block->vector_number); in qed_int_igu_init_pure_rt_single()
2003 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; in qed_int_igu_init_pure_rt()
2014 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { in qed_int_igu_init_pure_rt()
2015 p_block = &p_info->entry[igu_sb_id]; in qed_int_igu_init_pure_rt()
2017 if (!(p_block->status & QED_IGU_STATUS_VALID) || in qed_int_igu_init_pure_rt()
2018 !p_block->is_pf || in qed_int_igu_init_pure_rt()
2019 (p_block->status & QED_IGU_STATUS_DSB)) in qed_int_igu_init_pure_rt()
2023 p_hwfn->hw_info.opaque_fid, in qed_int_igu_init_pure_rt()
2029 p_info->igu_dsb_id, in qed_int_igu_init_pure_rt()
2030 p_hwfn->hw_info.opaque_fid, in qed_int_igu_init_pure_rt()
2036 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; in qed_int_igu_reset_cam()
2043 p_info->b_allow_pf_vf_change = false; in qed_int_igu_reset_cam()
2045 /* Use the numbers the MFW have provided - in qed_int_igu_reset_cam()
2048 p_info->b_allow_pf_vf_change = true; in qed_int_igu_reset_cam()
2050 if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { in qed_int_igu_reset_cam()
2053 RESC_NUM(p_hwfn, QED_SB) - 1, in qed_int_igu_reset_cam()
2054 p_info->usage.cnt); in qed_int_igu_reset_cam()
2055 p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; in qed_int_igu_reset_cam()
2059 u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; in qed_int_igu_reset_cam()
2061 if (vfs != p_info->usage.iov_cnt) in qed_int_igu_reset_cam()
2065 p_info->usage.iov_cnt, vfs); in qed_int_igu_reset_cam()
2071 if (vfs > p_info->usage.free_cnt + in qed_int_igu_reset_cam()
2072 p_info->usage.free_cnt_iov - p_info->usage.cnt) { in qed_int_igu_reset_cam()
2074 "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", in qed_int_igu_reset_cam()
2075 p_info->usage.free_cnt + in qed_int_igu_reset_cam()
2076 p_info->usage.free_cnt_iov, in qed_int_igu_reset_cam()
2077 p_info->usage.cnt, vfs); in qed_int_igu_reset_cam()
2078 return -EINVAL; in qed_int_igu_reset_cam()
2084 p_info->usage.iov_cnt = vfs; in qed_int_igu_reset_cam()
2089 p_info->usage.free_cnt = p_info->usage.cnt; in qed_int_igu_reset_cam()
2090 p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; in qed_int_igu_reset_cam()
2091 p_info->usage.orig = p_info->usage.cnt; in qed_int_igu_reset_cam()
2092 p_info->usage.iov_orig = p_info->usage.iov_cnt; in qed_int_igu_reset_cam()
2094 /* We now proceed to re-configure the IGU cam to reflect the initial in qed_int_igu_reset_cam()
2097 pf_sbs = p_info->usage.cnt; in qed_int_igu_reset_cam()
2098 vf_sbs = p_info->usage.iov_cnt; in qed_int_igu_reset_cam()
2100 for (igu_sb_id = p_info->igu_dsb_id; in qed_int_igu_reset_cam()
2101 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { in qed_int_igu_reset_cam()
2102 p_block = &p_info->entry[igu_sb_id]; in qed_int_igu_reset_cam()
2105 if (!(p_block->status & QED_IGU_STATUS_VALID)) in qed_int_igu_reset_cam()
2108 if (p_block->status & QED_IGU_STATUS_DSB) { in qed_int_igu_reset_cam()
2109 p_block->function_id = p_hwfn->rel_pf_id; in qed_int_igu_reset_cam()
2110 p_block->is_pf = 1; in qed_int_igu_reset_cam()
2111 p_block->vector_number = 0; in qed_int_igu_reset_cam()
2112 p_block->status = QED_IGU_STATUS_VALID | in qed_int_igu_reset_cam()
2116 pf_sbs--; in qed_int_igu_reset_cam()
2117 p_block->function_id = p_hwfn->rel_pf_id; in qed_int_igu_reset_cam()
2118 p_block->is_pf = 1; in qed_int_igu_reset_cam()
2119 p_block->vector_number = p_info->usage.cnt - pf_sbs; in qed_int_igu_reset_cam()
2120 p_block->status = QED_IGU_STATUS_VALID | in qed_int_igu_reset_cam()
2124 p_block->function_id = in qed_int_igu_reset_cam()
2125 p_hwfn->cdev->p_iov_info->first_vf_in_pf + in qed_int_igu_reset_cam()
2126 p_info->usage.iov_cnt - vf_sbs; in qed_int_igu_reset_cam()
2127 p_block->is_pf = 0; in qed_int_igu_reset_cam()
2128 p_block->vector_number = 0; in qed_int_igu_reset_cam()
2129 p_block->status = QED_IGU_STATUS_VALID | in qed_int_igu_reset_cam()
2131 vf_sbs--; in qed_int_igu_reset_cam()
2133 p_block->function_id = 0; in qed_int_igu_reset_cam()
2134 p_block->is_pf = 0; in qed_int_igu_reset_cam()
2135 p_block->vector_number = 0; in qed_int_igu_reset_cam()
2139 p_block->function_id); in qed_int_igu_reset_cam()
2140 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); in qed_int_igu_reset_cam()
2142 p_block->vector_number); in qed_int_igu_reset_cam()
2145 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); in qed_int_igu_reset_cam()
2157 "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", in qed_int_igu_reset_cam()
2159 p_block->function_id, in qed_int_igu_reset_cam()
2160 p_block->is_pf, in qed_int_igu_reset_cam()
2161 p_block->vector_number, rval, val); in qed_int_igu_reset_cam()
2175 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; in qed_int_igu_read_cam_block()
2178 p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); in qed_int_igu_read_cam_block()
2179 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); in qed_int_igu_read_cam_block()
2180 p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); in qed_int_igu_read_cam_block()
2181 p_block->igu_sb_id = igu_sb_id; in qed_int_igu_read_cam_block()
2191 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); in qed_int_igu_read_cam()
2192 if (!p_hwfn->hw_info.p_igu_info) in qed_int_igu_read_cam()
2193 return -ENOMEM; in qed_int_igu_read_cam()
2195 p_igu_info = p_hwfn->hw_info.p_igu_info; in qed_int_igu_read_cam()
2197 /* Distinguish between existent and non-existent default SB */ in qed_int_igu_read_cam()
2198 p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; in qed_int_igu_read_cam()
2201 if (p_hwfn->cdev->p_iov_info) { in qed_int_igu_read_cam()
2202 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; in qed_int_igu_read_cam()
2204 min_vf = p_iov->first_vf_in_pf; in qed_int_igu_read_cam()
2205 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; in qed_int_igu_read_cam()
2209 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { in qed_int_igu_read_cam()
2212 p_block = &p_igu_info->entry[igu_sb_id]; in qed_int_igu_read_cam()
2214 if ((p_block->is_pf) && in qed_int_igu_read_cam()
2215 (p_block->function_id == p_hwfn->rel_pf_id)) { in qed_int_igu_read_cam()
2216 p_block->status = QED_IGU_STATUS_PF | in qed_int_igu_read_cam()
2220 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) in qed_int_igu_read_cam()
2221 p_igu_info->usage.cnt++; in qed_int_igu_read_cam()
2222 } else if (!(p_block->is_pf) && in qed_int_igu_read_cam()
2223 (p_block->function_id >= min_vf) && in qed_int_igu_read_cam()
2224 (p_block->function_id < max_vf)) { in qed_int_igu_read_cam()
2226 p_block->status = QED_IGU_STATUS_VALID | in qed_int_igu_read_cam()
2229 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) in qed_int_igu_read_cam()
2230 p_igu_info->usage.iov_cnt++; in qed_int_igu_read_cam()
2236 if ((p_block->status & QED_IGU_STATUS_VALID) && in qed_int_igu_read_cam()
2237 (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { in qed_int_igu_read_cam()
2238 p_igu_info->igu_dsb_id = igu_sb_id; in qed_int_igu_read_cam()
2239 p_block->status |= QED_IGU_STATUS_DSB; in qed_int_igu_read_cam()
2246 if ((p_block->status & QED_IGU_STATUS_VALID) || in qed_int_igu_read_cam()
2247 (p_hwfn->abs_pf_id == 0)) { in qed_int_igu_read_cam()
2250 igu_sb_id, p_block->function_id, in qed_int_igu_read_cam()
2251 p_block->is_pf, p_block->vector_number); in qed_int_igu_read_cam()
2255 if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { in qed_int_igu_read_cam()
2258 p_igu_info->igu_dsb_id); in qed_int_igu_read_cam()
2259 return -EINVAL; in qed_int_igu_read_cam()
2263 p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; in qed_int_igu_read_cam()
2264 p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; in qed_int_igu_read_cam()
2267 "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", in qed_int_igu_read_cam()
2268 p_igu_info->igu_dsb_id, in qed_int_igu_read_cam()
2269 p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); in qed_int_igu_read_cam()
2275 * qed_int_igu_init_rt() - Initialize IGU runtime registers.
2288 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - in qed_int_igu_read_sisr_reg()
2290 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - in qed_int_igu_read_sisr_reg()
2308 tasklet_setup(&p_hwfn->sp_dpc, qed_int_sp_dpc); in qed_int_sp_dpc_setup()
2309 p_hwfn->b_sp_dpc_enabled = true; in qed_int_sp_dpc_setup()
2333 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); in qed_int_setup()
2341 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; in qed_int_get_num_sbs()
2346 memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); in qed_int_get_num_sbs()
2354 cdev->hwfns[i].b_int_requested = false; in qed_int_disable_post_isr_release()
2359 cdev->attn_clr_en = clr_enable; in qed_int_attn_clr_enable()
2369 if (!p_hwfn->hw_init_done) { in qed_int_set_timer_res()
2371 return -EINVAL; in qed_int_set_timer_res()
2406 u16 sbid = p_sb->igu_sb_id; in qed_int_get_sb_dbg()
2409 if (IS_VF(p_hwfn->cdev)) in qed_int_get_sb_dbg()
2410 return -EINVAL; in qed_int_get_sb_dbg()
2412 if (sbid >= NUM_OF_SBS(p_hwfn->cdev)) in qed_int_get_sb_dbg()
2413 return -EINVAL; in qed_int_get_sb_dbg()
2415 p_info->igu_prod = qed_rd(p_hwfn, p_ptt, IGU_REG_PRODUCER_MEMORY + sbid * 4); in qed_int_get_sb_dbg()
2416 p_info->igu_cons = qed_rd(p_hwfn, p_ptt, IGU_REG_CONSUMER_MEM + sbid * 4); in qed_int_get_sb_dbg()
2419 p_info->pi[i] = (u16)qed_rd(p_hwfn, p_ptt, in qed_int_get_sb_dbg()