Lines Matching full:x3
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
359 #define CORE_TX_BD_TX_DST_MASK 0x3
469 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
471 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
473 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
475 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
478 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
480 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
482 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
484 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
487 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
489 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
491 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
493 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
496 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
498 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
500 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
502 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
505 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
507 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
509 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
511 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
514 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
516 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
518 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
639 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
710 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
713 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
715 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
717 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
719 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
722 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
724 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
726 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
728 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
731 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
733 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
806 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
808 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
810 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
813 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
815 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
817 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
819 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
1494 #define DMAE_CMD_DST_MASK 0x3
1514 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1516 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1518 #define DMAE_CMD_PORT_ID_MASK 0x3
1528 #define DMAE_CMD_RESERVED2_MASK 0x3
1610 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1612 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1614 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1647 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1649 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1651 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1797 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1866 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
3253 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3255 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3257 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3259 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3262 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3264 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3266 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3268 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3271 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3273 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3275 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3277 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
3280 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
3282 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
3284 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
3286 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
3289 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
3291 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
3293 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
3295 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
3298 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
3300 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
3302 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
3423 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
3491 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
3493 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
3495 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3543 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3546 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3548 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3550 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3552 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3555 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3557 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3559 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3561 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3564 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3566 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3639 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
3641 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
3643 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3646 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3648 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
3650 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
3652 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4375 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
4377 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
4379 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
4381 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
4384 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
4386 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
4388 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
4390 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
4393 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
4395 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
4397 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
4399 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
4402 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
4404 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
4406 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
4408 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
4411 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
4413 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
4415 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
4417 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
4420 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
4422 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
4424 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
4545 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
4574 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4576 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4578 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4641 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
4643 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
4645 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
4647 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
4650 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
4652 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
4654 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
4656 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
4659 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
4661 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
4663 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
4665 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
4668 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
4670 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
4672 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
4674 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
4677 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4679 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4681 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
4683 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4686 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4688 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
4690 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4811 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4872 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
4911 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
5028 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5030 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5032 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
5084 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5086 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5088 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
5145 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
5148 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
5150 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
5152 #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3
5154 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
5249 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5251 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK 0x3
5253 #define YSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5323 #define XSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5325 #define XSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5327 #define XSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5329 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5332 #define XSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5334 #define XSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5336 #define XSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5338 #define XSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5341 #define XSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5343 #define XSTORM_TOE_CONN_AG_CTX_CF9_MASK 0x3
5345 #define XSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5347 #define XSTORM_TOE_CONN_AG_CTX_CF11_MASK 0x3
5350 #define XSTORM_TOE_CONN_AG_CTX_CF12_MASK 0x3
5352 #define XSTORM_TOE_CONN_AG_CTX_CF13_MASK 0x3
5354 #define XSTORM_TOE_CONN_AG_CTX_CF14_MASK 0x3
5356 #define XSTORM_TOE_CONN_AG_CTX_CF15_MASK 0x3
5359 #define XSTORM_TOE_CONN_AG_CTX_CF16_MASK 0x3
5361 #define XSTORM_TOE_CONN_AG_CTX_CF17_MASK 0x3
5363 #define XSTORM_TOE_CONN_AG_CTX_CF18_MASK 0x3
5365 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
5368 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5370 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
5372 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5493 #define XSTORM_TOE_CONN_AG_CTX_CF23_MASK 0x3
5558 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK 0x3
5561 #define TSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5563 #define TSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5565 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5567 #define TSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5570 #define TSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5572 #define TSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5574 #define TSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5576 #define TSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5579 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5581 #define TSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5647 #define USTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5649 #define USTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5651 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK 0x3
5654 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5656 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5658 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK 0x3
5660 #define USTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
6003 #define MSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
6005 #define MSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
6007 #define MSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
6035 #define TOE_DB_DATA_DEST_MASK 0x3
6037 #define TOE_DB_DATA_AGG_CMD_MASK 0x3
6043 #define TOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
6214 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6341 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6343 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6345 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6348 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6350 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6352 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6354 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6357 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6408 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6410 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6412 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6415 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6417 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
6419 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
6421 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6507 #define XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6509 #define XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
6511 #define XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6513 #define XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3
6516 #define XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3
6518 #define XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6520 #define XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6522 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6525 #define XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6527 #define XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6529 #define XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6531 #define XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3
6534 #define XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3
6536 #define XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3
6538 #define XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3
6540 #define XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3
6543 #define XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3
6545 #define XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3
6547 #define XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3
6549 #define XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3
6552 #define XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3
6554 #define XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3
6556 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6669 #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
6675 #define XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3
6714 #define TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6717 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6719 #define TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6721 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6723 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6726 #define TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6728 #define TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6730 #define TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3
6732 #define TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6735 #define TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6737 #define TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6863 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6922 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7436 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
7438 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
7440 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
7442 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
7445 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
7447 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
7449 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
7451 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
7454 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
7456 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
7458 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
7460 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
7463 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
7465 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
7467 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
7469 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
7472 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
7474 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
7476 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
7478 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
7481 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
7483 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
7485 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
7598 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
7604 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
7633 #define MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7635 #define MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
7637 #define MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7670 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7672 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7674 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7707 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7709 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7711 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7752 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7755 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7757 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7759 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7761 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7764 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3
7766 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7768 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7770 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7773 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7775 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7856 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7859 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7861 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7863 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7865 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7868 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7870 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7872 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7874 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7877 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7879 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7952 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7954 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7956 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7959 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7961 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
7963 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
7965 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
8021 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8023 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8025 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8028 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8030 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8032 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8034 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8120 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8122 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8124 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8126 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8129 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8131 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8133 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8135 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8138 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3
8140 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3
8142 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8144 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8147 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8149 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8151 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8153 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8156 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8158 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8160 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8162 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8165 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8167 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8169 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8282 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8288 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8349 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8351 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8353 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8355 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8358 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8360 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8362 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8364 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8367 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8369 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8371 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8373 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8376 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8378 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8380 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8382 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8385 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8387 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8389 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8391 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8394 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8396 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8398 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8519 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8550 #define YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
8552 #define YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
8554 #define YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
8594 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8596 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8598 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8638 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8640 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8642 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8735 #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8737 #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
8739 #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
8741 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8744 #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8746 #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8748 #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8750 #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8753 #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8755 #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
8757 #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
8759 #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
8762 #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
8764 #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
8766 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8768 #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
8771 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
8773 #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
8775 #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
8777 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8780 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8782 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
8784 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8905 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3
8970 #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8973 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
8975 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
8977 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8979 #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8982 #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8984 #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8986 #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8988 #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8991 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
8993 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
9382 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9384 #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9386 #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9419 #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9421 #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9423 #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9426 #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
9428 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
9430 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
9432 #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9488 #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9490 #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9492 #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9651 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
9738 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9740 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9742 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9744 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9747 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9749 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9751 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9753 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9756 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9758 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9760 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9762 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
9765 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
9767 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
9769 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
9771 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
9774 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
9776 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
9778 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
9780 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
9783 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9785 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
9787 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9908 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
9963 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
9966 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
9968 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9970 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
9972 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9975 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9977 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9979 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9981 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9984 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9986 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10042 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10044 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10046 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10049 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10051 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10053 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10055 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10121 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10139 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10141 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10143 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10280 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10282 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10284 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10371 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10373 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10375 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10377 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10380 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10382 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10384 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10386 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10389 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10391 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10393 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10395 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10398 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10400 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
10402 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
10404 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
10407 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
10409 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
10411 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
10413 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
10416 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
10418 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
10420 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10541 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
10606 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10609 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
10611 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
10613 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10615 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10618 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10620 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10622 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10624 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10627 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10629 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
10695 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10697 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10699 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10702 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
10704 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10706 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10708 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10769 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10771 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10773 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10844 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10846 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10848 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3