Lines Matching +full:0 +full:x1
89 LL2_OK = 0,
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
148 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
149 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
189 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
192 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
277 CORE_RX_PKT_SOURCE_NETWORK = 0,
322 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
323 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
324 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
326 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
328 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
330 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
332 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
334 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
336 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
338 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
340 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
342 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
344 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
346 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
357 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
358 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
359 #define CORE_TX_BD_TX_DST_MASK 0x3
435 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
436 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
437 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
439 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
441 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
443 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
445 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
447 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
449 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
452 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
453 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
454 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
456 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
458 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
460 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
462 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
464 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
466 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
469 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
470 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
471 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
473 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
475 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
478 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
479 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
480 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
482 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
484 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
487 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
488 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
489 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
491 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
493 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
496 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
497 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
498 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
500 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
502 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
505 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
506 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
507 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
509 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
511 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
514 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
515 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
516 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
518 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
520 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
522 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
525 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
526 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
527 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
529 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
531 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
533 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
535 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
537 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
539 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
542 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
543 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
544 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
546 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
548 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
550 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
552 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
554 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
556 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
559 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
560 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
561 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
563 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
565 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
567 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
569 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
571 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
573 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
576 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
577 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
578 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
580 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
582 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
584 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
586 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
588 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
590 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
593 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
594 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
595 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
597 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
599 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
601 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
603 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
605 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
607 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
610 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
611 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
612 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
614 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
616 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
618 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
620 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
622 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
624 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
627 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
628 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
629 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
631 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
633 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
635 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
637 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
639 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
698 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
699 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
700 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
702 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
704 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
706 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
708 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
710 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
713 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
714 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
715 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
717 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
719 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
722 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
723 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
724 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
726 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
728 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
731 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
732 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
733 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
735 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
737 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
739 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
741 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
744 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
745 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
746 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
748 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
750 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
752 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
754 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
756 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
758 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
761 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
762 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
763 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
765 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
767 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
769 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
771 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
773 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
775 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
802 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
803 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
804 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
806 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
808 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
810 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
813 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
814 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
815 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
817 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
819 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
822 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
823 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
824 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
826 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
828 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
830 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
832 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
834 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
836 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
839 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
840 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
841 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
843 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
845 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
847 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
849 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
851 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
853 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
1038 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1039 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1040 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1302 COMMON_ERR_CODE_OK = 0,
1309 ETH_VER_KEY = 0,
1409 TUNNEL_CLSS_MAC_VLAN = 0,
1492 #define DMAE_CMD_SRC_MASK 0x1
1493 #define DMAE_CMD_SRC_SHIFT 0
1494 #define DMAE_CMD_DST_MASK 0x3
1496 #define DMAE_CMD_C_DST_MASK 0x1
1498 #define DMAE_CMD_CRC_RESET_MASK 0x1
1500 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1502 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1504 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1506 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1508 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1510 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1512 #define DMAE_CMD_RESERVED1_MASK 0x1
1514 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1516 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1518 #define DMAE_CMD_PORT_ID_MASK 0x3
1520 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1522 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1524 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1526 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1528 #define DMAE_CMD_RESERVED2_MASK 0x3
1536 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1537 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1538 #define DMAE_CMD_DST_VF_ID_MASK 0xFF
1549 #define DMAE_CMD_ERROR_BIT_MASK 0x1
1550 #define DMAE_CMD_ERROR_BIT_SHIFT 0
1551 #define DMAE_CMD_RESERVED_MASK 0x7FFF
1606 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1607 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1608 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1610 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1612 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1614 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1617 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1618 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1619 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1621 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1623 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1625 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1627 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1629 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1631 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1643 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1644 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1645 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1647 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1649 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1651 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1654 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1655 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1656 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1658 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1660 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1662 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1664 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1666 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1668 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1693 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
1694 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
1695 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
1697 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
1699 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
1701 #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1
1703 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
1705 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
1707 #define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
1721 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1722 #define IGU_CLEANUP_RESERVED0_SHIFT 0
1723 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1725 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1727 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1742 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1743 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1744 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1746 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1753 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1754 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1755 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1757 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1759 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1761 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1763 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1772 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1773 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1774 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1776 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1778 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1785 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1786 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1787 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1789 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1791 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1793 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1795 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1797 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1812 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1813 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1814 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1816 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1818 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1820 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1822 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1824 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1826 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1833 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1834 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1835 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1837 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1839 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1841 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1843 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1845 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1847 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1849 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1851 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1858 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1859 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1860 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
1862 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1864 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F
1866 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
1868 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1870 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1877 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1878 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1879 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1881 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1888 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1889 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1890 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1892 #define SDM_OP_GEN_RESERVED_MASK 0xFFF
2015 #define ANY_PHASE_ID 0xffff
2119 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF
2120 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2121 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
2128 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2129 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2130 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2137 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2138 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2139 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2146 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2147 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2148 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2155 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2156 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2157 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2159 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2182 #define INIT_CALLBACK_OP_OP_MASK 0xF
2183 #define INIT_CALLBACK_OP_OP_SHIFT 0
2184 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2193 #define INIT_DELAY_OP_OP_MASK 0xF
2194 #define INIT_DELAY_OP_OP_SHIFT 0
2195 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2203 #define INIT_IF_MODE_OP_OP_MASK 0xF
2204 #define INIT_IF_MODE_OP_OP_SHIFT 0
2205 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2207 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2216 #define INIT_IF_PHASE_OP_OP_MASK 0xF
2217 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2218 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF
2220 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2223 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2224 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2225 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2227 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2242 #define INIT_RAW_OP_OP_MASK 0xF
2243 #define INIT_RAW_OP_OP_SHIFT 0
2244 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2266 #define INIT_WRITE_OP_OP_MASK 0xF
2267 #define INIT_WRITE_OP_OP_SHIFT 0
2268 #define INIT_WRITE_OP_SOURCE_MASK 0x7
2270 #define INIT_WRITE_OP_RESERVED_MASK 0x1
2272 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2274 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2282 #define INIT_READ_OP_OP_MASK 0xF
2283 #define INIT_READ_OP_OP_SHIFT 0
2284 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
2286 #define INIT_READ_OP_RESERVED_MASK 0x1
2288 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2343 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
2346 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
2349 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
2352 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
2355 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL
2358 #define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL
2361 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL
2364 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL
2367 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL
2370 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL
2373 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL
2376 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL
2424 * Return: 0 on success, -1 on error.
2459 * Return: 0 on success, -1 on error.
2473 * Return: 0 on success, -1 on error.
2486 * Return: 0 on success, -1 on error.
2501 * Return: 0 on success, -1 on error.
2517 * Return: 0 on success, -1 on error.
2533 * Return: 0 on success, -1 on error.
2743 #define PCICFG_OFFSET 0x2000
2744 #define GRC_CONFIG_REG_PF_INIT_VF 0x624
2750 * Since registers from 0x000-0x7ff are spilt across functions, each PF will
2753 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff
2756 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
3198 #define DMAE_READY_CB 0
3219 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
3220 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
3221 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
3223 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
3225 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
3227 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
3229 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
3231 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
3233 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
3236 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
3237 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
3238 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
3240 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
3242 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
3244 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
3246 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
3248 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
3250 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
3253 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3254 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
3255 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3257 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3259 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3262 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3263 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
3264 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3266 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3268 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3271 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3272 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
3273 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3275 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3277 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
3280 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
3281 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
3282 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
3284 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
3286 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
3289 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
3290 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
3291 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
3293 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
3295 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
3298 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
3299 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
3300 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
3302 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
3304 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
3306 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
3309 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3310 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
3311 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3313 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
3315 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
3317 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
3319 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
3321 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
3323 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
3326 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
3327 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
3328 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
3330 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
3332 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
3334 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
3336 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
3338 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
3340 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
3343 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
3344 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
3345 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
3347 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
3349 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
3351 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
3353 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
3355 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
3357 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
3360 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
3361 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
3362 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
3364 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
3366 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3368 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
3370 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3372 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
3374 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
3377 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
3378 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
3379 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
3381 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
3383 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
3385 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
3387 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
3389 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
3391 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
3394 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
3395 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
3396 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
3398 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
3400 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
3402 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
3404 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
3406 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
3408 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
3411 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
3412 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
3413 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
3415 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
3417 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
3419 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
3421 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
3423 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
3487 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3488 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3489 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3491 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
3493 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
3495 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3498 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
3499 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
3500 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
3502 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3504 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3506 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3508 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3510 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3512 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3531 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3532 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3533 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3535 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
3537 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
3539 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
3541 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
3543 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3546 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3547 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
3548 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3550 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3552 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3555 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3556 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
3557 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3559 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3561 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3564 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3565 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
3566 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3568 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
3570 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
3572 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3574 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3577 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
3578 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
3579 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
3581 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
3583 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
3585 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
3587 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
3589 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
3591 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3594 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3595 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
3596 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3598 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3600 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3602 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3604 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
3606 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3608 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
3635 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3636 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3637 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3639 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
3641 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
3643 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3646 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3647 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
3648 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
3650 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
3652 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
3655 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
3656 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
3657 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
3659 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3661 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3663 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
3665 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
3667 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
3669 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3672 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3673 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
3674 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3676 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3678 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3680 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3682 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
3684 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3686 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
3727 ETH_OK = 0x00,
3890 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F
3891 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
3892 #define ETH_RETURN_CODE_RESERVED_MASK 0x1
3894 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
3916 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
3917 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
3918 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
3920 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
3922 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
3924 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
3926 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
3928 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
3930 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
3932 #define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF
3939 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
3940 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
3941 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
3943 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
3945 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
3947 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
3949 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
3951 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
3953 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
3979 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
3980 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
3981 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
3983 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
3985 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
3987 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
3989 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
3991 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1
3993 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF
4020 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
4021 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
4022 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4024 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
4026 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4028 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4030 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
4175 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
4176 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
4177 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
4179 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
4181 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
4183 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
4185 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7
4341 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
4342 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
4343 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
4345 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
4347 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
4349 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
4351 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
4353 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
4355 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
4358 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
4359 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
4360 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
4362 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
4364 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
4366 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1
4368 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1
4370 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
4372 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
4375 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
4376 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
4377 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
4379 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
4381 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
4384 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
4385 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
4386 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
4388 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
4390 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
4393 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
4394 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
4395 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
4397 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
4399 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
4402 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
4403 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
4404 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
4406 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
4408 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
4411 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
4412 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
4413 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
4415 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
4417 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
4420 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
4421 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
4422 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
4424 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
4426 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
4428 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
4431 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
4432 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
4433 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
4435 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
4437 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
4439 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
4441 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
4443 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
4445 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
4448 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
4449 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
4450 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
4452 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
4454 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
4456 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
4458 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
4460 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
4462 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
4465 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
4466 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
4467 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
4469 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
4471 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
4473 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
4475 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
4477 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
4479 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
4482 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
4483 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
4484 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
4486 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
4488 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
4490 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
4492 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
4494 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
4496 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
4499 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
4500 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
4501 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
4503 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
4505 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
4507 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
4509 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
4511 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
4513 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
4516 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
4517 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
4518 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
4520 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
4522 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
4524 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
4526 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
4528 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
4530 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
4533 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
4534 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
4535 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
4537 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
4539 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4541 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
4543 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
4545 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
4570 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4571 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4572 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4574 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4576 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4578 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4581 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4582 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
4583 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4585 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4587 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4589 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4591 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4593 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4595 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4607 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4608 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4609 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
4611 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
4613 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4615 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
4617 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
4619 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
4621 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
4624 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
4625 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
4626 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
4628 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
4630 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
4632 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
4634 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
4636 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4638 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4641 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
4642 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
4643 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
4645 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
4647 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
4650 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
4651 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
4652 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
4654 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
4656 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
4659 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
4660 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
4661 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
4663 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
4665 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
4668 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
4669 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
4670 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
4672 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
4674 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
4677 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4678 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4679 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4681 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
4683 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4686 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4687 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4688 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
4690 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4692 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
4694 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
4697 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
4698 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
4699 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
4701 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
4703 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
4705 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
4707 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
4709 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
4711 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
4714 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
4715 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
4716 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
4718 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
4720 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
4722 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
4724 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
4726 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4728 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4731 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4732 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4733 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4735 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4737 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
4739 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4741 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4743 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
4745 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
4748 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
4749 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
4750 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
4752 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4754 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
4756 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
4758 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
4760 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4762 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
4765 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
4766 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
4767 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
4769 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4771 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4773 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
4775 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
4777 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
4779 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
4782 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
4783 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
4784 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
4786 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4788 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4790 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4792 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4794 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4796 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4799 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4800 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4801 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4803 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4805 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4807 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4809 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4811 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4826 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
4827 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
4828 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
4830 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
4832 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
4834 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
4836 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
4838 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
4840 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
4842 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
4844 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
4846 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
4848 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
4854 GFT_PROFILE_IPV4 = 0,
4862 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
4863 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
4864 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
4866 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
4868 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
4870 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
4872 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
4878 GFT_PROFILE_NO_TUNNEL = 0,
4889 GFT_PROFILE_ROCE_PROTOCOL = 0,
4911 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
4912 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
4913 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
4915 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
4917 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
4919 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
4921 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
4923 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
4925 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
4927 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
4929 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
4931 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
4933 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
4935 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
4937 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
4939 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
4941 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
4943 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
4945 #define GFT_RAM_LINE_TTL_MASK 0x1
4947 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
4949 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
4951 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
4953 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
4955 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
4957 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
4959 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
4961 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
4963 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
4965 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
4967 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
4969 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
4971 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
4974 #define GFT_RAM_LINE_DSCP_MASK 0x1
4975 #define GFT_RAM_LINE_DSCP_SHIFT 0
4976 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
4978 #define GFT_RAM_LINE_DST_IP_MASK 0x1
4980 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
4982 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
4984 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
4986 #define GFT_RAM_LINE_VLAN_MASK 0x1
4988 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
4990 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
4992 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
4994 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
5000 INNER_PROVIDER_VLAN = 0,
5017 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5018 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5019 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5021 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5023 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
5025 #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
5028 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5029 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5030 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5032 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
5034 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5036 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5039 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
5040 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
5041 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5043 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5045 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5047 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5049 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5051 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5053 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5073 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5074 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5075 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5077 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5079 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
5081 #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
5084 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5085 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5086 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5088 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
5090 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5092 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5095 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
5096 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
5097 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5099 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5101 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5103 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5105 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5107 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5109 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5139 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5140 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5141 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5143 #define USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5145 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
5148 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
5149 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
5150 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
5152 #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3
5154 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
5157 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
5158 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
5159 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
5161 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
5163 #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1
5165 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
5167 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5169 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5171 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5174 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
5175 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0
5176 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5178 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
5180 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5182 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
5245 #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5246 #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5247 #define YSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5249 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5251 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK 0x3
5253 #define YSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5256 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1
5257 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT 0
5258 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK 0x1
5260 #define YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5262 #define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK 0x1
5264 #define YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5266 #define YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5268 #define YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5270 #define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK 0x1
5289 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5290 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5291 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
5293 #define XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK 0x1
5295 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5297 #define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK 0x1
5299 #define XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK 0x1
5301 #define XSTORM_TOE_CONN_AG_CTX_BIT6_MASK 0x1
5303 #define XSTORM_TOE_CONN_AG_CTX_BIT7_MASK 0x1
5306 #define XSTORM_TOE_CONN_AG_CTX_BIT8_MASK 0x1
5307 #define XSTORM_TOE_CONN_AG_CTX_BIT8_SHIFT 0
5308 #define XSTORM_TOE_CONN_AG_CTX_BIT9_MASK 0x1
5310 #define XSTORM_TOE_CONN_AG_CTX_BIT10_MASK 0x1
5312 #define XSTORM_TOE_CONN_AG_CTX_BIT11_MASK 0x1
5314 #define XSTORM_TOE_CONN_AG_CTX_BIT12_MASK 0x1
5316 #define XSTORM_TOE_CONN_AG_CTX_BIT13_MASK 0x1
5318 #define XSTORM_TOE_CONN_AG_CTX_BIT14_MASK 0x1
5320 #define XSTORM_TOE_CONN_AG_CTX_BIT15_MASK 0x1
5323 #define XSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5324 #define XSTORM_TOE_CONN_AG_CTX_CF0_SHIFT 0
5325 #define XSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5327 #define XSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5329 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5332 #define XSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5333 #define XSTORM_TOE_CONN_AG_CTX_CF4_SHIFT 0
5334 #define XSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5336 #define XSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5338 #define XSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5341 #define XSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5342 #define XSTORM_TOE_CONN_AG_CTX_CF8_SHIFT 0
5343 #define XSTORM_TOE_CONN_AG_CTX_CF9_MASK 0x3
5345 #define XSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5347 #define XSTORM_TOE_CONN_AG_CTX_CF11_MASK 0x3
5350 #define XSTORM_TOE_CONN_AG_CTX_CF12_MASK 0x3
5351 #define XSTORM_TOE_CONN_AG_CTX_CF12_SHIFT 0
5352 #define XSTORM_TOE_CONN_AG_CTX_CF13_MASK 0x3
5354 #define XSTORM_TOE_CONN_AG_CTX_CF14_MASK 0x3
5356 #define XSTORM_TOE_CONN_AG_CTX_CF15_MASK 0x3
5359 #define XSTORM_TOE_CONN_AG_CTX_CF16_MASK 0x3
5360 #define XSTORM_TOE_CONN_AG_CTX_CF16_SHIFT 0
5361 #define XSTORM_TOE_CONN_AG_CTX_CF17_MASK 0x3
5363 #define XSTORM_TOE_CONN_AG_CTX_CF18_MASK 0x3
5365 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
5368 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5369 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5370 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
5372 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5374 #define XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
5376 #define XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5379 #define XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5380 #define XSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 0
5381 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5383 #define XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1
5385 #define XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1
5387 #define XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5389 #define XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1
5391 #define XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1
5393 #define XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK 0x1
5396 #define XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1
5397 #define XSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT 0
5398 #define XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK 0x1
5400 #define XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK 0x1
5402 #define XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK 0x1
5404 #define XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK 0x1
5406 #define XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK 0x1
5408 #define XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK 0x1
5410 #define XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK 0x1
5413 #define XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK 0x1
5414 #define XSTORM_TOE_CONN_AG_CTX_CF18EN_SHIFT 0
5415 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
5417 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5419 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
5421 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5423 #define XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK 0x1
5425 #define XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5427 #define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
5430 #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
5431 #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
5432 #define XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5434 #define XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK 0x1
5436 #define XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5438 #define XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5440 #define XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5442 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5444 #define XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK 0x1
5447 #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK 0x1
5448 #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_SHIFT 0
5449 #define XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK 0x1
5451 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5453 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5455 #define XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK 0x1
5457 #define XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK 0x1
5459 #define XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK 0x1
5461 #define XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK 0x1
5464 #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK 0x1
5465 #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_SHIFT 0
5466 #define XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK 0x1
5468 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5470 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5472 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5474 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5476 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5478 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5481 #define XSTORM_TOE_CONN_AG_CTX_BIT16_MASK 0x1
5482 #define XSTORM_TOE_CONN_AG_CTX_BIT16_SHIFT 0
5483 #define XSTORM_TOE_CONN_AG_CTX_BIT17_MASK 0x1
5485 #define XSTORM_TOE_CONN_AG_CTX_BIT18_MASK 0x1
5487 #define XSTORM_TOE_CONN_AG_CTX_BIT19_MASK 0x1
5489 #define XSTORM_TOE_CONN_AG_CTX_BIT20_MASK 0x1
5491 #define XSTORM_TOE_CONN_AG_CTX_BIT21_MASK 0x1
5493 #define XSTORM_TOE_CONN_AG_CTX_CF23_MASK 0x3
5546 #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5547 #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5548 #define TSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5550 #define TSTORM_TOE_CONN_AG_CTX_BIT2_MASK 0x1
5552 #define TSTORM_TOE_CONN_AG_CTX_BIT3_MASK 0x1
5554 #define TSTORM_TOE_CONN_AG_CTX_BIT4_MASK 0x1
5556 #define TSTORM_TOE_CONN_AG_CTX_BIT5_MASK 0x1
5558 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK 0x3
5561 #define TSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5562 #define TSTORM_TOE_CONN_AG_CTX_CF1_SHIFT 0
5563 #define TSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5565 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5567 #define TSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5570 #define TSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5571 #define TSTORM_TOE_CONN_AG_CTX_CF5_SHIFT 0
5572 #define TSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5574 #define TSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5576 #define TSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5579 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5580 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5581 #define TSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5583 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK 0x1
5585 #define TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5587 #define TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5589 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5592 #define TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1
5593 #define TSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT 0
5594 #define TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1
5596 #define TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5598 #define TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1
5600 #define TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1
5602 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5604 #define TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1
5606 #define TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5609 #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5610 #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 0
5611 #define TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5613 #define TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5615 #define TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
5617 #define TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5619 #define TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5621 #define TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5623 #define TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1
5643 #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5644 #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5645 #define USTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5647 #define USTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5649 #define USTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5651 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK 0x3
5654 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5655 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 0
5656 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5658 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK 0x3
5660 #define USTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5663 #define USTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
5664 #define USTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 0
5665 #define USTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5667 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK 0x1
5669 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5671 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1
5673 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5675 #define USTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5677 #define USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5680 #define USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5681 #define USTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 0
5682 #define USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5684 #define USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5686 #define USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
5688 #define USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5690 #define USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5692 #define USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5694 #define USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1
5824 #define TOE_RX_BD_START_MASK 0x1
5825 #define TOE_RX_BD_START_SHIFT 0
5826 #define TOE_RX_BD_END_MASK 0x1
5828 #define TOE_RX_BD_NO_PUSH_MASK 0x1
5830 #define TOE_RX_BD_SPLIT_MASK 0x1
5832 #define TOE_RX_BD_RESERVED0_MASK 0xFFF
5837 /* TOE RX completion queue opcodes (opcode 0 is illegal) */
5937 #define TOE_TX_BD_PUSH_MASK 0x1
5938 #define TOE_TX_BD_PUSH_SHIFT 0
5939 #define TOE_TX_BD_NOTIFY_MASK 0x1
5941 #define TOE_TX_BD_LARGE_IO_MASK 0x1
5943 #define TOE_TX_BD_BD_CONS_MASK 0x1FFF
5981 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_MASK 0x1
5982 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 0
5983 #define TOE_UPDATE_PARAMS_RESERVED_MASK 0x7FFF
5999 #define MSTORM_TOE_CONN_AG_CTX_BIT0_MASK 0x1
6000 #define MSTORM_TOE_CONN_AG_CTX_BIT0_SHIFT 0
6001 #define MSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
6003 #define MSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
6005 #define MSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
6007 #define MSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
6010 #define MSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
6011 #define MSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 0
6012 #define MSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
6014 #define MSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
6016 #define MSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
6018 #define MSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
6020 #define MSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
6022 #define MSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
6024 #define MSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
6035 #define TOE_DB_DATA_DEST_MASK 0x3
6036 #define TOE_DB_DATA_DEST_SHIFT 0
6037 #define TOE_DB_DATA_AGG_CMD_MASK 0x3
6039 #define TOE_DB_DATA_BYPASS_EN_MASK 0x1
6041 #define TOE_DB_DATA_RESERVED_MASK 0x1
6043 #define TOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
6083 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6084 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
6085 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F
6127 RDMA_RETURN_OK = 0,
6147 #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_MASK 0x1
6148 #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_SHIFT 0
6149 #define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_MASK 0x1
6151 #define RDMA_INIT_FUNC_HDR_DPT_MODE_MASK 0x1
6153 #define RDMA_INIT_FUNC_HDR_RESERVED0_MASK 0x1F
6194 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
6195 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
6196 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6198 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6200 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6202 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6204 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6206 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6208 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6210 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6212 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6214 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6217 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
6218 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
6219 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
6222 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6223 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
6224 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
6226 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
6252 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
6253 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
6254 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
6256 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6258 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F
6277 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1
6278 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0
6279 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6281 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F
6326 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
6327 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
6328 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
6330 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6332 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6334 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6337 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6338 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6339 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
6341 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6343 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6345 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6348 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6349 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
6350 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6352 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6354 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6357 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6358 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
6359 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6361 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6363 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6365 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6367 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
6369 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
6372 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
6373 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
6374 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
6376 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6378 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6380 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6382 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6384 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6386 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6404 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6405 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6406 #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1
6408 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6410 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6412 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6415 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6416 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
6417 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
6419 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
6421 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6424 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6425 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6426 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6428 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6430 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
6432 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
6434 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
6436 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6438 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
6441 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
6442 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
6443 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6445 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6447 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6449 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6451 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6453 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6455 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6473 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6474 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6475 #define XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
6477 #define XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
6479 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6481 #define XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
6483 #define XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
6485 #define XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1
6487 #define XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1
6490 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1
6491 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0
6492 #define XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1
6494 #define XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1
6496 #define XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
6498 #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
6500 #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
6502 #define XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
6504 #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
6507 #define XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6508 #define XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0
6509 #define XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
6511 #define XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6513 #define XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3
6516 #define XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3
6517 #define XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0
6518 #define XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6520 #define XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6522 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6525 #define XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6526 #define XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0
6527 #define XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6529 #define XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6531 #define XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3
6534 #define XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3
6535 #define XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0
6536 #define XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3
6538 #define XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3
6540 #define XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3
6543 #define XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3
6544 #define XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0
6545 #define XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3
6547 #define XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3
6549 #define XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3
6552 #define XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3
6553 #define XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0
6554 #define XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3
6556 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6558 #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
6560 #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
6563 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
6564 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0
6565 #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1
6567 #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1
6569 #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
6571 #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
6573 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6575 #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
6577 #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
6580 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
6581 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0
6582 #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1
6584 #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1
6586 #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1
6588 #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1
6590 #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1
6592 #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1
6594 #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1
6597 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1
6598 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0
6599 #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1
6601 #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1
6603 #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1
6605 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6607 #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1
6609 #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
6611 #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
6614 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
6615 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0
6616 #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
6618 #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
6620 #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
6622 #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
6624 #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
6626 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6628 #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1
6631 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1
6632 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0
6633 #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1
6635 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6637 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6639 #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1
6641 #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1
6643 #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1
6645 #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1
6648 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1
6649 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0
6650 #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1
6652 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6654 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6656 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6658 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6660 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6662 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6665 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1
6666 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0
6667 #define XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1
6669 #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
6671 #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1
6673 #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6675 #define XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3
6702 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6703 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6704 #define TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
6706 #define TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
6708 #define TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1
6710 #define TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
6712 #define TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
6714 #define TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6717 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6718 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6719 #define TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6721 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6723 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6726 #define TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6727 #define TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0
6728 #define TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6730 #define TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3
6732 #define TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6735 #define TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6736 #define TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0
6737 #define TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6739 #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
6741 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6743 #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
6745 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6748 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6749 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6750 #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
6752 #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
6754 #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1
6756 #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
6758 #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
6760 #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
6762 #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
6765 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
6766 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0
6767 #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
6769 #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
6771 #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
6773 #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
6775 #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
6777 #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
6779 #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1
6863 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6864 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6865 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
6867 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
6869 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
6871 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
6873 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
6875 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
6905 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
6906 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0
6907 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6909 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1
6911 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1F
6922 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6923 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6924 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
6926 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
6928 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
6930 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
6932 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
6934 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6936 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
6938 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
6940 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
6942 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6944 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1
6946 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x1FFF
6987 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_MASK 0x1
6988 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_SHIFT 0
6990 0x7FFFFFFF
7007 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7008 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0
7009 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7011 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7146 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7147 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7148 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7150 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F
7168 #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_MASK 0x1
7169 #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_SHIFT 0
7170 #define ROCE_LL2_CQE_DATA_RESERVED0_MASK 0x7F
7179 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7180 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7181 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7183 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7185 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7187 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7189 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7191 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7193 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7195 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7197 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7199 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7201 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7203 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1
7205 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x1
7208 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7209 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7210 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7230 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7231 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7232 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7234 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7236 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7238 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7240 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7242 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7244 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7246 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7248 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7250 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7252 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1
7254 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0xF
7257 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7258 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7259 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7278 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7279 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7280 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7282 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7295 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7296 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7297 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7310 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7311 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7312 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7329 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7330 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0
7331 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7333 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7378 ROCE_QP_RDB_ENTRY_RDMA_RESPONSE = 0,
7389 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7390 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7391 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7393 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF
7402 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
7403 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
7404 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
7406 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
7408 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
7410 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
7412 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
7414 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
7416 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
7419 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
7420 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
7421 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
7423 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
7425 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
7427 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
7429 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
7431 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
7433 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
7436 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
7437 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
7438 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
7440 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
7442 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
7445 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
7446 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
7447 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
7449 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
7451 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
7454 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
7455 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
7456 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
7458 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
7460 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
7463 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
7464 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
7465 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
7467 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
7469 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
7472 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
7473 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
7474 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
7476 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
7478 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
7481 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
7482 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
7483 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
7485 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
7487 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
7489 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
7492 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
7493 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
7494 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
7496 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
7498 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
7500 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
7502 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
7504 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
7506 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
7509 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
7510 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
7511 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
7513 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
7515 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
7517 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
7519 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
7521 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
7523 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
7526 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
7527 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
7528 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
7530 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
7532 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
7534 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
7536 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
7538 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
7540 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
7543 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
7544 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
7545 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
7547 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
7549 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
7551 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
7553 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
7555 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
7557 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
7560 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
7561 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
7562 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
7564 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
7566 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
7568 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
7570 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
7572 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
7574 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
7577 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
7578 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
7579 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
7581 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
7583 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
7585 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
7587 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
7589 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
7591 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
7594 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
7595 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
7596 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
7598 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
7600 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
7602 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
7604 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
7629 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
7630 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
7631 #define MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7633 #define MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7635 #define MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
7637 #define MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7640 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7641 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
7642 #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
7644 #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7646 #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7648 #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7650 #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7652 #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7654 #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7666 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7667 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7668 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7670 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7672 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7674 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7677 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7678 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7679 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7681 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7683 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7685 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7687 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7689 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7691 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7703 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7704 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7705 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7707 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7709 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7711 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7714 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7715 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7716 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7718 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7720 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7722 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7724 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7726 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7728 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7740 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7741 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7742 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
7744 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
7746 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7748 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7750 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7752 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7755 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7756 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7757 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7759 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7761 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7764 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3
7765 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0
7766 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7768 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7770 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7773 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7774 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
7775 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7777 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
7779 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7781 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
7783 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7786 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7787 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7788 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1
7790 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
7792 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
7794 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
7796 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
7798 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
7800 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7803 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7804 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7805 #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
7807 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7809 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7811 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7813 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
7815 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7817 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7844 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7845 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7846 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
7848 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
7850 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
7852 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7854 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
7856 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7859 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7860 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7861 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7863 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7865 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7868 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7869 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
7870 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7872 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7874 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7877 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7878 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
7879 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7881 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7883 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7885 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
7887 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7890 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7891 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7892 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7894 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7896 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
7898 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7900 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7902 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7904 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7907 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7908 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7909 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7911 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7913 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7915 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7917 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
7919 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7921 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7948 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7949 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7950 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7952 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7954 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7956 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7959 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7960 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
7961 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
7963 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
7965 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
7968 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7969 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7970 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7972 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7974 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7976 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
7978 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
7980 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
7982 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7985 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7986 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7987 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7989 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7991 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7993 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7995 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7997 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7999 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8017 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8018 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8019 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8021 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8023 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8025 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8028 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8029 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
8030 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8032 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8034 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8037 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8038 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8039 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8041 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8043 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8045 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8047 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8049 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8051 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8054 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8055 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8056 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8058 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8060 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8062 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8064 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8066 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8068 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8086 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8087 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8088 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8090 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8092 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8094 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8096 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8098 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8100 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8103 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8104 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
8105 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8107 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8109 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8111 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8113 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8115 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8117 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8120 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8121 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
8122 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8124 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8126 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8129 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8130 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
8131 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8133 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8135 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8138 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3
8139 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0
8140 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3
8142 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8144 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8147 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8148 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
8149 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8151 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8153 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8156 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8157 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
8158 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8160 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8162 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8165 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8166 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
8167 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8169 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8171 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8173 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8176 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8177 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
8178 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8180 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8182 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8184 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8186 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8188 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
8190 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1
8193 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8194 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
8195 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8197 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8199 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8201 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8203 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8205 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8207 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8210 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8211 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
8212 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8214 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8216 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8218 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8220 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8222 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8224 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8227 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8228 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
8229 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8231 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8233 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8235 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8237 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8239 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8241 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8244 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8245 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
8246 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8248 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8250 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8252 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8254 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8256 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8258 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8261 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8262 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
8263 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8265 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8267 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8269 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8271 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8273 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8275 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8278 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8279 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
8280 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8282 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8284 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8286 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8288 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8315 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8316 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8317 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8319 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8321 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8323 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8325 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8327 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8329 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8332 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8333 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
8334 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8336 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8338 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8340 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8342 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8344 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8346 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8349 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8350 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
8351 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8353 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8355 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8358 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8359 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
8360 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8362 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8364 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8367 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8368 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
8369 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8371 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8373 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8376 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8377 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
8378 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8380 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8382 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8385 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8386 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
8387 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8389 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8391 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8394 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8395 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
8396 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8398 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8400 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8402 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8405 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8406 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
8407 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8409 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
8411 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8413 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
8415 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8417 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8419 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8422 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8423 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
8424 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
8426 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
8428 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
8430 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
8432 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
8434 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
8436 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
8439 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
8440 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
8441 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
8443 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
8445 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
8447 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8449 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
8451 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8453 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8456 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8457 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
8458 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8460 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8462 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8464 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8466 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8468 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8470 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
8473 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
8474 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
8475 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
8477 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8479 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8481 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
8483 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
8485 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
8487 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
8490 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
8491 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
8492 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
8494 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8496 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8498 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8500 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8502 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8504 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8507 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
8508 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
8509 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
8511 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
8513 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
8515 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
8517 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
8519 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8546 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
8547 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
8548 #define YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
8550 #define YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
8552 #define YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
8554 #define YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
8557 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
8558 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
8559 #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
8561 #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
8563 #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
8565 #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
8567 #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
8569 #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
8571 #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
8590 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8591 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8592 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8594 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8596 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8598 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8601 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8602 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8603 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8605 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8607 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8609 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8611 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8613 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8615 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8634 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8635 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8636 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8638 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8640 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8642 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8645 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8646 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8647 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8649 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8651 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8653 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8655 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8657 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8659 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8701 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8702 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8703 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
8705 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
8707 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8709 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8711 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
8713 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
8715 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
8718 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
8719 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
8720 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
8722 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
8724 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
8726 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
8728 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
8730 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
8732 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
8735 #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8736 #define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
8737 #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
8739 #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
8741 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8744 #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8745 #define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
8746 #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8748 #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8750 #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8753 #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8754 #define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
8755 #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
8757 #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
8759 #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
8762 #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
8763 #define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
8764 #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
8766 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8768 #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
8771 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
8772 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
8773 #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
8775 #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
8777 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8780 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8781 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8782 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
8784 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8786 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8788 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
8791 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
8792 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
8793 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8795 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8797 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8799 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8801 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8803 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8805 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
8808 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
8809 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
8810 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
8812 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
8814 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
8816 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8818 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
8820 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
8822 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
8825 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
8826 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
8827 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
8829 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8831 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
8833 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8835 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1
8837 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
8839 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
8842 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
8843 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
8844 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
8846 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
8848 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
8850 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
8852 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
8854 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8856 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
8859 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
8860 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
8861 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
8863 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8865 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8867 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
8869 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
8871 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
8873 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
8876 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
8877 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
8878 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
8880 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
8882 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
8884 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8886 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
8888 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8890 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8893 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
8894 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
8895 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
8897 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
8899 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
8901 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
8903 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
8905 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3
8958 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8959 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8960 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
8962 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
8964 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1
8966 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8968 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
8970 #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8973 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
8974 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
8975 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
8977 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8979 #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8982 #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8983 #define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
8984 #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8986 #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8988 #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8991 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
8992 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
8993 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
8995 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8997 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
8999 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
9001 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9004 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9005 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
9006 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9008 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9010 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9012 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9014 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9016 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
9018 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9021 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9022 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
9023 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9025 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9027 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9029 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9031 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
9033 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9035 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9094 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
9095 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
9096 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9098 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9100 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9102 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9104 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9106 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1
9108 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1
9219 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9220 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
9221 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9223 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9225 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
9227 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
9229 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
9231 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF
9269 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
9270 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
9271 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
9301 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
9302 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
9303 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
9349 MPA_RTR_TYPE_NONE = 0,
9365 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
9366 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
9367 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9369 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
9378 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9379 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9380 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9382 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9384 #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9386 #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9389 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9390 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
9391 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9393 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9395 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9397 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9399 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9401 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
9403 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9415 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9416 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9417 #define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9419 #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9421 #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9423 #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9426 #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
9427 #define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
9428 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
9430 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
9432 #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9435 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9436 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9437 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9439 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9441 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
9443 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
9445 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
9447 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9449 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
9452 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
9453 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
9454 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9456 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9458 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9460 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9462 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9464 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9466 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9484 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
9485 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
9486 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9488 #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9490 #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9492 #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9495 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9496 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9497 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9499 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9501 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9503 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9505 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9507 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9509 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9540 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9541 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
9542 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9544 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
9550 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9551 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
9552 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9554 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
9562 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
9563 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
9564 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
9566 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7
9616 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
9617 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
9618 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
9620 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9622 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9624 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1
9626 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7
9645 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
9646 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
9647 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9649 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
9651 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
9653 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
9680 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
9681 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
9682 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9684 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9686 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
9688 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
9690 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
9704 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9705 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9706 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
9708 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
9710 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9712 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
9714 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
9716 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
9718 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
9721 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
9722 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
9723 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
9725 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
9727 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
9729 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
9731 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
9733 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
9735 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
9738 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9739 #define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
9740 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9742 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9744 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9747 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9748 #define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
9749 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9751 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9753 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9756 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9757 #define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
9758 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9760 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9762 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
9765 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
9766 #define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
9767 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
9769 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
9771 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
9774 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
9775 #define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
9776 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
9778 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
9780 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
9783 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9784 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9785 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
9787 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9789 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9791 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9794 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9795 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
9796 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9798 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9800 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9802 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9804 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9806 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9808 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9811 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9812 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
9813 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
9815 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
9817 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
9819 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
9821 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
9823 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
9825 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
9828 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
9829 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
9830 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
9832 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9834 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
9836 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9838 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
9840 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
9842 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
9845 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
9846 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
9847 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
9849 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
9851 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9853 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9855 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9857 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9859 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
9862 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
9863 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
9864 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
9866 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9868 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9870 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
9872 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
9874 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
9876 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
9879 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
9880 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
9881 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
9883 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9885 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9887 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9889 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9891 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9893 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9896 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
9897 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
9898 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
9900 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
9902 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
9904 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
9906 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
9908 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
9951 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9952 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9953 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
9955 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
9957 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
9959 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
9961 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
9963 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
9966 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
9967 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
9968 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9970 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
9972 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9975 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9976 #define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
9977 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9979 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9981 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9984 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9985 #define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
9986 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9988 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
9990 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9992 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9994 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
9997 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9998 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
9999 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10001 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10003 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10005 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10007 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10009 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10011 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10014 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10015 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10016 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10018 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10020 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10022 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10024 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10026 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10028 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10038 #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10039 #define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10040 #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10042 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10044 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10046 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10049 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10050 #define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
10051 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10053 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10055 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10058 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10059 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10060 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10062 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10064 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10066 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10068 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10070 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10072 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10075 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10076 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10077 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10079 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10081 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10083 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10085 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10087 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10089 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10109 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10110 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
10111 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10113 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
10121 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10122 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
10123 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
10135 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10136 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10137 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10139 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10141 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10143 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10146 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10147 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10148 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10150 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10152 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10154 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10156 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10158 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10160 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10174 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
10175 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10176 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
10178 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
10276 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10277 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10278 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10280 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10282 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10284 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10287 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10288 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10289 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10291 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10293 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10295 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10297 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10299 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10301 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10337 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10338 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10339 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10341 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10343 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10345 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10347 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10349 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10351 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10354 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10355 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
10356 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10358 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10360 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10362 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10364 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10366 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10368 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10371 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10372 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
10373 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10375 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10377 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10380 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10381 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
10382 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10384 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10386 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10389 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10390 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
10391 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10393 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10395 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10398 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10399 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
10400 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
10402 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
10404 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
10407 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
10408 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
10409 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
10411 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
10413 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
10416 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
10417 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
10418 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
10420 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10422 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10424 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10427 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10428 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
10429 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10431 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10433 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10435 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10437 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10439 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10441 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
10444 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10445 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
10446 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
10448 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
10450 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
10452 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
10454 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
10456 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
10458 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
10461 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
10462 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
10463 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
10465 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
10467 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
10469 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10471 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
10473 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10475 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
10478 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
10479 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
10480 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10482 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
10484 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10486 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10488 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10490 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10492 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
10495 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
10496 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
10497 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
10499 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10501 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10503 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
10505 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
10507 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
10509 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
10512 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
10513 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
10514 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
10516 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10518 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10520 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10522 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10524 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10526 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10529 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
10530 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
10531 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
10533 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
10535 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
10537 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
10539 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
10541 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
10594 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10595 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10596 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10598 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
10600 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
10602 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10604 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
10606 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10609 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
10610 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
10611 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
10613 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10615 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10618 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10619 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
10620 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10622 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10624 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10627 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10628 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10629 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
10631 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10633 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
10635 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
10637 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10640 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10641 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
10642 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10644 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10646 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10648 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10650 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10652 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1
10654 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10657 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10658 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10659 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10661 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10663 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10665 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10667 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10669 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10671 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10691 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10692 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10693 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10695 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10697 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10699 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10702 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
10703 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
10704 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10706 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10708 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10711 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10712 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10713 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10715 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10717 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
10719 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10721 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10723 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10725 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10728 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10729 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10730 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10732 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10734 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10736 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10738 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10740 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10742 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10765 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10766 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10767 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10769 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10771 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10773 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10776 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10777 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10778 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10780 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10782 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10784 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10786 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10788 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10790 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10840 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10841 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10842 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10844 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10846 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10848 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10851 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10852 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10853 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10855 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10857 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10859 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10861 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10863 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10865 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1