Lines Matching +full:0 +full:x1200000
16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
18 #define MS_WIN(addr) (addr & 0x0ffc0000)
22 #define CRB_BLK(off) ((off >> 20) & 0x3f)
23 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
24 #define CRB_WINDOW_2M (0x130060)
25 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
26 #define CRB_INDIRECT_2M (0x1e0000UL)
57 {{{0, 0, 0, 0} } }, /* 0: PCI */
58 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
59 {1, 0x0110000, 0x0120000, 0x130000},
60 {1, 0x0120000, 0x0122000, 0x124000},
61 {1, 0x0130000, 0x0132000, 0x126000},
62 {1, 0x0140000, 0x0142000, 0x128000},
63 {1, 0x0150000, 0x0152000, 0x12a000},
64 {1, 0x0160000, 0x0170000, 0x110000},
65 {1, 0x0170000, 0x0172000, 0x12e000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {0, 0x0000000, 0x0000000, 0x000000},
72 {1, 0x01e0000, 0x01e0800, 0x122000},
73 {0, 0x0000000, 0x0000000, 0x000000} } },
74 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
75 {{{0, 0, 0, 0} } }, /* 3: */
76 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
77 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
78 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
79 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
80 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {1, 0x08f0000, 0x08f2000, 0x172000} } },
96 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {1, 0x09f0000, 0x09f2000, 0x176000} } },
112 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
128 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
144 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
145 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
146 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
147 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
148 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
149 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
150 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
151 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
152 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
153 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
154 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
155 {{{0, 0, 0, 0} } }, /* 23: */
156 {{{0, 0, 0, 0} } }, /* 24: */
157 {{{0, 0, 0, 0} } }, /* 25: */
158 {{{0, 0, 0, 0} } }, /* 26: */
159 {{{0, 0, 0, 0} } }, /* 27: */
160 {{{0, 0, 0, 0} } }, /* 28: */
161 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
162 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
163 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
164 {{{0} } }, /* 32: PCI */
165 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
166 {1, 0x2110000, 0x2120000, 0x130000},
167 {1, 0x2120000, 0x2122000, 0x124000},
168 {1, 0x2130000, 0x2132000, 0x126000},
169 {1, 0x2140000, 0x2142000, 0x128000},
170 {1, 0x2150000, 0x2152000, 0x12a000},
171 {1, 0x2160000, 0x2170000, 0x110000},
172 {1, 0x2170000, 0x2172000, 0x12e000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000} } },
181 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
182 {{{0} } }, /* 35: */
183 {{{0} } }, /* 36: */
184 {{{0} } }, /* 37: */
185 {{{0} } }, /* 38: */
186 {{{0} } }, /* 39: */
187 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
188 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
189 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
190 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
191 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
192 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
193 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
194 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
195 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
196 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
197 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
198 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
199 {{{0} } }, /* 52: */
200 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
201 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
202 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
203 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
204 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
205 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
206 {{{0} } }, /* 59: I2C0 */
207 {{{0} } }, /* 60: I2C1 */
208 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
209 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
210 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
218 0,
222 0,
245 0,
248 0,
250 0,
253 0,
254 0,
255 0,
256 0,
257 0,
259 0,
270 0,
275 0,
279 0,
281 0,
286 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
295 int done = 0, timeout = 0; in netxen_pcie_sem_lock()
309 return 0; in netxen_pcie_sem_lock()
321 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); in netxen_niu_xg_init_port()
322 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5); in netxen_niu_xg_init_port()
325 return 0; in netxen_niu_xg_init_port()
335 return 0; in netxen_niu_disable_xg_port()
340 mac_cfg = 0; in netxen_niu_disable_xg_port()
342 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg)) in netxen_niu_disable_xg_port()
344 return 0; in netxen_niu_disable_xg_port()
350 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
352 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
359 u32 cnt = 0; in netxen_p2_nic_set_promisc()
360 __u32 reg = 0x0200; in netxen_p2_nic_set_promisc()
367 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port)); in netxen_p2_nic_set_promisc()
368 mac_cfg &= ~0x4; in netxen_p2_nic_set_promisc()
369 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); in netxen_p2_nic_set_promisc()
373 reg = (0x20 << port); in netxen_p2_nic_set_promisc()
385 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port)); in netxen_p2_nic_set_promisc()
388 reg = (reg | 0x2000UL); in netxen_p2_nic_set_promisc()
390 reg = (reg & ~0x2000UL); in netxen_p2_nic_set_promisc()
393 reg = (reg | 0x1000UL); in netxen_p2_nic_set_promisc()
395 reg = (reg & ~0x1000UL); in netxen_p2_nic_set_promisc()
398 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); in netxen_p2_nic_set_promisc()
401 mac_cfg |= 0x4; in netxen_p2_nic_set_promisc()
402 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); in netxen_p2_nic_set_promisc()
404 return 0; in netxen_p2_nic_set_promisc()
417 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24); in netxen_p2_nic_set_mac_addr()
421 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy); in netxen_p2_nic_set_mac_addr()
422 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy); in netxen_p2_nic_set_mac_addr()
430 return 0; in netxen_p2_nic_set_mac_addr()
436 u32 val = 0; in netxen_nic_enable_mcast_filter()
441 return 0; in netxen_nic_enable_mcast_filter()
448 val = 0xffffff; in netxen_nic_enable_mcast_filter()
449 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); in netxen_nic_enable_mcast_filter()
450 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); in netxen_nic_enable_mcast_filter()
459 return 0; in netxen_nic_enable_mcast_filter()
465 u32 val = 0; in netxen_nic_disable_mcast_filter()
470 return 0; in netxen_nic_disable_mcast_filter()
477 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); in netxen_nic_disable_mcast_filter()
479 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); in netxen_nic_disable_mcast_filter()
481 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); in netxen_nic_disable_mcast_filter()
482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); in netxen_nic_disable_mcast_filter()
484 adapter->mc_enabled = 0; in netxen_nic_disable_mcast_filter()
485 return 0; in netxen_nic_disable_mcast_filter()
492 u32 hi = 0, lo = 0; in netxen_nic_set_mcast_addr()
501 return 0; in netxen_nic_set_mcast_addr()
540 i = 0; in netxen_p2_nic_set_multi()
557 i = 0; in netxen_send_cmd_descs()
582 pbuf->frag_count = 0; in netxen_send_cmd_descs()
598 return 0; in netxen_send_cmd_descs()
608 memset(&req, 0, sizeof(nx_nic_req_t)); in nx_p3_sre_macaddr_change()
614 mac_req = (nx_mac_req_t *)&req.words[0]; in nx_p3_sre_macaddr_change()
633 return 0; in nx_p3_nic_add_mac()
652 0xff, 0xff, 0xff, 0xff, 0xff, 0xff in netxen_p3_nic_set_multi()
701 memset(&req, 0, sizeof(nx_nic_req_t)); in netxen_p3_nic_set_promisc()
709 req.words[0] = cpu_to_le64(mode); in netxen_p3_nic_set_promisc()
733 return 0; in netxen_p3_nic_set_mac_addr()
747 memset(&req, 0, sizeof(nx_nic_req_t)); in netxen_config_intr_coalesce()
748 memset(word, 0, sizeof(word)); in netxen_config_intr_coalesce()
752 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16); in netxen_config_intr_coalesce()
753 req.req_hdr = cpu_to_le64(word[0]); in netxen_config_intr_coalesce()
755 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal)); in netxen_config_intr_coalesce()
756 for (i = 0; i < 6; i++) in netxen_config_intr_coalesce()
760 if (rv != 0) { in netxen_config_intr_coalesce()
772 int rv = 0; in netxen_config_hw_lro()
775 return 0; in netxen_config_hw_lro()
777 memset(&req, 0, sizeof(nx_nic_req_t)); in netxen_config_hw_lro()
784 req.words[0] = cpu_to_le64(enable); in netxen_config_hw_lro()
787 if (rv != 0) { in netxen_config_hw_lro()
799 int rv = 0; in netxen_config_bridged_mode()
804 memset(&req, 0, sizeof(nx_nic_req_t)); in netxen_config_bridged_mode()
812 req.words[0] = cpu_to_le64(enable); in netxen_config_bridged_mode()
815 if (rv != 0) { in netxen_config_bridged_mode()
826 #define RSS_HASHTYPE_IP_TCP 0x3
835 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, in netxen_config_rss()
836 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, in netxen_config_rss()
837 0x255b0ec26d5a56daULL in netxen_config_rss()
841 memset(&req, 0, sizeof(nx_nic_req_t)); in netxen_config_rss()
849 * bits 3-0: hash_method in netxen_config_rss()
857 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | in netxen_config_rss()
858 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | in netxen_config_rss()
859 ((u64)(enable & 0x1) << 8) | in netxen_config_rss()
860 ((0x7ULL) << 48); in netxen_config_rss()
861 req.words[0] = cpu_to_le64(word); in netxen_config_rss()
862 for (i = 0; i < ARRAY_SIZE(key); i++) in netxen_config_rss()
867 if (rv != 0) { in netxen_config_rss()
881 memset(&req, 0, sizeof(nx_nic_req_t)); in netxen_config_ipaddr()
887 req.words[0] = cpu_to_le64(cmd); in netxen_config_ipaddr()
891 if (rv != 0) { in netxen_config_ipaddr()
892 printk(KERN_ERR "%s: could not notify %s IP 0x%x request\n", in netxen_config_ipaddr()
905 memset(&req, 0, sizeof(nx_nic_req_t)); in netxen_linkevent_request()
910 req.words[0] = cpu_to_le64(enable | (enable << 8)); in netxen_linkevent_request()
913 if (rv != 0) { in netxen_linkevent_request()
928 return 0; in netxen_send_lro_cleanup()
930 memset(&req, 0, sizeof(nx_nic_req_t)); in netxen_send_lro_cleanup()
940 if (rv != 0) { in netxen_send_lro_cleanup()
949 * @returns 0 on success, negative on failure
957 int rc = 0; in netxen_nic_change_mtu()
977 for (i = 0; i < size / sizeof(u32); i++) { in netxen_get_flash_block()
995 return 0; in netxen_get_flash_block()
1008 if (*mac == ~0ULL) { in netxen_get_flash_mac_addr()
1017 if (*mac == ~0ULL) in netxen_get_flash_mac_addr()
1020 return 0; in netxen_get_flash_mac_addr()
1039 return 0; in netxen_p3_get_mac_addr()
1070 } while (--count > 0); in netxen_nic_pci_set_crbwindow_128M()
1072 if (count > 0) in netxen_nic_pci_set_crbwindow_128M()
1077 * Returns < 0 if off is not valid,
1080 * 0 if no window access is needed. 'off' is set to 2M addr
1103 return 0; in netxen_nic_pci_get_crb_addr_2M()
1133 "failed to set CRB window to %d off 0x%lx\n", in netxen_nic_pci_set_crbwindow_2M()
1153 if (adapter->ahw.pci_len0 == 0) in netxen_nic_map_indirect_address_128M()
1156 mem_base = pci_resource_start(adapter->pdev, 0); in netxen_nic_map_indirect_address_128M()
1176 } else { /* Window 0 */ in netxen_nic_hw_write_wx_128M()
1178 netxen_nic_pci_set_crbwindow_128M(adapter, 0); in netxen_nic_hw_write_wx_128M()
1188 return 0; in netxen_nic_hw_write_wx_128M()
1204 } else { /* Window 0 */ in netxen_nic_hw_read_wx_128M()
1206 netxen_nic_pci_set_crbwindow_128M(adapter, 0); in netxen_nic_hw_read_wx_128M()
1228 if (rv == 0) { in netxen_nic_hw_write_wx_2M()
1230 return 0; in netxen_nic_hw_write_wx_2M()
1233 if (rv > 0) { in netxen_nic_hw_write_wx_2M()
1241 return 0; in netxen_nic_hw_write_wx_2M()
1245 "%s: invalid offset: 0x%016lx\n", __func__, off); in netxen_nic_hw_write_wx_2M()
1260 if (rv == 0) in netxen_nic_hw_read_wx_2M()
1263 if (rv > 0) { in netxen_nic_hw_read_wx_2M()
1275 "%s: invalid offset: 0x%016lx\n", __func__, off); in netxen_nic_hw_read_wx_2M()
1338 return 0; in netxen_nic_pci_set_window_128M()
1342 return 0; in netxen_nic_pci_set_window_128M()
1362 return 0; in netxen_nic_pci_set_window_2M()
1377 if (ret != 0) in netxen_nic_pci_mem_access_direct()
1387 mem_base = pci_resource_start(adapter->pdev, 0) + in netxen_nic_pci_mem_access_direct()
1398 if (op == 0) /* read */ in netxen_nic_pci_mem_access_direct()
1467 off_hi = 0; in netxen_nic_pci_mem_write_128M()
1473 if (adapter->ahw.pci_len0 != 0) { in netxen_nic_pci_mem_write_128M()
1483 netxen_nic_pci_set_crbwindow_128M(adapter, 0); in netxen_nic_pci_mem_write_128M()
1487 writel(data & 0xffffffff, (mem_crb + data_lo)); in netxen_nic_pci_mem_write_128M()
1488 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi)); in netxen_nic_pci_mem_write_128M()
1493 for (j = 0; j < MAX_CTL_CHECK; j++) { in netxen_nic_pci_mem_write_128M()
1495 if ((temp & TA_CTL_BUSY) == 0) in netxen_nic_pci_mem_write_128M()
1505 ret = 0; in netxen_nic_pci_mem_write_128M()
1545 off_hi = 0; in netxen_nic_pci_mem_read_128M()
1551 if (adapter->ahw.pci_len0 != 0) { in netxen_nic_pci_mem_read_128M()
1553 off, data, 0); in netxen_nic_pci_mem_read_128M()
1561 netxen_nic_pci_set_crbwindow_128M(adapter, 0); in netxen_nic_pci_mem_read_128M()
1568 for (j = 0; j < MAX_CTL_CHECK; j++) { in netxen_nic_pci_mem_read_128M()
1570 if ((temp & TA_CTL_BUSY) == 0) in netxen_nic_pci_mem_read_128M()
1585 ret = 0; in netxen_nic_pci_mem_read_128M()
1626 off8 = off & 0xfffffff8; in netxen_nic_pci_mem_write_2M()
1631 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); in netxen_nic_pci_mem_write_2M()
1633 writel(data & 0xffffffff, in netxen_nic_pci_mem_write_2M()
1635 writel((data >> 32) & 0xffffffff, in netxen_nic_pci_mem_write_2M()
1642 for (j = 0; j < MAX_CTL_CHECK; j++) { in netxen_nic_pci_mem_write_2M()
1644 if ((temp & TA_CTL_BUSY) == 0) in netxen_nic_pci_mem_write_2M()
1654 ret = 0; in netxen_nic_pci_mem_write_2M()
1690 off, data, 0); in netxen_nic_pci_mem_read_2M()
1696 off8 = off & 0xfffffff8; in netxen_nic_pci_mem_read_2M()
1701 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); in netxen_nic_pci_mem_read_2M()
1705 for (j = 0; j < MAX_CTL_CHECK; j++) { in netxen_nic_pci_mem_read_2M()
1707 if ((temp & TA_CTL_BUSY) == 0) in netxen_nic_pci_mem_read_2M()
1720 ret = 0; in netxen_nic_pci_mem_read_2M()
1788 if ((gpio & 0x8000) == 0) in netxen_nic_get_board_info()
1833 return 0; in netxen_nic_get_board_info()
1840 if (adapter->physical_port == 0) in netxen_nic_set_mtu_xgb()
1844 return 0; in netxen_nic_set_mtu_xgb()
1854 adapter->link_speed = 0; in netxen_nic_set_link_parameters()
1872 &status) == 0) { in netxen_nic_set_link_parameters()
1875 case 0: in netxen_nic_set_link_parameters()
1885 adapter->link_speed = 0; in netxen_nic_set_link_parameters()
1889 case 0: in netxen_nic_set_link_parameters()
1902 &autoneg) == 0) in netxen_nic_set_link_parameters()
1908 adapter->link_speed = 0; in netxen_nic_set_link_parameters()
1920 return 0; in netxen_nic_wol_supported()
1929 return 0; in netxen_nic_wol_supported()
1936 int loop_cnt, i, rv = 0, timeout_flag; in netxen_md_cntrl()
1944 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { in netxen_md_cntrl()
1945 for (i = 0; i < sizeof(crtEntry->opcode) * 8; i++) { in netxen_md_cntrl()
1946 opcode = (crtEntry->opcode & (0x1 << i)); in netxen_md_cntrl()
1987 for (timeout_flag = 0; in netxen_md_cntrl()
2071 u64 addr, value = 0; in netxen_md_rdmem()
2072 int i = 0, loop_cnt; in netxen_md_rdmem()
2078 for (i = 0; i < loop_cnt; i++) { in netxen_md_rdmem()
2100 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { in netxen_md_rd_crb()
2115 int i, count = 0; in netxen_md_rdrom()
2131 for (i = 0; i < size; i++) { in netxen_md_rdrom()
2132 waddr = fl_addr & 0xFFFF0000; in netxen_md_rdrom()
2134 raddr = FLASH_ROM_DATA + (fl_addr & 0x0000FFFF); in netxen_md_rdrom()
2149 int loop_cnt, i, k, timeout_flag = 0; in netxen_md_L2Cache()
2163 for (i = 0; i < loop_cnt; i++) { in netxen_md_L2Cache()
2173 for (timeout_flag = 0; !timeout_flag && in netxen_md_L2Cache()
2174 ((cntl_value_r & cacheEntry->poll_mask) != 0);) { in netxen_md_L2Cache()
2188 for (k = 0; k < read_cnt; k++) { in netxen_md_L2Cache()
2218 for (i = 0; i < loop_cnt; i++) { in netxen_md_L1Cache()
2223 for (k = 0; k < read_cnt; k++) { in netxen_md_L1Cache()
2247 for (i = 0; i < loop_cnt; i++) { in netxen_md_rdocm()
2260 int loop_cnt = 0; in netxen_md_rdmux()
2267 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) { in netxen_md_rdmux()
2290 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count; in netxen_md_rdqueue()
2294 for (k = 0; k < read_cnt; k++) { in netxen_md_rdqueue()
2314 if (esize < 0) { in netxen_md_entry_err_chk()
2327 return 0; in netxen_md_entry_err_chk()
2333 int rv = 0, sane_start = 0, sane_end = 0; in netxen_parse_md_template()
2341 if ((capture_mask & 0x3) != 0x3) { in netxen_parse_md_template()
2356 for (e_cnt = 0, buff_level = 0; e_cnt < num_of_entries; e_cnt++) { in netxen_parse_md_template()
2383 if (rv < 0) in netxen_parse_md_template()
2394 if (rv < 0) in netxen_parse_md_template()
2405 if (rv < 0) in netxen_parse_md_template()
2418 if (rv < 0) in netxen_parse_md_template()
2429 if (rv < 0) in netxen_parse_md_template()
2439 if (rv < 0) in netxen_parse_md_template()
2449 if (rv < 0) in netxen_parse_md_template()
2459 if (rv < 0) in netxen_parse_md_template()
2475 return 0; in netxen_parse_md_template()
2481 int ret = 0; in netxen_collect_minidump()
2501 int i, k, data_size = 0; in netxen_dump_fw()
2507 for (i = 0x2, k = 1; (i & NX_DUMP_MASK_MAX); i <<= 1, k++) { in netxen_dump_fw()
2513 "Invalid cap sizes for capture_mask=0x%x\n", in netxen_dump_fw()
2527 adapter->mdump.has_valid_dump = 0; in netxen_dump_fw()
2528 adapter->mdump.md_dump_size = 0; in netxen_dump_fw()