3293 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3303 		phyreg = readl(base + NvRegSlotTime);  in nv_force_linkspeed()
3304 		phyreg &= ~(0x3FF00);  in nv_force_linkspeed()
3306 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3308 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3310 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_force_linkspeed()
3311 		writel(phyreg, base + NvRegSlotTime);  in nv_force_linkspeed()
3314 	phyreg = readl(base + NvRegPhyInterface);  in nv_force_linkspeed()
3315 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_force_linkspeed()
3317 		phyreg |= PHY_HALF;  in nv_force_linkspeed()
3319 		phyreg |= PHY_100;  in nv_force_linkspeed()
3322 		phyreg |= PHY_1000;  in nv_force_linkspeed()
3323 	writel(phyreg, base + NvRegPhyInterface);  in nv_force_linkspeed()
3325 	if (phyreg & PHY_RGMII) {  in nv_force_linkspeed()
3377 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3486 		phyreg = readl(base + NvRegSlotTime);  in nv_update_linkspeed()
3487 		phyreg &= ~(0x3FF00);  in nv_update_linkspeed()
3490 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_update_linkspeed()
3492 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_update_linkspeed()
3493 		writel(phyreg, base + NvRegSlotTime);  in nv_update_linkspeed()
3496 	phyreg = readl(base + NvRegPhyInterface);  in nv_update_linkspeed()
3497 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_update_linkspeed()
3499 		phyreg |= PHY_HALF;  in nv_update_linkspeed()
3501 		phyreg |= PHY_100;  in nv_update_linkspeed()
3503 		phyreg |= PHY_1000;  in nv_update_linkspeed()
3504 	writel(phyreg, base + NvRegPhyInterface);  in nv_update_linkspeed()
3507 	if (phyreg & PHY_RGMII) {  in nv_update_linkspeed()