Lines Matching refs:mii_rw
1128 static int mii_rw(struct net_device *dev, int addr, int miireg, int value) in mii_rw() function
1171 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) in phy_reset()
1180 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1205 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) in init_realtek_8211b()
1227 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in init_realtek_8211c()
1229 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) in init_realtek_8211c()
1231 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1234 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in init_realtek_8211c()
1237 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) in init_realtek_8211c()
1240 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1252 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201()
1255 if (mii_rw(dev, np->phyaddr, in init_realtek_8201()
1268 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1271 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1275 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1278 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1292 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in init_cicada()
1295 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) in init_cicada()
1297 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in init_cicada()
1299 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) in init_cicada()
1302 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in init_cicada()
1304 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) in init_cicada()
1314 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1317 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1320 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1322 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1324 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1328 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1330 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1333 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1336 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1340 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1342 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1344 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1346 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1349 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1352 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1354 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1356 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1360 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1362 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1365 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1381 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1383 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1414 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1418 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1428 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1431 mii_control_1000 = mii_rw(dev, np->phyaddr, in phy_init()
1439 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1447 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1455 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1504 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1507 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1511 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) in phy_init()
3300 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_force_linkspeed()
3384 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_update_linkspeed()
3397 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3398 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3433 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3434 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3438 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3439 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3506 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
4364 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_link_ksettings()
4374 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_link_ksettings()
4469 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4483 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4486 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4490 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4495 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4506 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4513 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4532 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4536 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4538 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4541 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4554 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4615 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4625 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4827 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4833 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4837 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4839 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4868 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_loopback()
4878 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); in nv_set_loopback()
5022 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5023 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5452 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5453 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5653 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5654 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
6041 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); in nv_probe()
6046 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); in nv_probe()
6062 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
6076 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
6156 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
6157 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
6160 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
6161 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
6164 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
6166 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()