Lines Matching refs:NVREG_IRQSTAT_MASK
97 #define NVREG_IRQSTAT_MASK 0x83ff macro
2746 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; in nv_tx_timeout()
2748 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; in nv_tx_timeout()
3968 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; in nv_nic_irq_test()
3971 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; in nv_nic_irq_test()
4224 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in nv_do_nic_poll()
4226 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); in nv_do_nic_poll()
5116 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in nv_interrupt_test()
5118 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); in nv_interrupt_test()
5286 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in nv_self_test()
5288 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); in nv_self_test()
5519 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in nv_open()
5570 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in nv_open()