Lines Matching +full:8 +full:- +full:n +full:- +full:1
2 * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2010 Exar Corp.
21 /* General Control-Status Registers */
24 #define GEN_INTR_TXDMA s2BIT(1)
27 #define GEN_INTR_TXTRAFFIC s2BIT(8)
42 u8 unused0[0x100 - 0x10];
46 #define SW_RESET_XENA vBIT(0xA5,0,8)
47 #define SW_RESET_FLASH vBIT(0xA5,8,8)
48 #define SW_RESET_EOI vBIT(0xA5,16,8)
58 #define ADAPTER_STATUS_RDMA_READY s2BIT(1)
64 #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
65 #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
66 #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
83 #define SERR_SOURCE_TXDMA s2BIT(1)
106 #define PCI_MODE_32_BITS s2BIT(8)
109 u8 unused_0[0x800 - 0x128];
111 /* PCI-X Controller registers */
115 #define PIC_INT_FLSH s2BIT(1)
124 #define PCIX_INT_REG_ECC_DB_ERR s2BIT(1)
125 #define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8)
155 #define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8)
165 #define IIC_INT_REG_ACK_ERR s2BIT(8)
172 #define GPIO_INT_REG_LINK_DOWN s2BIT(1)
175 #define GPIO_INT_MASK_LINK_DOWN s2BIT(1)
182 #define TX_TRAFFIC_INT_n(n) s2BIT(n) argument
186 #define RX_TRAFFIC_INT_n(n) s2BIT(n) argument
192 #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5) argument
196 #define SWAPPER_CTRL_PIF_R_SE s2BIT(1)
197 #define SWAPPER_CTRL_PIF_W_FE s2BIT(8)
223 #define SCHED_INT_CTRL_ONE_SHOT s2BIT(1)
232 #define STATREQTO_VAL(n) TBD argument
246 #define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
251 #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
255 #define STAT_BC(n) vBIT(n,4,12) argument
260 #define STAT_CFG_ONE_SHOT_EN s2BIT(1)
261 #define STAT_CFG_STAT_NS_EN s2BIT(8)
263 #define STAT_TRSF_PER(n) TBD argument
265 #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32) argument
286 #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
297 #define GPIO_CTRL_GPIO_0 s2BIT(8)
300 #define EXT_REQ_EN s2BIT(1)
303 u8 unused7_1[0x230 - 0x208];
311 u8 unused7_2[0x800 - 0x248];
317 #define TXDMA_TDA_INT s2BIT(1)
334 #define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
335 #define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
343 #define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
344 #define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
345 #define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
346 #define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
347 #define PCC_SM_ERR_ALARM vBIT(0xff,32,8)
348 #define PCC_WR_ERR_ALARM vBIT(0xff,40,8)
349 #define PCC_N_SERR vBIT(0xff,48,8)
354 #define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
387 u8 unused8[0x100 - 0xB8];
393 #define X_MAX_FIFOS 8
421 #define TX_FIFO_PARTITION_PRI_1 1
439 #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) argument
442 #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) argument
443 #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) argument
446 #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) argument
447 #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) argument
448 #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) argument
451 #define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) argument
452 #define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) argument
453 #define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) argument
454 #define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) argument
458 #define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
467 u8 unused9[0x700 - 0x178];
471 u8 unused10[0x1800 - 0x1708];
477 #define RXDMA_INT_RPA_INT_M s2BIT(1)
482 #define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
483 #define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
495 #define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
496 #define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
499 #define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
501 #define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
506 #define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
507 #define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
508 #define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
509 #define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
510 #define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
511 #define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
531 u8 unused11[0x100 - 0x88];
545 #define RX_QUEUE_PRI_1 1
559 /* Per-ring controller regs */
560 #define RX_MAX_RINGS 8
570 #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
604 #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) argument
607 #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) argument
610 #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) argument
611 #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) argument
612 #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) argument
615 #define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) argument
616 #define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) argument
617 #define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) argument
618 #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) argument
621 #define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1)
631 u8 unused12[0x700 - 0x1F0];
635 u8 unused13[0x2000 - 0x1f08];
641 #define MAC_INT_STATUS_RMAC_INT s2BIT(1)
657 #define RMAC_FRM_RCVD_INT s2BIT(1)
662 #define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8)
676 s2BIT(8) | s2BIT(9) | s2BIT(10)|\
684 u8 unused14[0x100 - 0x40];
688 #define MAC_CFG_RMAC_ENABLE s2BIT(1)
695 #define MAC_RMAC_DISCARD_PFRM s2BIT(8)
698 #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
701 #define TMAC_AVG_IPG(val) vBIT(val,0,8)
710 #define RMAC_ERR_FCS_ACCEPT s2BIT(1)
711 #define RMAC_ERR_TOO_LONG s2BIT(1)
712 #define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1)
737 #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) argument
740 #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) argument
744 #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) argument
750 #define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
751 #define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
760 #define RMAC_PAUSE_RX s2BIT(1)
761 #define RMAC_PAUSE_RX_ENABLE s2BIT(1)
771 #define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
772 #define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
773 #define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) argument
776 #define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) argument
785 u64 rts_frm_len_n[8];
805 #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) argument
808 #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
809 #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
815 #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) argument
817 #define RTS_DS_MEM_DATA(n) vBIT(n,0,8) argument
819 u8 unused16[0x700 - 0x220];
824 u8 unused17[0x2800 - 0x2708];
848 u8 unused18[0x100 - 0x28];
852 #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) argument
853 #define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) argument
854 #define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) argument
855 #define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) argument
856 #define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) argument
857 #define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) argument
858 #define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) argument
859 #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) argument
870 u64 mc_red_thresh_q[8];
872 u8 unused19[0x200 - 0x168];
874 u8 unused20[0x220 - 0x208];
882 u8 unused21[0x240 - 0x228];
884 u8 unused22[0x260 - 0x248];
886 u8 unused23[0x280 - 0x268];
888 u8 unused24[0x300 - 0x288];
891 u8 unused24_1[0x360 - 0x308];
895 u8 unused24_2[0x640 - 0x368];
899 u8 unused24_3[0x660 - 0x648];
902 u8 unused25[0x700 - 0x668];
905 u8 unused26[0x3000 - 0x2f08];
912 #define XGXS_INT_STATUS_RXGXS s2BIT(1)
915 #define XGXS_INT_MASK_RXGXS s2BIT(1)
932 u8 unused27[0x100 - 0x40];
945 #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)