Lines Matching +full:bit +full:- +full:banging
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Questions/comments/discussion to linux-ns83820@kvack.org.
16 * 20010414 0.1 - created
17 * 20010622 0.2 - basic rx and tx.
18 * 20010711 0.3 - added duplex and link state detection support.
19 * 20010713 0.4 - zero copy, no hangs.
20 * 0.5 - 64 bit dma support (davem will hate me for this)
21 * - disable jumbo frames to avoid tx hangs
22 * - work around tx deadlocks on my 1.02 card via
24 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
25 * 20010816 0.7 - misc cleanups
26 * 20010826 0.8 - fix critical zero copy bugs
27 * 0.9 - internal experiment
28 * 20010827 0.10 - fix ia64 unaligned access.
29 * 20010906 0.11 - accept all packets with checksum errors as
31 * - fix >> 32 bugs
32 * 0.12 - add statistics counters
33 * - add allmulti/promisc support
34 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
35 * 20011204 0.13a - optical transceiver support added
37 * 20011205 0.13b - call register_netdev earlier in initialization
39 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
43 * 20020610 0.18 - actually use the pci dma api for highmem
44 * - remove pci latency register fiddling
45 * 0.19 - better bist support
46 * - add ihr and reset_phy parameters
47 * - gmii bus probing
48 * - fix missed txok introduced during performance
50 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
51 * 20040828 0.21 - add hardware vlan accleration
53 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
54 * - removal of dead code from Adrian Bunk
55 * - fix half duplex collision behaviour
60 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
71 * Cameo SOHO-GA2000T SOHO-GA2500T
72 * D-Link DGE-500T
73 * PureData PDP8023Z-TG
88 #include <linux/dma-mapping.h>
115 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
455 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
461 if (test_and_clear_bit(0, &dev->rx_info.idle)) { in kick_rx()
463 writel(dev->rx_info.phy_descs + in kick_rx()
464 (4 * DESC_SIZE * dev->rx_info.next_rx), in kick_rx()
465 dev->base + RXDP); in kick_rx()
466 if (dev->rx_info.next_rx == dev->rx_info.next_empty) in kick_rx()
467 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n", in kick_rx()
468 ndev->name); in kick_rx()
473 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
475 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
481 * ownership bit. While the hardware does support the use of a
484 * This will also make bugs a bit more obvious. The current code
499 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_D…
507 next_empty = dev->rx_info.next_empty; in ns83820_add_rx_skb()
517 dev->rx_info.next_empty, in ns83820_add_rx_skb()
518 dev->rx_info.nr_used, in ns83820_add_rx_skb()
519 dev->rx_info.next_rx in ns83820_add_rx_skb()
523 sg = dev->rx_info.descs + (next_empty * DESC_SIZE); in ns83820_add_rx_skb()
524 BUG_ON(NULL != dev->rx_info.skbs[next_empty]); in ns83820_add_rx_skb()
525 dev->rx_info.skbs[next_empty] = skb; in ns83820_add_rx_skb()
527 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC; in ns83820_add_rx_skb()
529 buf = dma_map_single(&dev->pci_dev->dev, skb->data, REAL_RX_BUF_SIZE, in ns83820_add_rx_skb()
533 if (likely(next_empty != dev->rx_info.next_rx)) in ns83820_add_rx_skb()
534 …dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx… in ns83820_add_rx_skb()
550 spin_lock_irqsave(&dev->rx_info.lock, flags); in rx_refill()
560 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16)); in rx_refill()
562 spin_lock_irqsave(&dev->rx_info.lock, flags); in rx_refill()
565 spin_unlock_irqrestore(&dev->rx_info.lock, flags); in rx_refill()
572 spin_unlock_irqrestore(&dev->rx_info.lock, flags); in rx_refill()
574 return i ? 0 : -ENOMEM; in rx_refill()
586 struct net_device *ndev = dev->ndev; in queue_refill()
589 if (dev->rx_info.up) in queue_refill()
595 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0); in clear_rx_desc()
606 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; in phy_intr()
608 if (dev->CFG_cache & CFG_TBI_EN) { in phy_intr()
612 tbisr = readl(dev->base + TBISR); in phy_intr()
613 tanar = readl(dev->base + TANAR); in phy_intr()
614 tanlpar = readl(dev->base + TANLPAR); in phy_intr()
622 writel(readl(dev->base + TXCFG) in phy_intr()
624 dev->base + TXCFG); in phy_intr()
625 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
626 dev->base + RXCFG); in phy_intr()
628 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, in phy_intr()
629 dev->base + GPIOR); in phy_intr()
639 writel((readl(dev->base + TXCFG) in phy_intr()
641 dev->base + TXCFG); in phy_intr()
642 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, in phy_intr()
643 dev->base + RXCFG); in phy_intr()
645 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, in phy_intr()
646 dev->base + GPIOR); in phy_intr()
653 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS); in phy_intr()
665 writel(readl(dev->base + TXCFG) in phy_intr()
667 dev->base + TXCFG); in phy_intr()
668 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
669 dev->base + RXCFG); in phy_intr()
671 writel(readl(dev->base + TXCFG) in phy_intr()
673 dev->base + TXCFG); in phy_intr()
674 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), in phy_intr()
675 dev->base + RXCFG); in phy_intr()
679 ((new_cfg ^ dev->CFG_cache) != 0)) { in phy_intr()
680 writel(new_cfg, dev->base + CFG); in phy_intr()
681 dev->CFG_cache = new_cfg; in phy_intr()
684 dev->CFG_cache &= ~CFG_SPDSTS; in phy_intr()
685 dev->CFG_cache |= cfg & CFG_SPDSTS; in phy_intr()
691 dev->linkstate != newlinkstate) { in phy_intr()
695 ndev->name, in phy_intr()
699 dev->linkstate != newlinkstate) { in phy_intr()
701 printk(KERN_INFO "%s: link now down.\n", ndev->name); in phy_intr()
704 dev->linkstate = newlinkstate; in phy_intr()
715 dev->rx_info.idle = 1; in ns83820_setup_rx()
716 dev->rx_info.next_rx = 0; in ns83820_setup_rx()
717 dev->rx_info.next_rx_desc = dev->rx_info.descs; in ns83820_setup_rx()
718 dev->rx_info.next_empty = 0; in ns83820_setup_rx()
723 writel(0, dev->base + RXDP_HI); in ns83820_setup_rx()
724 writel(dev->rx_info.phy_descs, dev->base + RXDP); in ns83820_setup_rx()
730 spin_lock_irq(&dev->rx_info.lock); in ns83820_setup_rx()
732 writel(0x0001, dev->base + CCSR); in ns83820_setup_rx()
733 writel(0, dev->base + RFCR); in ns83820_setup_rx()
734 writel(0x7fc00000, dev->base + RFCR); in ns83820_setup_rx()
735 writel(0xffc00000, dev->base + RFCR); in ns83820_setup_rx()
737 dev->rx_info.up = 1; in ns83820_setup_rx()
742 spin_lock(&dev->misc_lock); in ns83820_setup_rx()
743 dev->IMR_cache |= ISR_PHY; in ns83820_setup_rx()
744 dev->IMR_cache |= ISR_RXRCMP; in ns83820_setup_rx()
745 //dev->IMR_cache |= ISR_RXERR; in ns83820_setup_rx()
746 //dev->IMR_cache |= ISR_RXOK; in ns83820_setup_rx()
747 dev->IMR_cache |= ISR_RXORN; in ns83820_setup_rx()
748 dev->IMR_cache |= ISR_RXSOVR; in ns83820_setup_rx()
749 dev->IMR_cache |= ISR_RXDESC; in ns83820_setup_rx()
750 dev->IMR_cache |= ISR_RXIDLE; in ns83820_setup_rx()
751 dev->IMR_cache |= ISR_TXDESC; in ns83820_setup_rx()
752 dev->IMR_cache |= ISR_TXIDLE; in ns83820_setup_rx()
754 writel(dev->IMR_cache, dev->base + IMR); in ns83820_setup_rx()
755 writel(1, dev->base + IER); in ns83820_setup_rx()
756 spin_unlock(&dev->misc_lock); in ns83820_setup_rx()
760 spin_unlock_irq(&dev->rx_info.lock); in ns83820_setup_rx()
773 spin_lock_irqsave(&dev->misc_lock, flags); in ns83820_cleanup_rx()
774 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE); in ns83820_cleanup_rx()
775 writel(dev->IMR_cache, dev->base + IMR); in ns83820_cleanup_rx()
776 spin_unlock_irqrestore(&dev->misc_lock, flags); in ns83820_cleanup_rx()
779 dev->rx_info.up = 0; in ns83820_cleanup_rx()
780 synchronize_irq(dev->pci_dev->irq); in ns83820_cleanup_rx()
783 readl(dev->base + IMR); in ns83820_cleanup_rx()
786 writel(0, dev->base + RXDP_HI); in ns83820_cleanup_rx()
787 writel(0, dev->base + RXDP); in ns83820_cleanup_rx()
790 struct sk_buff *skb = dev->rx_info.skbs[i]; in ns83820_cleanup_rx()
791 dev->rx_info.skbs[i] = NULL; in ns83820_cleanup_rx()
801 if (dev->rx_info.up) { in ns83820_rx_kick()
807 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4) in ns83820_rx_kick()
808 schedule_work(&dev->tq_refill); in ns83820_rx_kick()
811 if (dev->rx_info.idle) in ns83820_rx_kick()
812 printk(KERN_DEBUG "%s: BAD\n", ndev->name); in ns83820_rx_kick()
821 struct rx_info *info = &dev->rx_info;
831 readl(dev->base + RXDP),
832 (long)(dev->rx_info.phy_descs),
833 (int)dev->rx_info.next_rx,
834 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
835 (int)dev->rx_info.next_empty,
836 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
839 spin_lock_irqsave(&info->lock, flags);
840 if (!info->up)
844 next_rx = info->next_rx;
845 desc = info->next_rx_desc;
856 skb = info->skbs[next_rx];
857 info->skbs[next_rx] = NULL;
858 info->next_rx = (next_rx + 1) % NR_RX_DESC;
863 dma_unmap_single(&dev->pci_dev->dev, bufptr, RX_BUF_SIZE,
872 * also means that the OK bit in the descriptor
885 ndev->stats.rx_dropped++;
889 ndev->stats.multicast++;
890 ndev->stats.rx_packets++;
891 ndev->stats.rx_bytes += len;
893 skb->ip_summed = CHECKSUM_UNNECESSARY;
897 skb->protocol = eth_type_trans(skb, ndev);
913 next_rx = info->next_rx;
914 desc = info->descs + (DESC_SIZE * next_rx);
916 info->next_rx = next_rx;
917 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
924 spin_unlock_irqrestore(&info->lock, flags);
930 struct net_device *ndev = dev->ndev;
932 writel(ihr, dev->base + IHR);
934 spin_lock_irq(&dev->misc_lock);
935 dev->IMR_cache |= ISR_RXDESC;
936 writel(dev->IMR_cache, dev->base + IMR);
937 spin_unlock_irq(&dev->misc_lock);
948 dev, dev->tx_idx, dev->tx_free_idx);
949 writel(CR_TXE, dev->base + CR);
962 tx_done_idx = dev->tx_done_idx;
963 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
966 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
967 while ((tx_done_idx != dev->tx_free_idx) &&
974 ndev->stats.tx_errors++;
976 ndev->stats.tx_packets++;
978 ndev->stats.tx_bytes += cmdsts & 0xffff;
981 tx_done_idx, dev->tx_free_idx, cmdsts);
982 skb = dev->tx_skbs[tx_done_idx];
983 dev->tx_skbs[tx_done_idx] = NULL;
989 dma_unmap_single(&dev->pci_dev->dev, addr, len,
992 atomic_dec(&dev->nr_tx_skbs);
994 dma_unmap_page(&dev->pci_dev->dev, addr, len,
998 dev->tx_done_idx = tx_done_idx;
1001 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1019 struct sk_buff *skb = dev->tx_skbs[i];
1020 dev->tx_skbs[i] = NULL;
1022 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1023 dma_unmap_single(&dev->pci_dev->dev,
1028 atomic_dec(&dev->nr_tx_skbs);
1032 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1057 nr_frags = skb_shinfo(skb)->nr_frags;
1059 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1061 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1066 last_idx = free_idx = dev->tx_free_idx;
1067 tx_done_idx = dev->tx_done_idx;
1068 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1069 nr_free -= 1;
1071 dprintk("stop_queue - not enough(%p)\n", ndev);
1075 if (dev->tx_done_idx != tx_done_idx) {
1083 if (free_idx == dev->tx_intr_idx) {
1085 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1088 nr_free -= nr_frags;
1090 dprintk("stop_queue - last entry(%p)\n", ndev);
1095 frag = skb_shinfo(skb)->frags;
1099 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1101 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1103 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1118 len = skb->len;
1120 len -= skb->data_len;
1121 buf = dma_map_single(&dev->pci_dev->dev, skb->data, len,
1124 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1127 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1133 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1145 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
1148 (long long)buf, (long) page_to_pfn(frag->page),
1149 frag->page_offset);
1152 nr_frags--;
1156 spin_lock_irq(&dev->tx_lock);
1157 dev->tx_skbs[last_idx] = skb;
1159 dev->tx_free_idx = free_idx;
1160 atomic_inc(&dev->nr_tx_skbs);
1161 spin_unlock_irq(&dev->tx_lock);
1166 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1174 struct net_device *ndev = dev->ndev;
1175 u8 __iomem *base = dev->base;
1178 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1179 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1180 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1181 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1182 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1183 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1184 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1185 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1186 /*ndev->stats.rx_pause_count += */ readl(base + 0x80);
1187 /*ndev->stats.tx_pause_count += */ readl(base + 0x84);
1188 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1196 spin_lock_irq(&dev->misc_lock);
1198 spin_unlock_irq(&dev->misc_lock);
1200 return &ndev->stats;
1214 * cmd->advertising =
1216 * cmd->duplex =
1217 * cmd->port = 0;
1218 * cmd->phy_address =
1219 * cmd->transceiver = 0;
1220 * cmd->autoneg =
1221 * cmd->maxtxpkt = 0;
1222 * cmd->maxrxpkt = 0;
1226 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1227 readl(dev->base + TANAR);
1228 tbicr = readl(dev->base + TBICR);
1234 if (dev->CFG_cache & CFG_TBI_EN) {
1239 cmd->base.port = PORT_FIBRE;
1247 cmd->base.port = PORT_MII;
1250 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1253 cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1256 cmd->base.speed = SPEED_1000;
1259 cmd->base.speed = SPEED_100;
1262 cmd->base.speed = SPEED_10;
1265 cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1280 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1281 tanar = readl(dev->base + TANAR);
1283 if (dev->CFG_cache & CFG_TBI_EN) {
1293 spin_lock_irq(&dev->misc_lock);
1294 spin_lock(&dev->tx_lock);
1297 if (cmd->base.duplex != fullduplex) {
1300 if (cmd->base.duplex == DUPLEX_FULL) {
1302 writel(readl(dev->base + TXCFG)
1304 dev->base + TXCFG);
1305 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1306 dev->base + RXCFG);
1308 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1309 dev->base + GPIOR);
1319 ndev->name);
1324 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1327 dev->base + TBICR);
1328 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1329 dev->linkstate = LINK_AUTONEGOTIATE;
1332 ndev->name);
1335 writel(0x00000000, dev->base + TBICR);
1338 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1339 cmd->base.autoneg ? "ENABLED" : "DISABLED");
1343 spin_unlock(&dev->tx_lock);
1344 spin_unlock_irq(&dev->misc_lock);
1348 /* end ethtool get/set support -df */
1353 strscpy(info->driver, "ns83820", sizeof(info->driver));
1354 strscpy(info->version, VERSION, sizeof(info->version));
1355 strscpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
1361 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1374 writel(0, dev->base + IMR);
1375 writel(0, dev->base + IER);
1376 readl(dev->base + IER);
1383 spin_lock_irqsave(&dev->misc_lock, flags);
1385 spin_unlock_irqrestore(&dev->misc_lock, flags);
1396 dev->ihr = 0;
1398 isr = readl(dev->base + ISR);
1415 dev->rx_info.idle = 1;
1421 prefetch(dev->rx_info.next_rx_desc);
1423 spin_lock_irqsave(&dev->misc_lock, flags);
1424 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1425 writel(dev->IMR_cache, dev->base + IMR);
1426 spin_unlock_irqrestore(&dev->misc_lock, flags);
1428 tasklet_schedule(&dev->rx_tasklet);
1430 //writel(4, dev->base + IHR);
1438 ndev->stats.rx_fifo_errors++;
1443 ndev->stats.rx_fifo_errors++;
1446 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1447 writel(CR_RXE, dev->base + CR);
1451 txdp = readl(dev->base + TXDP);
1453 txdp -= dev->tx_phy_descs;
1454 dev->tx_idx = txdp / (DESC_SIZE * 4);
1455 if (dev->tx_idx >= NR_TX_DESC) {
1456 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1457 dev->tx_idx = 0;
1464 if (dev->tx_idx != dev->tx_free_idx)
1472 spin_lock_irqsave(&dev->tx_lock, flags);
1474 spin_unlock_irqrestore(&dev->tx_lock, flags);
1478 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1479 (dev->IMR_cache & ISR_TXOK)) {
1480 spin_lock_irqsave(&dev->misc_lock, flags);
1481 dev->IMR_cache &= ~ISR_TXOK;
1482 writel(dev->IMR_cache, dev->base + IMR);
1483 spin_unlock_irqrestore(&dev->misc_lock, flags);
1493 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1494 spin_lock_irqsave(&dev->misc_lock, flags);
1495 dev->IMR_cache |= ISR_TXOK;
1496 writel(dev->IMR_cache, dev->base + IMR);
1497 spin_unlock_irqrestore(&dev->misc_lock, flags);
1509 if (dev->ihr)
1510 writel(dev->ihr, dev->base + IHR);
1517 writel(which, dev->base + CR);
1520 } while (readl(dev->base + CR) & which);
1529 timer_delete_sync(&dev->tx_watchdog);
1533 dev->rx_info.up = 0;
1534 synchronize_irq(dev->pci_dev->irq);
1538 synchronize_irq(dev->pci_dev->irq);
1540 spin_lock_irq(&dev->misc_lock);
1541 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1542 spin_unlock_irq(&dev->misc_lock);
1557 spin_lock_irqsave(&dev->tx_lock, flags);
1559 tx_done_idx = dev->tx_done_idx;
1560 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1563 ndev->name,
1564 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1569 isr = readl(dev->base + ISR);
1570 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1577 tx_done_idx = dev->tx_done_idx;
1578 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1581 ndev->name,
1582 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1584 spin_unlock_irqrestore(&dev->tx_lock, flags);
1590 struct net_device *ndev = dev->ndev;
1594 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1599 dev->tx_done_idx != dev->tx_free_idx) {
1601 ndev->name,
1602 dev->tx_done_idx, dev->tx_free_idx,
1603 atomic_read(&dev->nr_tx_skbs));
1607 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1619 writel(0, dev->base + PQCR);
1625 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1627 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1629 dev->tx_phy_descs
1633 dev->tx_idx = 0;
1634 dev->tx_done_idx = 0;
1635 desc = dev->tx_phy_descs;
1636 writel(0, dev->base + TXDP_HI);
1637 writel(desc, dev->base + TXDP);
1639 timer_setup(&dev->tx_watchdog, ns83820_tx_watch, 0);
1640 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1662 writel(i*2, dev->base + RFCR);
1663 data = readl(dev->base + RFDR);
1674 u8 __iomem *rfcr = dev->base + RFCR;
1679 if (ndev->flags & IFF_PROMISC)
1684 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
1689 spin_lock_irq(&dev->misc_lock);
1694 spin_unlock_irq(&dev->misc_lock);
1705 dprintk("%s: start %s\n", ndev->name, name);
1709 writel(enable, dev->base + PTSCR);
1712 status = readl(dev->base + PTSCR);
1728 ndev->name, name, status, fail);
1731 ndev->name, name, status);
1733 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1737 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit) argument
1740 dev->MEAR_cache &= ~MEAR_MDC;
1741 writel(dev->MEAR_cache, dev->base + MEAR);
1742 readl(dev->base + MEAR);
1744 /* enable output, set bit */
1745 dev->MEAR_cache |= MEAR_MDDIR;
1746 if (bit)
1747 dev->MEAR_cache |= MEAR_MDIO;
1749 dev->MEAR_cache &= ~MEAR_MDIO;
1751 /* set the output bit */
1752 writel(dev->MEAR_cache, dev->base + MEAR);
1753 readl(dev->base + MEAR);
1758 /* drive MDC high causing the data bit to be latched */
1759 dev->MEAR_cache |= MEAR_MDC;
1760 writel(dev->MEAR_cache, dev->base + MEAR);
1761 readl(dev->base + MEAR);
1769 int bit; local
1772 dev->MEAR_cache &= ~MEAR_MDC;
1773 dev->MEAR_cache &= ~MEAR_MDDIR;
1774 writel(dev->MEAR_cache, dev->base + MEAR);
1775 readl(dev->base + MEAR);
1780 /* drive MDC high causing the data bit to be latched */
1781 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1782 dev->MEAR_cache |= MEAR_MDC;
1783 writel(dev->MEAR_cache, dev->base + MEAR);
1788 return bit;
1851 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1864 ndev->name, j,
1906 !dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64))) {
1908 } else if (!dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
1911 dev_warn(&pci_dev->dev, "dma_set_mask failed!\n");
1912 return -ENODEV;
1916 err = -ENOMEM;
1921 dev->ndev = ndev;
1923 spin_lock_init(&dev->rx_info.lock);
1924 spin_lock_init(&dev->tx_lock);
1925 spin_lock_init(&dev->misc_lock);
1926 dev->pci_dev = pci_dev;
1928 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1930 INIT_WORK(&dev->tq_refill, queue_refill);
1931 tasklet_setup(&dev->rx_tasklet, rx_action);
1935 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1941 dev->base = ioremap(addr, PAGE_SIZE);
1942 dev->tx_descs = dma_alloc_coherent(&pci_dev->dev,
1944 &dev->tx_phy_descs, GFP_KERNEL);
1945 dev->rx_info.descs = dma_alloc_coherent(&pci_dev->dev,
1947 &dev->rx_info.phy_descs, GFP_KERNEL);
1948 err = -ENOMEM;
1949 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1953 dev->tx_descs, (long)dev->tx_phy_descs,
1954 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1958 dev->IMR_cache = 0;
1960 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1963 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1964 pci_dev->irq, err);
1970 * because some of the setup code uses dev->name. It's Wrong(tm) -
1971 * we should be using driver-specific names for all that stuff.
1976 err = dev_alloc_name(ndev, ndev->name);
1978 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1983 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1984 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1986 ndev->netdev_ops = &netdev_ops;
1987 ndev->ethtool_ops = &ops;
1988 ndev->watchdog_timeo = 5 * HZ;
1994 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2002 dev->CFG_cache = readl(dev->base + CFG);
2004 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2005 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2006 ndev->name);
2007 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2008 if (!(dev->CFG_cache & CFG_DATA64_EN))
2009 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2010 ndev->name);
2012 dev->CFG_cache &= ~(CFG_DATA64_EN);
2014 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2017 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2019 dev->CFG_cache |= CFG_REQALG;
2020 dev->CFG_cache |= CFG_POW;
2021 dev->CFG_cache |= CFG_TMRTEST;
2023 /* When compiled with 64 bit addressing, we must always enable
2024 * the 64 bit descriptor format.
2027 dev->CFG_cache |= CFG_M64ADDR;
2029 dev->CFG_cache |= CFG_T64ADDR;
2032 dev->CFG_cache &= ~CFG_BEM;
2035 if (dev->CFG_cache & CFG_TBI_EN) {
2037 ndev->name);
2038 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2041 writel(readl(dev->base + TANAR)
2043 dev->base + TANAR);
2047 dev->base + TBICR);
2048 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2049 dev->linkstate = LINK_AUTONEGOTIATE;
2051 dev->CFG_cache |= CFG_MODE_1000;
2054 writel(dev->CFG_cache, dev->base + CFG);
2055 dprintk("CFG: %08x\n", dev->CFG_cache);
2058 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2059 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2061 writel(dev->CFG_cache, dev->base + CFG);
2067 if (readl(dev->base + SRR))
2068 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2073 * can be transmitted is 8192 - FLTH - burst size.
2076 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2080 dev->base + TXCFG);
2083 writel(0x000, dev->base + IHR);
2084 writel(0x100, dev->base + IHR);
2085 writel(0x000, dev->base + IHR);
2090 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2096 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2099 writel(0, dev->base + PQCR);
2119 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2121 /* Enable per-packet TCP/UDP/IP checksumming
2130 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2133 /* writel(0, dev->base + PCR); */
2136 dev->base + PCR);
2139 writel(0, dev->base + WCSR);
2144 ndev->features |= NETIF_F_SG;
2145 ndev->features |= NETIF_F_IP_CSUM;
2147 ndev->min_mtu = 0;
2151 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2155 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2156 ndev->name);
2157 ndev->features |= NETIF_F_HIGHDMA;
2161 ndev->name,
2162 (unsigned)readl(dev->base + SRR) >> 8,
2163 (unsigned)readl(dev->base + SRR) & 0xff,
2164 ndev->dev_addr, addr, pci_dev->irq,
2165 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2185 free_irq(pci_dev->irq, ndev);
2187 if (dev->base)
2188 iounmap(dev->base);
2189 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2190 dev->tx_descs, dev->tx_phy_descs);
2191 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2192 dev->rx_info.descs, dev->rx_info.phy_descs);
2211 free_irq(dev->pci_dev->irq, ndev);
2212 iounmap(dev->base);
2213 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2214 dev->tx_descs, dev->tx_phy_descs);
2215 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2216 dev->rx_info.descs, dev->rx_info.phy_descs);
2217 pci_disable_device(dev->pci_dev);
2256 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2259 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");