Lines Matching +full:0 +full:x11200000
53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
63 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */
64 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */
65 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */
66 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */
67 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */
68 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */
69 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */
70 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */
71 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */
72 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */
73 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */
74 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */
75 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */
76 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */
77 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */
78 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */
79 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */
80 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */
81 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */
82 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */
83 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */
84 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */
85 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */
86 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */
87 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */
88 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */
89 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */
90 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */
91 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */
92 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */
93 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */
94 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */
95 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */
96 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */
97 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */
98 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */
99 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */
100 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */
101 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */
102 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */
103 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */
104 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */
105 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */
106 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */
107 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */
108 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */
109 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */
110 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */
111 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */
112 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */
113 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */
114 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */
115 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */
116 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */
117 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */
118 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */
119 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */
120 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */
121 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */
122 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */
123 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */
124 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */
125 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */
126 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */
127 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */
128 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */
129 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */
130 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */
131 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */
132 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */
133 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */
134 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */
135 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */
136 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */
137 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */
138 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */
139 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */
140 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */
141 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */
142 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */
143 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */
144 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */
145 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */
146 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */
147 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */
148 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */
149 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */
150 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */
151 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */
152 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */
153 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */
154 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */
155 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */
156 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */
157 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */
158 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */
159 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */
160 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */
161 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */
162 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */
163 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */
164 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */
165 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */
166 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */
167 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */
168 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */
169 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */
170 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */
171 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */
172 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */
173 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */
174 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */
175 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */
176 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */
177 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */
178 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */
179 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */
180 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */
181 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */
182 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */
183 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */
184 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */
185 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */
186 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */
187 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */
188 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */
189 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */
190 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */
191 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */
192 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */
193 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */
194 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */
195 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */
196 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */
197 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */
198 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */
199 { TARGET_VCAP_ES2, 0x110d0000, 2 }, /* 0x6110d0000 */
200 { TARGET_VCAP_ES0, 0x110e0000, 2 }, /* 0x6110e0000 */
201 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */
202 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */
203 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */
204 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */
205 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */
206 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */
207 { TARGET_ANA_AC_SDLB, 0x11500000, 2 }, /* 0x611500000 */
208 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */
209 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */
210 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */
211 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */
212 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */
279 for (idx = 0, jdx = 0; jdx < iomap_size; jdx++) { in sparx5_create_targets()
287 for (idx = 0; idx < ioranges; idx++) { in sparx5_create_targets()
304 for (jdx = 0; jdx < iomap_size; jdx++) { in sparx5_create_targets()
309 return 0; in sparx5_create_targets()
335 spx5_port->custom_etype = 0x8880; /* Vitesse */ in sparx5_create_port()
393 return 0; in sparx5_create_port()
413 for (jdx = 0; jdx < 10; jdx++) { in sparx5_init_ram()
415 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) { in sparx5_init_ram()
417 if (jdx == 0) { in sparx5_init_ram()
430 if (pending > 0) { in sparx5_init_ram()
437 return 0; in sparx5_init_ram()
443 int err = 0; in sparx5_init_switchcore()
450 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), in sparx5_init_switchcore()
470 return 0; in sparx5_init_switchcore()
487 freq = 0; /* Not supported */ in sparx5_init_coreclock()
495 freq = 0; /* Not supported */ in sparx5_init_coreclock()
502 freq = 0; /* Not supported */ in sparx5_init_coreclock()
514 freq = 0; /* Not supported */ in sparx5_init_coreclock()
559 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | in sparx5_init_coreclock()
560 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | in sparx5_init_coreclock()
561 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | in sparx5_init_coreclock()
562 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | in sparx5_init_coreclock()
600 for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++) in sparx5_init_coreclock()
617 return 0; in sparx5_init_coreclock()
631 for (res = 0; res < 2; res++) { in sparx5_qlim_set()
632 for (prio = 0; prio < 8; prio++) in sparx5_qlim_set()
633 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
638 for (dp = 0; dp < 4; dp++) in sparx5_qlim_set()
639 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
646 spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); in sparx5_qlim_set()
647 spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); in sparx5_qlim_set()
648 spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); in sparx5_qlim_set()
649 spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); in sparx5_qlim_set()
651 return 0; in sparx5_qlim_set()
671 for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) in sparx5_board_init()
673 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) in sparx5_board_init()
681 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; in sparx5_start()
689 for (idx = 0; idx < consts->n_own_upsids; idx++) { in sparx5_start()
781 if (sparx5->fdma_irq >= 0 && is_sparx5(sparx5)) { in sparx5_start()
782 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) in sparx5_start()
786 0, in sparx5_start()
795 if (err && sparx5->xtr_irq >= 0) { in sparx5_start()
807 if (sparx5->ptp_irq >= 0 && in sparx5_start()
835 int idx = 0, err = 0; in mchp_sparx5_probe()
910 conf->sd_sgpio = ~0; in mchp_sparx5_probe()
939 sparx5->base_mac[5] = 0; in mchp_sparx5_probe()
969 for (idx = 0; idx < sparx5->port_count; ++idx) { in mchp_sparx5_probe()