Lines Matching +full:36 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200.
22 TARGET_ORG = 36,
46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16)
61 #define ANA_ADVLEARN_VLAN_CHK BIT(0)
73 #define ANA_ANAINTR_INTR BIT(1)
79 #define ANA_ANAINTR_INTR_ENA BIT(0)
172 #define ANA_PGID_CFG_OBEY_VLAN BIT(0)
187 #define ANA_MACACCESS_CHANGE2SW BIT(17)
193 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16)
199 #define ANA_MACACCESS_VALID BIT(12)
259 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18)
274 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
292 #define ANA_VLAN_CFG_VLAN_DEI BIT(12)
307 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
313 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
319 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
325 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
334 #define ANA_QOS_CFG_DP_DEFAULT_VAL BIT(8)
346 #define ANA_QOS_CFG_QOS_DSCP_ENA BIT(4)
352 #define ANA_QOS_CFG_QOS_PCP_ENA BIT(3)
367 #define ANA_VCAP_CFG_S1_ENA BIT(14)
421 #define ANA_VCAP_S2_CFG_ENA BIT(14)
466 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL BIT(3)
481 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6)
487 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5)
493 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4)
499 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3)
511 #define ANA_PORT_CFG_SRC_MIRROR_ENA BIT(13)
517 #define ANA_PORT_CFG_LEARNAUTO BIT(6)
523 #define ANA_PORT_CFG_LEARN_ENA BIT(5)
529 #define ANA_PORT_CFG_RECV_ENA BIT(4)
553 #define ANA_POL_CFG_PORT_POL_ENA BIT(17)
577 #define ANA_AGGR_CFG_AC_RND_ENA BIT(6)
583 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(5)
589 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(4)
595 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(3)
601 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(2)
607 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(1)
613 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(0)
622 #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
634 #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
640 #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
664 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA BIT(11)
670 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA BIT(10)
688 #define ANA_POL_MODE_OVERSHOOT_ENA BIT(0)
706 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0)
715 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
721 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
727 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
733 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
739 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
754 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
760 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
769 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
787 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA BIT(1)
793 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
829 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
839 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4)
844 #define DEV_PCS1G_CFG_PCS_ENA BIT(0)
853 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
859 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1)
868 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0)
883 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
889 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1)
895 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0)
910 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
919 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
925 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
934 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
988 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(4)
994 #define FDMA_CH_CFG_CH_INJ_PORT BIT(3)
1006 #define FDMA_CH_CFG_CH_MEM BIT(0)
1015 #define FDMA_PORT_CTRL_INJ_STOP BIT(4)
1021 #define FDMA_PORT_CTRL_XTR_STOP BIT(2)
1148 #define PTP_TWOSTEP_CTRL_NXT BIT(11)
1154 #define PTP_TWOSTEP_CTRL_VLD BIT(10)
1160 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9)
1172 #define PTP_TWOSTEP_CTRL_OVFL BIT(0)
1188 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
1196 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
1203 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
1206 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
1209 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
1212 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
1220 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
1227 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
1230 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
1238 #define QS_INJ_CTRL_EOF BIT(19)
1244 #define QS_INJ_CTRL_SOF BIT(18)
1257 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
1274 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
1283 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18)
1295 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12)
1352 #define QSYS_SE_CFG_SE_RR_ENA BIT(5)
1358 #define QSYS_SE_CFG_SE_AVB_ENA BIT(4)
1393 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q BIT(17)
1481 #define QSYS_TAS_LST __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4)
1582 #define REW_PORT_CFG_ES0_EN BIT(4)
1588 #define REW_PORT_CFG_NO_REWRITE BIT(0)
1606 #define REW_PCP_DEI_CFG_DEI_QOS_VAL BIT(3)
1630 #define SYS_RESET_CFG_CORE_ENA BIT(0)
1654 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1)
1663 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20)
1693 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
1720 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18)
1726 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17)
1732 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16)
1750 #define SYS_RAM_INIT_RAM_INIT BIT(1)
1765 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
1771 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
1777 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
1789 #define VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2)
1795 #define VCAP_UPDATE_CTRL_CLEAR_CACHE BIT(1)
1801 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
1886 #define VCAP_IF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 36, 0, 1, 4)