Lines Matching +full:0 +full:x120000
17 #define XTR_EOF_0 0x00000080U
18 #define XTR_EOF_1 0x01000080U
19 #define XTR_EOF_2 0x02000080U
20 #define XTR_EOF_3 0x03000080U
21 #define XTR_PRUNED 0x04000080U
22 #define XTR_ABORT 0x05000080U
23 #define XTR_ESCAPE 0x06000080U
24 #define XTR_NOT_READY 0x07000080U
42 { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */
43 { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */
44 { TARGET_ORG, 0, 1 }, /* 0xe2000000 */
45 { TARGET_GCB, 0x4000, 1 }, /* 0xe2004000 */
46 { TARGET_QS, 0x8000, 1 }, /* 0xe2008000 */
47 { TARGET_PTP, 0xc000, 1 }, /* 0xe200c000 */
48 { TARGET_CHIP_TOP, 0x10000, 1 }, /* 0xe2010000 */
49 { TARGET_REW, 0x14000, 1 }, /* 0xe2014000 */
50 { TARGET_VCAP, 0x18000, 1 }, /* 0xe2018000 */
51 { TARGET_VCAP + 1, 0x20000, 1 }, /* 0xe2020000 */
52 { TARGET_VCAP + 2, 0x24000, 1 }, /* 0xe2024000 */
53 { TARGET_SYS, 0x28000, 1 }, /* 0xe2028000 */
54 { TARGET_DEV, 0x34000, 1 }, /* 0xe2034000 */
55 { TARGET_DEV + 1, 0x38000, 1 }, /* 0xe2038000 */
56 { TARGET_DEV + 2, 0x3c000, 1 }, /* 0xe203c000 */
57 { TARGET_DEV + 3, 0x40000, 1 }, /* 0xe2040000 */
58 { TARGET_DEV + 4, 0x44000, 1 }, /* 0xe2044000 */
59 { TARGET_DEV + 5, 0x48000, 1 }, /* 0xe2048000 */
60 { TARGET_DEV + 6, 0x4c000, 1 }, /* 0xe204c000 */
61 { TARGET_DEV + 7, 0x50000, 1 }, /* 0xe2050000 */
62 { TARGET_QSYS, 0x100000, 1 }, /* 0xe2100000 */
63 { TARGET_AFI, 0x120000, 1 }, /* 0xe2120000 */
64 { TARGET_ANA, 0x140000, 1 }, /* 0xe2140000 */
79 for (idx = 0; idx < IO_RANGES; idx++) { in lan966x_create_targets()
97 for (idx = 0; idx < ARRAY_SIZE(lan966x_main_iomap); idx++) { in lan966x_create_targets()
104 return 0; in lan966x_create_targets()
113 for (p = 0; p < lan966x->num_phys_ports; ++p) { in lan966x_port_unique_address()
133 return 0; in lan966x_port_set_mac_address()
166 return 0; in lan966x_port_get_phys_port_name()
186 err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0); in lan966x_port_open()
194 return 0; in lan966x_port_open()
205 return 0; in lan966x_port_stop()
218 return 0; in lan966x_port_inj_ready()
232 u8 grp = 0; in lan966x_port_ifh_xmit()
247 for (i = 0; i < IFH_LEN; ++i) { in lan966x_port_ifh_xmit()
259 for (i = 0; i < count; ++i) { in lan966x_port_ifh_xmit()
275 lan_wr(0, lan966x, QS_INJ_WR(grp)); in lan966x_port_ifh_xmit()
282 0 : last) | in lan966x_port_ifh_xmit()
287 lan_wr(0, lan966x, QS_INJ_WR(grp)); in lan966x_port_ifh_xmit()
310 int i = 0; in lan966x_ifh_set()
314 u8 v = val >> i & 0xff; in lan966x_ifh_set()
374 memset(ifh, 0x0, sizeof(__be32) * IFH_LEN); in lan966x_port_xmit()
378 lan966x_ifh_set_qos_class(ifh, skb->priority >= 7 ? 0x7 : skb->priority); in lan966x_port_xmit()
379 lan966x_ifh_set_ipv(ifh, skb->priority >= 7 ? 0x7 : skb->priority); in lan966x_port_xmit()
414 return 0; in lan966x_port_change_mtu()
456 return 0; in lan966x_port_get_parent_id()
469 return 0; in lan966x_port_hwtstamp_get()
498 return 0; in lan966x_port_hwtstamp_set()
613 u64 val = 0; in lan966x_ifh_get()
616 for (int i = 0; i < length ; i++) { in lan966x_ifh_get()
620 if (i == 0 || k == 0) in lan966x_ifh_get()
648 int i, grp = 0, err = 0; in lan966x_xtr_irq_handler()
657 int sz = 0, buf_len; in lan966x_xtr_irq_handler()
662 for (i = 0; i < IFH_LEN; i++) { in lan966x_xtr_irq_handler()
668 err = 0; in lan966x_xtr_irq_handler()
685 len = 0; in lan966x_xtr_irq_handler()
688 if (sz < 0) { in lan966x_xtr_irq_handler()
699 if (sz < 0) { in lan966x_xtr_irq_handler()
720 skb->offload_fwd_mark = 0; in lan966x_xtr_irq_handler()
730 if (sz < 0 || err) in lan966x_xtr_irq_handler()
750 for (p = 0; p < lan966x->num_phys_ports; p++) { in lan966x_cleanup_ports()
777 if (lan966x->ana_irq > 0) { in lan966x_cleanup_ports()
785 if (lan966x->ptp_irq > 0) in lan966x_cleanup_ports()
788 if (lan966x->ptp_ext_irq > 0) in lan966x_cleanup_ports()
879 lan966x_vlan_port_set_vlan_aware(port, 0); in lan966x_probe_port()
884 return 0; in lan966x_probe_port()
898 GENMASK(1, 0), in lan966x_init()
906 ~(GENMASK(1, 0)), in lan966x_init()
926 lan_wr(0, lan966x, QSYS_CPU_GROUP_MAP); in lan966x_init()
933 lan966x, QS_XTR_GRP_CFG(0)); in lan966x_init()
938 lan966x, QS_INJ_GRP_CFG(0)); in lan966x_init()
940 lan_rmw(QS_INJ_CTRL_GAP_SIZE_SET(0), in lan966x_init()
942 lan966x, QS_INJ_CTRL(0)); in lan966x_init()
957 for (i = 0; i < 8; ++i) in lan966x_init()
966 for (i = 0; i < PGID_ENTRIES; ++i) in lan966x_init()
972 for (p = 0; p < lan966x->num_phys_ports; p++) { in lan966x_init()
974 lan_rmw(ANA_PGID_PGID_SET(0x0), in lan966x_init()
981 lan_wr(0xffff, lan966x, ANA_CPU_FWD_BPDU_CFG(p)); in lan966x_init()
985 for (i = 0; i <= QSYS_Q_RSRV; ++i) { in lan966x_init()
997 lan_rmw(ANA_PGID_PGID_SET(0), in lan966x_init()
1005 lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0), in lan966x_init()
1010 lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0), in lan966x_init()
1014 lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0), in lan966x_init()
1019 lan_rmw(GENMASK(lan966x->num_phys_ports - 1, 0), in lan966x_init()
1024 lan_rmw(ANA_PGID_PGID_SET(BIT(CPU_PORT) | GENMASK(lan966x->num_phys_ports - 1, 0)), in lan966x_init()
1048 int val = 0; in lan966x_reset_switch()
1067 return 0; in lan966x_reset_switch()
1069 lan_wr(SYS_RESET_CFG_CORE_ENA_SET(0), lan966x, SYS_RESET_CFG); in lan966x_reset_switch()
1072 val, (val & BIT(1)) == 0, READL_SLEEP_US, in lan966x_reset_switch()
1079 return 0; in lan966x_reset_switch()
1101 lan966x->base_mac[5] &= 0xf0; in lan966x_probe()
1125 if (lan966x->xtr_irq < 0) in lan966x_probe()
1137 if (lan966x->ana_irq > 0) { in lan966x_probe()
1146 if (lan966x->ptp_irq > 0) { in lan966x_probe()
1157 if (lan966x->fdma_irq > 0) { in lan966x_probe()
1159 lan966x_fdma_irq_handler, 0, in lan966x_probe()
1169 if (lan966x->ptp_ext_irq > 0) { in lan966x_probe()
1245 return 0; in lan966x_probe()
1311 return 0; in lan966x_switch_driver_init()