Lines Matching +full:channel +full:- +full:4
1 /* SPDX-License-Identifier: GPL-2.0+ */
41 #define STRAP_READ_SGMII_2_5G_ BIT(4)
54 #define HW_CFG_EE_OTP_RELOAD_ BIT(4)
67 #define PMT_CTL_ETH_PHY_RST_ BIT(4)
107 #define GEN_SYS_LOAD_STARTED_REG_ETH_ BIT(4)
111 #define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4)
152 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
153 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
154 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
157 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
158 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
159 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
207 #define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4)
238 #define MAC_WUCSR_BCAST_FR_ BIT(4)
263 #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index)))
283 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
287 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
322 #define MAC_WUCSR2_IPV4_TCPSYN_RCD_ BIT(4)
341 #define MISC_CTL_0_RFE_READ_FIFO_MASK_ GENMASK(6, 4)
356 #define VR_MII_DIG_CTRL1_DTXLANED_0_ BIT(4)
363 #define VR_MII_AN_CTRL_SGMII_LINK_STS_ BIT(4)
372 #define VR_MII_AN_INTR_STS_LINK_UP_ BIT(4)
382 #define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2)
386 #define VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_ BIT(4)
404 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) argument
406 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) argument
427 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ argument
428 (((u32)(vector)) << ((channel) << 2))
431 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ argument
432 (((u32)(vector)) << ((channel) << 2))
457 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
463 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ argument
464 (0x7 << (1 + ((channel) << 2)))
469 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4)
472 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ argument
473 (((value) & 0x7) << (1 + ((channel) << 2)))
474 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) argument
477 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ argument
478 (0xf << (4 + ((channel) << 2)))
483 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4)
495 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ argument
496 (((value) & 0xf) << (4 + ((channel) << 2)))
497 #define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2))) argument
498 #define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2)) argument
503 #define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel)) argument
506 #define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel)) argument
515 #define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel)) argument
516 #define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel)) argument
517 #define PTP_INT_EN_TIMER_SET_(channel) BIT(channel) argument
519 #define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel)) argument
520 #define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel)) argument
534 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) argument
535 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) argument
536 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) argument
537 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) argument
553 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
585 #define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel)) argument
586 #define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel)) argument
587 #define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel)) argument
588 #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel)) argument
594 #define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel)) argument
595 #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel)) argument
597 #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel)) argument
632 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
663 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) argument
664 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) argument
665 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) argument
666 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) argument
667 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) argument
668 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) argument
673 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) argument
674 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) argument
676 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) argument
689 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) argument
700 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) argument
702 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) argument
704 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) argument
706 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) argument
708 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) argument
710 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) argument
714 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) argument
716 #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4)
720 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) argument
734 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) argument
738 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) argument
740 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) argument
742 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) argument
744 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) argument
746 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) argument
748 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) argument
753 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) argument
756 #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4)
855 #define LAN743X_MAX_RX_CHANNELS (4)
857 #define PCI11X1X_MAX_TX_CHANNELS (4)
860 #define LAN743X_USED_RX_CHANNELS (4)
862 #define PCI11X1X_USED_TX_CHANNELS (4)
906 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4)
1091 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) argument