Lines Matching +full:8 +full:- +full:channel
1 /* SPDX-License-Identifier: GPL-2.0+ */
33 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
65 #define PMT_CTL_RES_CLR_WKP_MASK_ GENMASK(9, 8)
132 #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)
152 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
153 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
154 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
157 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
158 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
159 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
164 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
254 #define MAC_WK_SRC_WU_FR_WK_ BIT(8)
283 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
284 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
287 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
288 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
295 #define RFE_CTL_AU_ BIT(8)
308 #define RFE_RSS_CFG_IPV4_ BIT(8)
337 #define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8)
355 #define VR_MII_DIG_CTRL1_INIT_ BIT(8)
362 #define VR_MII_AN_CTRL_MII_CTRL_ BIT(8)
404 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) argument
406 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) argument
427 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ argument
428 (((u32)(vector)) << ((channel) << 2))
431 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ argument
432 (((u32)(vector)) << ((channel) << 2))
463 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ argument
464 (0x7 << (1 + ((channel) << 2)))
472 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ argument
473 (((value) & 0x7) << (1 + ((channel) << 2)))
474 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) argument
477 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ argument
478 (0xf << (4 + ((channel) << 2)))
487 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8)
495 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ argument
496 (((value) & 0xf) << (4 + ((channel) << 2)))
497 #define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2))) argument
498 #define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2)) argument
503 #define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel)) argument
506 #define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel)) argument
511 #define PTP_INT_RX_TS_INT_ BIT(8)
515 #define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel)) argument
516 #define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel)) argument
517 #define PTP_INT_EN_TIMER_SET_(channel) BIT(channel) argument
519 #define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel)) argument
520 #define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel)) argument
534 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) argument
535 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) argument
536 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) argument
537 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) argument
543 #define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8)
546 #define PTP_IO_SEL_MASK_ GENMASK(10, 8)
547 #define PTP_IO_SEL_SHIFT_ (8)
585 #define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel)) argument
586 #define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel)) argument
587 #define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel)) argument
588 #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel)) argument
594 #define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel)) argument
595 #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel)) argument
597 #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel)) argument
648 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
656 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
663 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) argument
664 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) argument
665 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) argument
666 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) argument
667 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) argument
668 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) argument
673 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) argument
674 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) argument
676 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) argument
686 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
689 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) argument
700 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) argument
702 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) argument
704 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) argument
706 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) argument
708 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) argument
710 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) argument
714 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) argument
720 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) argument
728 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
734 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) argument
738 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) argument
740 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) argument
742 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) argument
744 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) argument
746 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) argument
748 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) argument
753 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) argument
890 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8)
910 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8)
929 #define LAN743X_MAX_VECTOR_COUNT (8)
1091 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) argument
1094 #define INTR_FLAG_MSI_ENABLED BIT(8)