Lines Matching defs:data
131 u32 data)
133 iowrite32(data, &adapter->csr.csr_address[offset]);
140 u32 data;
142 data = lan743x_csr_read(adapter, HW_CFG);
143 data |= HW_CFG_LRST_;
144 lan743x_csr_write(adapter, HW_CFG, data);
146 return readx_poll_timeout(LAN743X_CSR_READ_OP, HW_CFG, data,
147 !(data & HW_CFG_LRST_), 100000, 10000000);
155 u32 data;
157 return readx_poll_timeout_atomic(LAN743X_CSR_READ_OP, offset, data,
158 target_value == !!(data & bit_mask),
167 u32 data;
169 return readx_poll_timeout(LAN743X_CSR_READ_OP, offset, data,
170 target_value == !!(data & bit_mask),
795 u32 data;
797 return readx_poll_timeout(LAN743X_CSR_READ_OP, MAC_MII_ACC, data,
798 !(data & MAC_MII_ACC_MII_BUSY_), 0, 1000000);
930 u32 data;
933 ret = readx_poll_timeout(LAN743X_CSR_READ_OP, SGMII_ACC, data,
934 !(data & SGMII_ACC_SGMII_BZY_), 100, 1000000);
1221 u32 data;
1226 data = lan743x_csr_read(adapter, MAC_CR);
1227 data &= ~(MAC_CR_ADD_ | MAC_CR_ASD_);
1228 data |= MAC_CR_CNTR_RST_;
1229 lan743x_csr_write(adapter, MAC_CR, data);
1335 u32 data;
1339 data = lan743x_csr_read(adapter, PMT_CTL);
1340 data |= PMT_CTL_ETH_PHY_RST_;
1341 lan743x_csr_write(adapter, PMT_CTL, data);
1343 return readx_poll_timeout(LAN743X_CSR_READ_OP, PMT_CTL, data,
1344 (!(data & PMT_CTL_ETH_PHY_RST_) &&
1345 (data & PMT_CTL_READY_)),
1352 u32 data;
1354 data = lan743x_csr_read(adapter, MAC_CR);
1361 else if ((id_rev == ID_REV_ID_LAN7431_) && (data & MAC_CR_MII_EN_))
1413 u32 data;
1441 data = ha->addr[3];
1442 data = ha->addr[2] | (data << 8);
1443 data = ha->addr[1] | (data << 8);
1444 data = ha->addr[0] | (data << 8);
1446 RFE_ADDR_FILT_LO(i), data);
1447 data = ha->addr[5];
1448 data = ha->addr[4] | (data << 8);
1449 data |= RFE_ADDR_FILT_HI_VALID_;
1451 RFE_ADDR_FILT_HI(i), data);
1470 u32 data = 0;
1477 data = DMAC_CFG_MAX_DSPACE_16_;
1480 data = DMAC_CFG_MAX_DSPACE_32_;
1483 data = DMAC_CFG_MAX_DSPACE_64_;
1486 data = DMAC_CFG_MAX_DSPACE_128_;
1492 data |= DMAC_CFG_COAL_EN_;
1493 data |= DMAC_CFG_CH_ARB_SEL_RX_HIGH_;
1494 data |= DMAC_CFG_MAX_READ_REQ_SET_(6);
1495 lan743x_csr_write(adapter, DMAC_CFG, data);
1496 data = DMAC_COAL_CFG_TIMER_LIMIT_SET_(1);
1497 data |= DMAC_COAL_CFG_TIMER_TX_START_;
1498 data |= DMAC_COAL_CFG_FLUSH_INTS_;
1499 data |= DMAC_COAL_CFG_INT_EXIT_COAL_;
1500 data |= DMAC_COAL_CFG_CSR_EXIT_COAL_;
1501 data |= DMAC_COAL_CFG_TX_THRES_SET_(0x0A);
1502 data |= DMAC_COAL_CFG_RX_THRES_SET_(0x0C);
1503 lan743x_csr_write(adapter, DMAC_COAL_CFG, data);
1504 data = DMAC_OBFF_TX_THRES_SET_(0x08);
1505 data |= DMAC_OBFF_RX_THRES_SET_(0x0A);
1506 lan743x_csr_write(adapter, DMAC_OBFF_CFG, data);
1691 u32 data;
1695 data = lan743x_csr_read(adapter, RX_CFG_B(channel_number));
1696 data &= RX_CFG_B_TS_MASK_;
1697 data |= rx_ts_config;
1699 data);
1706 u32 data;
1712 data = lan743x_csr_read(adapter, PTP_RX_TS_CFG);
1713 data |= PTP_RX_TS_CFG_EVENT_MSGS_;
1714 lan743x_csr_write(adapter, PTP_RX_TS_CFG, data);
2008 skb->data, head_length,
2206 u32 data = 0;
2241 data = lan743x_csr_read(adapter, TX_CFG_B(tx->channel_number));
2242 data &= ~TX_CFG_B_TX_RING_LEN_MASK_;
2243 data |= ((tx->ring_size) & TX_CFG_B_TX_RING_LEN_MASK_);
2245 data |= TX_CFG_B_TDMABL_512_;
2246 lan743x_csr_write(adapter, TX_CFG_B(tx->channel_number), data);
2249 data = TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ | TX_CFG_A_TX_HP_WB_EN_;
2251 data |= TX_CFG_A_TX_HP_WB_ON_INT_TMR_;
2252 data |= TX_CFG_A_TX_PF_THRES_SET_(0x10);
2253 data |= TX_CFG_A_TX_PF_PRI_THRES_SET_(0x04);
2254 data |= TX_CFG_A_TX_HP_WB_THRES_SET_(0x07);
2256 lan743x_csr_write(adapter, TX_CFG_A(tx->channel_number), data);
2281 data = 0;
2283 data |= TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_;
2285 data |= TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_;
2287 data |= TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_;
2289 data |= TX_CFG_C_TX_INT_EN_R2C_;
2290 lan743x_csr_write(adapter, TX_CFG_C(tx->channel_number), data);
2335 dma_ptr = dma_map_single(dev, skb->data, buffer_length, DMA_FROM_DEVICE);
2756 u32 data = 0;
2787 data = RX_CFG_A_RX_HP_WB_EN_;
2789 data |= (RX_CFG_A_RX_WB_ON_INT_TMR_ |
2797 RX_CFG_A(rx->channel_number), data);
2800 data = lan743x_csr_read(adapter, RX_CFG_B(rx->channel_number));
2801 data &= ~RX_CFG_B_RX_PAD_MASK_;
2803 data |= RX_CFG_B_RX_PAD_0_;
2805 data |= RX_CFG_B_RX_PAD_2_;
2806 data &= ~RX_CFG_B_RX_RING_LEN_MASK_;
2807 data |= ((rx->ring_size) & RX_CFG_B_RX_RING_LEN_MASK_);
2809 data |= RX_CFG_B_RDMABL_512_;
2811 lan743x_csr_write(adapter, RX_CFG_B(rx->channel_number), data);
2817 data = 0;
2819 data |= RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_;
2821 data |= RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_;
2823 data |= RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_;
2825 data |= RX_CFG_C_RX_INT_EN_R2C_;
2826 lan743x_csr_write(adapter, RX_CFG_C(rx->channel_number), data);
3880 u32 data;
3894 data = lan743x_csr_read(adapter, HW_CFG);
3895 adapter->hw_cfg = data;
3896 data |= (HW_CFG_RST_PROTECT_PCIE_ |
3901 lan743x_csr_write(adapter, HW_CFG, data);
3913 u32 data;
3938 data = MAC_WUCSR_EEE_TX_WAKE_ | MAC_WUCSR_EEE_RX_WAKE_ |
3941 lan743x_csr_write(adapter, MAC_WUCSR, data);
3943 data = MAC_WUCSR2_NS_RCD_ | MAC_WUCSR2_ARP_RCD_ |
3945 lan743x_csr_write(adapter, MAC_WUCSR2, data);
3947 data = MAC_WK_SRC_ETH_PHY_WK_ | MAC_WK_SRC_IPV6_TCPSYN_RCD_WK_ |
3953 lan743x_csr_write(adapter, MAC_WK_SRC, data);