Lines Matching +full:0 +full:x0542
33 #define KS_DMA_TX_CTRL 0x0000
34 #define DMA_TX_ENABLE 0x00000001
35 #define DMA_TX_CRC_ENABLE 0x00000002
36 #define DMA_TX_PAD_ENABLE 0x00000004
37 #define DMA_TX_LOOPBACK 0x00000100
38 #define DMA_TX_FLOW_ENABLE 0x00000200
39 #define DMA_TX_CSUM_IP 0x00010000
40 #define DMA_TX_CSUM_TCP 0x00020000
41 #define DMA_TX_CSUM_UDP 0x00040000
42 #define DMA_TX_BURST_SIZE 0x3F000000
44 #define KS_DMA_RX_CTRL 0x0004
45 #define DMA_RX_ENABLE 0x00000001
46 #define KS884X_DMA_RX_MULTICAST 0x00000002
47 #define DMA_RX_PROMISCUOUS 0x00000004
48 #define DMA_RX_ERROR 0x00000008
49 #define DMA_RX_UNICAST 0x00000010
50 #define DMA_RX_ALL_MULTICAST 0x00000020
51 #define DMA_RX_BROADCAST 0x00000040
52 #define DMA_RX_FLOW_ENABLE 0x00000200
53 #define DMA_RX_CSUM_IP 0x00010000
54 #define DMA_RX_CSUM_TCP 0x00020000
55 #define DMA_RX_CSUM_UDP 0x00040000
56 #define DMA_RX_BURST_SIZE 0x3F000000
61 #define KS_DMA_TX_START 0x0008
62 #define KS_DMA_RX_START 0x000C
63 #define DMA_START 0x00000001
65 #define KS_DMA_TX_ADDR 0x0010
66 #define KS_DMA_RX_ADDR 0x0014
68 #define DMA_ADDR_LIST_MASK 0xFFFFFFFC
72 #define KS884X_MULTICAST_0_OFFSET 0x0020
73 #define KS884X_MULTICAST_1_OFFSET 0x0021
74 #define KS884X_MULTICAST_2_OFFSET 0x0022
75 #define KS884x_MULTICAST_3_OFFSET 0x0023
77 #define KS884X_MULTICAST_4_OFFSET 0x0024
78 #define KS884X_MULTICAST_5_OFFSET 0x0025
79 #define KS884X_MULTICAST_6_OFFSET 0x0026
80 #define KS884X_MULTICAST_7_OFFSET 0x0027
85 #define KS884X_INTERRUPTS_ENABLE 0x0028
87 #define KS884X_INTERRUPTS_STATUS 0x002C
89 #define KS884X_INT_RX_STOPPED 0x02000000
90 #define KS884X_INT_TX_STOPPED 0x04000000
91 #define KS884X_INT_RX_OVERRUN 0x08000000
92 #define KS884X_INT_TX_EMPTY 0x10000000
93 #define KS884X_INT_RX 0x20000000
94 #define KS884X_INT_TX 0x40000000
95 #define KS884X_INT_PHY 0x80000000
106 #define KS_ADD_ADDR_0_LO 0x0080
108 #define KS_ADD_ADDR_0_HI 0x0084
110 #define KS_ADD_ADDR_1_LO 0x0088
112 #define KS_ADD_ADDR_1_HI 0x008C
114 #define KS_ADD_ADDR_2_LO 0x0090
116 #define KS_ADD_ADDR_2_HI 0x0094
118 #define KS_ADD_ADDR_3_LO 0x0098
120 #define KS_ADD_ADDR_3_HI 0x009C
122 #define KS_ADD_ADDR_4_LO 0x00A0
124 #define KS_ADD_ADDR_4_HI 0x00A4
126 #define KS_ADD_ADDR_5_LO 0x00A8
128 #define KS_ADD_ADDR_5_HI 0x00AC
130 #define KS_ADD_ADDR_6_LO 0x00B0
132 #define KS_ADD_ADDR_6_HI 0x00B4
134 #define KS_ADD_ADDR_7_LO 0x00B8
136 #define KS_ADD_ADDR_7_HI 0x00BC
138 #define KS_ADD_ADDR_8_LO 0x00C0
140 #define KS_ADD_ADDR_8_HI 0x00C4
142 #define KS_ADD_ADDR_9_LO 0x00C8
144 #define KS_ADD_ADDR_9_HI 0x00CC
146 #define KS_ADD_ADDR_A_LO 0x00D0
148 #define KS_ADD_ADDR_A_HI 0x00D4
150 #define KS_ADD_ADDR_B_LO 0x00D8
152 #define KS_ADD_ADDR_B_HI 0x00DC
154 #define KS_ADD_ADDR_C_LO 0x00E0
156 #define KS_ADD_ADDR_C_HI 0x00E4
158 #define KS_ADD_ADDR_D_LO 0x00E8
160 #define KS_ADD_ADDR_D_HI 0x00EC
162 #define KS_ADD_ADDR_E_LO 0x00F0
164 #define KS_ADD_ADDR_E_HI 0x00F4
166 #define KS_ADD_ADDR_F_LO 0x00F8
168 #define KS_ADD_ADDR_F_HI 0x00FC
170 #define ADD_ADDR_HI_MASK 0x0000FFFF
171 #define ADD_ADDR_ENABLE 0x80000000
177 #define KS884X_ADDR_0_OFFSET 0x0200
178 #define KS884X_ADDR_1_OFFSET 0x0201
180 #define KS884X_ADDR_2_OFFSET 0x0202
181 #define KS884X_ADDR_3_OFFSET 0x0203
183 #define KS884X_ADDR_4_OFFSET 0x0204
184 #define KS884X_ADDR_5_OFFSET 0x0205
187 #define KS884X_BUS_CTRL_OFFSET 0x0210
189 #define BUS_SPEED_125_MHZ 0x0000
190 #define BUS_SPEED_62_5_MHZ 0x0001
191 #define BUS_SPEED_41_66_MHZ 0x0002
192 #define BUS_SPEED_25_MHZ 0x0003
195 #define KS884X_EEPROM_CTRL_OFFSET 0x0212
197 #define EEPROM_CHIP_SELECT 0x0001
198 #define EEPROM_SERIAL_CLOCK 0x0002
199 #define EEPROM_DATA_OUT 0x0004
200 #define EEPROM_DATA_IN 0x0008
201 #define EEPROM_ACCESS_ENABLE 0x0010
204 #define KS884X_MEM_INFO_OFFSET 0x0214
206 #define RX_MEM_TEST_FAILED 0x0008
207 #define RX_MEM_TEST_FINISHED 0x0010
208 #define TX_MEM_TEST_FAILED 0x0800
209 #define TX_MEM_TEST_FINISHED 0x1000
212 #define KS884X_GLOBAL_CTRL_OFFSET 0x0216
213 #define GLOBAL_SOFTWARE_RESET 0x0001
215 #define KS8841_POWER_MANAGE_OFFSET 0x0218
218 #define KS8841_WOL_CTRL_OFFSET 0x021A
219 #define KS8841_WOL_MAGIC_ENABLE 0x0080
220 #define KS8841_WOL_FRAME3_ENABLE 0x0008
221 #define KS8841_WOL_FRAME2_ENABLE 0x0004
222 #define KS8841_WOL_FRAME1_ENABLE 0x0002
223 #define KS8841_WOL_FRAME0_ENABLE 0x0001
226 #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
227 #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
228 #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
231 #define KS884X_IACR_P 0x04A0
235 #define KS884X_IADR1_P 0x04A2
236 #define KS884X_IADR2_P 0x04A4
237 #define KS884X_IADR3_P 0x04A6
238 #define KS884X_IADR4_P 0x04A8
239 #define KS884X_IADR5_P 0x04AA
255 #define KS884X_P1MBCR_P 0x04D0
256 #define KS884X_P1MBSR_P 0x04D2
257 #define KS884X_PHY1ILR_P 0x04D4
258 #define KS884X_PHY1IHR_P 0x04D6
259 #define KS884X_P1ANAR_P 0x04D8
260 #define KS884X_P1ANLPR_P 0x04DA
263 #define KS884X_P2MBCR_P 0x04E0
264 #define KS884X_P2MBSR_P 0x04E2
265 #define KS884X_PHY2ILR_P 0x04E4
266 #define KS884X_PHY2IHR_P 0x04E6
267 #define KS884X_P2ANAR_P 0x04E8
268 #define KS884X_P2ANLPR_P 0x04EA
273 #define KS884X_PHY_CTRL_OFFSET 0x00
275 #define KS884X_PHY_STATUS_OFFSET 0x02
277 #define KS884X_PHY_ID_1_OFFSET 0x04
278 #define KS884X_PHY_ID_2_OFFSET 0x06
280 #define KS884X_PHY_AUTO_NEG_OFFSET 0x08
282 #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
285 #define KS884X_P1VCT_P 0x04F0
286 #define KS884X_P1PHYCTRL_P 0x04F2
289 #define KS884X_P2VCT_P 0x04F4
290 #define KS884X_P2PHYCTRL_P 0x04F6
295 #define KS884X_PHY_LINK_MD_OFFSET 0x00
297 #define PHY_START_CABLE_DIAG 0x8000
298 #define PHY_CABLE_DIAG_RESULT 0x6000
299 #define PHY_CABLE_STAT_NORMAL 0x0000
300 #define PHY_CABLE_STAT_OPEN 0x2000
301 #define PHY_CABLE_STAT_SHORT 0x4000
302 #define PHY_CABLE_STAT_FAILED 0x6000
303 #define PHY_CABLE_10M_SHORT 0x1000
304 #define PHY_CABLE_FAULT_COUNTER 0x01FF
306 #define KS884X_PHY_PHY_CTRL_OFFSET 0x02
308 #define PHY_STAT_REVERSED_POLARITY 0x0020
309 #define PHY_STAT_MDIX 0x0010
310 #define PHY_FORCE_LINK 0x0008
311 #define PHY_POWER_SAVING_DISABLE 0x0004
312 #define PHY_REMOTE_LOOPBACK 0x0002
315 #define KS884X_SIDER_P 0x0400
319 #define REG_FAMILY_ID 0x88
321 #define REG_CHIP_ID_41 0x8810
322 #define REG_CHIP_ID_42 0x8800
324 #define KS884X_CHIP_ID_MASK_41 0xFF10
325 #define KS884X_CHIP_ID_MASK 0xFFF0
327 #define KS884X_REVISION_MASK 0x000E
329 #define KS8842_START 0x0001
331 #define CHIP_IP_41_M 0x8810
332 #define CHIP_IP_42_M 0x8800
333 #define CHIP_IP_61_M 0x8890
334 #define CHIP_IP_62_M 0x8880
336 #define CHIP_IP_41_P 0x8850
337 #define CHIP_IP_42_P 0x8840
338 #define CHIP_IP_61_P 0x88D0
339 #define CHIP_IP_62_P 0x88C0
342 #define KS8842_SGCR1_P 0x0402
345 #define SWITCH_PASS_ALL 0x8000
346 #define SWITCH_TX_FLOW_CTRL 0x2000
347 #define SWITCH_RX_FLOW_CTRL 0x1000
348 #define SWITCH_CHECK_LENGTH 0x0800
349 #define SWITCH_AGING_ENABLE 0x0400
350 #define SWITCH_FAST_AGING 0x0200
351 #define SWITCH_AGGR_BACKOFF 0x0100
352 #define SWITCH_PASS_PAUSE 0x0008
353 #define SWITCH_LINK_AUTO_AGING 0x0001
356 #define KS8842_SGCR2_P 0x0404
359 #define SWITCH_VLAN_ENABLE 0x8000
360 #define SWITCH_IGMP_SNOOP 0x4000
361 #define IPV6_MLD_SNOOP_ENABLE 0x2000
362 #define IPV6_MLD_SNOOP_OPTION 0x1000
363 #define PRIORITY_SCHEME_SELECT 0x0800
364 #define SWITCH_MIRROR_RX_TX 0x0100
365 #define UNICAST_VLAN_BOUNDARY 0x0080
366 #define MULTICAST_STORM_DISABLE 0x0040
367 #define SWITCH_BACK_PRESSURE 0x0020
368 #define FAIR_FLOW_CTRL 0x0010
369 #define NO_EXC_COLLISION_DROP 0x0008
370 #define SWITCH_HUGE_PACKET 0x0004
371 #define SWITCH_LEGAL_PACKET 0x0002
372 #define SWITCH_BUF_RESERVE 0x0001
375 #define KS8842_SGCR3_P 0x0406
378 #define BROADCAST_STORM_RATE_LO 0xFF00
379 #define SWITCH_REPEATER 0x0080
380 #define SWITCH_HALF_DUPLEX 0x0040
381 #define SWITCH_FLOW_CTRL 0x0020
382 #define SWITCH_10_MBIT 0x0010
383 #define SWITCH_REPLACE_NULL_VID 0x0008
384 #define BROADCAST_STORM_RATE_HI 0x0007
386 #define BROADCAST_STORM_RATE 0x07FF
389 #define KS8842_SGCR4_P 0x0408
392 #define KS8842_SGCR5_P 0x040A
395 #define LED_MODE 0x8200
396 #define LED_SPEED_DUPLEX_ACT 0x0000
397 #define LED_SPEED_DUPLEX_LINK_ACT 0x8000
398 #define LED_DUPLEX_10_100 0x0200
401 #define KS8842_SGCR6_P 0x0410
408 #define KS8842_SGCR7_P 0x0412
411 #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
412 #define SWITCH_UNK_DEF_PORT_3 0x0004
413 #define SWITCH_UNK_DEF_PORT_2 0x0002
414 #define SWITCH_UNK_DEF_PORT_1 0x0001
417 #define KS8842_MACAR1_P 0x0470
418 #define KS8842_MACAR2_P 0x0472
419 #define KS8842_MACAR3_P 0x0474
428 #define KS8842_TOSR1_P 0x0480
429 #define KS8842_TOSR2_P 0x0482
430 #define KS8842_TOSR3_P 0x0484
431 #define KS8842_TOSR4_P 0x0486
432 #define KS8842_TOSR5_P 0x0488
433 #define KS8842_TOSR6_P 0x048A
434 #define KS8842_TOSR7_P 0x0490
435 #define KS8842_TOSR8_P 0x0492
447 #define KS8842_P1CR1_P 0x0500
448 #define KS8842_P1CR2_P 0x0502
449 #define KS8842_P1VIDR_P 0x0504
450 #define KS8842_P1CR3_P 0x0506
451 #define KS8842_P1IRCR_P 0x0508
452 #define KS8842_P1ERCR_P 0x050A
453 #define KS884X_P1SCSLMD_P 0x0510
454 #define KS884X_P1CR4_P 0x0512
455 #define KS884X_P1SR_P 0x0514
458 #define KS8842_P2CR1_P 0x0520
459 #define KS8842_P2CR2_P 0x0522
460 #define KS8842_P2VIDR_P 0x0524
461 #define KS8842_P2CR3_P 0x0526
462 #define KS8842_P2IRCR_P 0x0528
463 #define KS8842_P2ERCR_P 0x052A
464 #define KS884X_P2SCSLMD_P 0x0530
465 #define KS884X_P2CR4_P 0x0532
466 #define KS884X_P2SR_P 0x0534
469 #define KS8842_P3CR1_P 0x0540
470 #define KS8842_P3CR2_P 0x0542
471 #define KS8842_P3VIDR_P 0x0544
472 #define KS8842_P3CR3_P 0x0546
473 #define KS8842_P3IRCR_P 0x0548
474 #define KS8842_P3ERCR_P 0x054A
484 #define KS8842_PORT_CTRL_1_OFFSET 0x00
486 #define PORT_BROADCAST_STORM 0x0080
487 #define PORT_DIFFSERV_ENABLE 0x0040
488 #define PORT_802_1P_ENABLE 0x0020
489 #define PORT_BASED_PRIORITY_MASK 0x0018
490 #define PORT_BASED_PRIORITY_BASE 0x0003
492 #define PORT_BASED_PRIORITY_0 0x0000
493 #define PORT_BASED_PRIORITY_1 0x0008
494 #define PORT_BASED_PRIORITY_2 0x0010
495 #define PORT_BASED_PRIORITY_3 0x0018
496 #define PORT_INSERT_TAG 0x0004
497 #define PORT_REMOVE_TAG 0x0002
498 #define PORT_PRIO_QUEUE_ENABLE 0x0001
500 #define KS8842_PORT_CTRL_2_OFFSET 0x02
502 #define PORT_INGRESS_VLAN_FILTER 0x4000
503 #define PORT_DISCARD_NON_VID 0x2000
504 #define PORT_FORCE_FLOW_CTRL 0x1000
505 #define PORT_BACK_PRESSURE 0x0800
506 #define PORT_TX_ENABLE 0x0400
507 #define PORT_RX_ENABLE 0x0200
508 #define PORT_LEARN_DISABLE 0x0100
509 #define PORT_MIRROR_SNIFFER 0x0080
510 #define PORT_MIRROR_RX 0x0040
511 #define PORT_MIRROR_TX 0x0020
512 #define PORT_USER_PRIORITY_CEILING 0x0008
513 #define PORT_VLAN_MEMBERSHIP 0x0007
515 #define KS8842_PORT_CTRL_VID_OFFSET 0x04
517 #define PORT_DEFAULT_VID 0x0001
519 #define KS8842_PORT_CTRL_3_OFFSET 0x06
521 #define PORT_INGRESS_LIMIT_MODE 0x000C
522 #define PORT_INGRESS_ALL 0x0000
523 #define PORT_INGRESS_UNICAST 0x0004
524 #define PORT_INGRESS_MULTICAST 0x0008
525 #define PORT_INGRESS_BROADCAST 0x000C
526 #define PORT_COUNT_IFG 0x0002
527 #define PORT_COUNT_PREAMBLE 0x0001
529 #define KS8842_PORT_IN_RATE_OFFSET 0x08
530 #define KS8842_PORT_OUT_RATE_OFFSET 0x0A
532 #define PORT_PRIORITY_RATE 0x0F
535 #define KS884X_PORT_LINK_MD 0x10
537 #define PORT_CABLE_10M_SHORT 0x8000
538 #define PORT_CABLE_DIAG_RESULT 0x6000
539 #define PORT_CABLE_STAT_NORMAL 0x0000
540 #define PORT_CABLE_STAT_OPEN 0x2000
541 #define PORT_CABLE_STAT_SHORT 0x4000
542 #define PORT_CABLE_STAT_FAILED 0x6000
543 #define PORT_START_CABLE_DIAG 0x1000
544 #define PORT_FORCE_LINK 0x0800
545 #define PORT_POWER_SAVING_DISABLE 0x0400
546 #define PORT_PHY_REMOTE_LOOPBACK 0x0200
547 #define PORT_CABLE_FAULT_COUNTER 0x01FF
549 #define KS884X_PORT_CTRL_4_OFFSET 0x12
551 #define PORT_LED_OFF 0x8000
552 #define PORT_TX_DISABLE 0x4000
553 #define PORT_AUTO_NEG_RESTART 0x2000
554 #define PORT_REMOTE_FAULT_DISABLE 0x1000
555 #define PORT_POWER_DOWN 0x0800
556 #define PORT_AUTO_MDIX_DISABLE 0x0400
557 #define PORT_FORCE_MDIX 0x0200
558 #define PORT_LOOPBACK 0x0100
559 #define PORT_AUTO_NEG_ENABLE 0x0080
560 #define PORT_FORCE_100_MBIT 0x0040
561 #define PORT_FORCE_FULL_DUPLEX 0x0020
562 #define PORT_AUTO_NEG_SYM_PAUSE 0x0010
563 #define PORT_AUTO_NEG_100BTX_FD 0x0008
564 #define PORT_AUTO_NEG_100BTX 0x0004
565 #define PORT_AUTO_NEG_10BT_FD 0x0002
566 #define PORT_AUTO_NEG_10BT 0x0001
568 #define KS884X_PORT_STATUS_OFFSET 0x14
570 #define PORT_HP_MDIX 0x8000
571 #define PORT_REVERSED_POLARITY 0x2000
572 #define PORT_RX_FLOW_CTRL 0x0800
573 #define PORT_TX_FLOW_CTRL 0x1000
574 #define PORT_STATUS_SPEED_100MBIT 0x0400
575 #define PORT_STATUS_FULL_DUPLEX 0x0200
576 #define PORT_REMOTE_FAULT 0x0100
577 #define PORT_MDIX_STATUS 0x0080
578 #define PORT_AUTO_NEG_COMPLETE 0x0040
579 #define PORT_STATUS_LINK_GOOD 0x0020
580 #define PORT_REMOTE_SYM_PAUSE 0x0010
581 #define PORT_REMOTE_100BTX_FD 0x0008
582 #define PORT_REMOTE_100BTX 0x0004
583 #define PORT_REMOTE_10BT_FD 0x0002
584 #define PORT_REMOTE_10BT 0x0001
595 #define STATIC_MAC_TABLE_ADDR 0x0000FFFF
596 #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
597 #define STATIC_MAC_TABLE_VALID 0x00080000
598 #define STATIC_MAC_TABLE_OVERRIDE 0x00100000
599 #define STATIC_MAC_TABLE_USE_FID 0x00200000
600 #define STATIC_MAC_TABLE_FID 0x03C00000
612 #define VLAN_TABLE_VID 0x00000FFF
613 #define VLAN_TABLE_FID 0x0000F000
614 #define VLAN_TABLE_MEMBERSHIP 0x00070000
615 #define VLAN_TABLE_VALID 0x00080000
631 #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
632 #define DYNAMIC_MAC_TABLE_FID 0x000F0000
633 #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
634 #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
635 #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
637 #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
638 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
639 #define DYNAMIC_MAC_TABLE_RESERVED 0x78
640 #define DYNAMIC_MAC_TABLE_NOT_READY 0x80
654 #define MIB_COUNTER_VALUE 0x3FFFFFFF
655 #define MIB_COUNTER_VALID 0x40000000
656 #define MIB_COUNTER_OVERFLOW 0x80000000
658 #define MIB_PACKET_DROPPED 0x0000FFFF
660 #define KS_MIB_PACKET_DROPPED_TX_0 0x100
661 #define KS_MIB_PACKET_DROPPED_TX_1 0x101
662 #define KS_MIB_PACKET_DROPPED_TX 0x102
663 #define KS_MIB_PACKET_DROPPED_RX_0 0x103
664 #define KS_MIB_PACKET_DROPPED_RX_1 0x104
665 #define KS_MIB_PACKET_DROPPED_RX 0x105
717 #define KS_DESC_RX_FRAME_LEN 0x000007FF
718 #define KS_DESC_RX_FRAME_TYPE 0x00008000
719 #define KS_DESC_RX_ERROR_CRC 0x00010000
720 #define KS_DESC_RX_ERROR_RUNT 0x00020000
721 #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
722 #define KS_DESC_RX_ERROR_PHY 0x00080000
723 #define KS884X_DESC_RX_PORT_MASK 0x00300000
724 #define KS_DESC_RX_MULTICAST 0x01000000
725 #define KS_DESC_RX_ERROR 0x02000000
726 #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
727 #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
728 #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
729 #define KS_DESC_RX_LAST 0x20000000
730 #define KS_DESC_RX_FIRST 0x40000000
737 #define KS_DESC_HW_OWNED 0x80000000
739 #define KS_DESC_BUF_SIZE 0x000007FF
740 #define KS884X_DESC_TX_PORT_MASK 0x00300000
741 #define KS_DESC_END_OF_RING 0x02000000
742 #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
743 #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
744 #define KS_DESC_TX_CSUM_GEN_IP 0x10000000
745 #define KS_DESC_TX_LAST 0x20000000
746 #define KS_DESC_TX_FIRST 0x40000000
747 #define KS_DESC_TX_INTERRUPT 0x80000000
949 TABLE_STATIC_MAC = 0,
1001 #define MAIN_PORT 0
1005 #define PORT_COUNTER_NUM 0x20
1008 #define MIB_COUNTER_RX_LO_PRIORITY 0x00
1009 #define MIB_COUNTER_RX_HI_PRIORITY 0x01
1010 #define MIB_COUNTER_RX_UNDERSIZE 0x02
1011 #define MIB_COUNTER_RX_FRAGMENT 0x03
1012 #define MIB_COUNTER_RX_OVERSIZE 0x04
1013 #define MIB_COUNTER_RX_JABBER 0x05
1014 #define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1015 #define MIB_COUNTER_RX_CRC_ERR 0x07
1016 #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1017 #define MIB_COUNTER_RX_CTRL_8808 0x09
1018 #define MIB_COUNTER_RX_PAUSE 0x0A
1019 #define MIB_COUNTER_RX_BROADCAST 0x0B
1020 #define MIB_COUNTER_RX_MULTICAST 0x0C
1021 #define MIB_COUNTER_RX_UNICAST 0x0D
1022 #define MIB_COUNTER_RX_OCTET_64 0x0E
1023 #define MIB_COUNTER_RX_OCTET_65_127 0x0F
1024 #define MIB_COUNTER_RX_OCTET_128_255 0x10
1025 #define MIB_COUNTER_RX_OCTET_256_511 0x11
1026 #define MIB_COUNTER_RX_OCTET_512_1023 0x12
1027 #define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1028 #define MIB_COUNTER_TX_LO_PRIORITY 0x14
1029 #define MIB_COUNTER_TX_HI_PRIORITY 0x15
1030 #define MIB_COUNTER_TX_LATE_COLLISION 0x16
1031 #define MIB_COUNTER_TX_PAUSE 0x17
1032 #define MIB_COUNTER_TX_BROADCAST 0x18
1033 #define MIB_COUNTER_TX_MULTICAST 0x19
1034 #define MIB_COUNTER_TX_UNICAST 0x1A
1035 #define MIB_COUNTER_TX_DEFERRED 0x1B
1036 #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1037 #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1038 #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1039 #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1041 #define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1042 #define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1049 * @mib_start: The starting counter index. Some ports do not start at 0.
1145 #define LINK_INT_WORKING (1 << 0)
1152 #define PAUSE_FLOW_CTRL (1 << 0)
1250 * duplex, and 0 for auto, which normally results in full
1253 * 0 for auto, which normally results in 100 Mbit.
1254 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1412 #define DRV_VERSION "1.0.0"
1418 static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1432 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE); in hw_dis_intr()
1444 hw->intr_blocked = 0; in hw_ena_intr()
1502 uint interrupt = 0; in hw_block_intr()
1517 status.rx.hw_owned = 0; in reset_desc()
1572 #define TABLE_READ 0x10
1578 } while (0)
1659 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1]; in sw_w_sta_mac_table()
1685 * Return 0 if the entry is valid; otherwise -1.
1698 return 0; in sw_r_vlan_table()
1728 for (timeout = 100; timeout > 0; timeout--) { in port_r_mib_cnt()
1813 mib->cnt_ptr = 0; in port_r_cnt()
1814 return 0; in port_r_cnt()
1829 mib->cnt_ptr = 0; in port_init_cnt()
1839 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); in port_init_cnt()
1840 mib->cnt_ptr = 0; in port_init_cnt()
1936 * Return 0 if the bits are not set.
1998 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8); in sw_cfg_broad_storm()
2031 port_cfg_broad_storm(hw, port, 0); in sw_dis_broad_storm()
2059 for (port = 0; port < TOTAL_PORT_NUM; port++) in sw_init_broad_storm()
2095 writel(0, hw->io + addr); in sw_dis_prio_rate()
2110 for (port = 0; port < TOTAL_PORT_NUM; port++) { in sw_init_prio_rate()
2111 for (prio = 0; prio < PRIO_QUEUES; prio++) { in sw_init_prio_rate()
2113 sw->port_cfg[port].tx_rate[prio] = 0; in sw_init_prio_rate()
2156 for (port = 0; port < TOTAL_PORT_NUM; port++) { in sw_init_mirror()
2157 port_cfg_mirror_sniffer(hw, port, 0); in sw_init_mirror()
2158 port_cfg_mirror_rx(hw, port, 0); in sw_init_mirror()
2159 port_cfg_mirror_tx(hw, port, 0); in sw_init_mirror()
2161 sw_cfg_mirror_rx_tx(hw, 0); in sw_init_mirror()
2199 port_cfg_diffserv(hw, port, 0); in sw_dis_diffserv()
2211 port_cfg_802_1p(hw, port, 0); in sw_dis_802_1p()
2274 port_cfg_prio(hw, port, 0); in sw_dis_multi_queue()
2293 sw->p_802_1p[0] = 0; in sw_init_prio()
2294 sw->p_802_1p[1] = 0; in sw_init_prio()
2304 * queue 0. in sw_init_prio()
2306 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++) in sw_init_prio()
2307 sw->diffserv[tos] = 0; in sw_init_prio()
2310 for (port = 0; port < TOTAL_PORT_NUM; port++) { in sw_init_prio()
2314 sw_cfg_replace_vid(hw, port, 0); in sw_init_prio()
2316 sw->port_cfg[port].port_prio = 0; in sw_init_prio()
2319 sw_cfg_replace_null_vid(hw, 0); in sw_init_prio()
2352 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) { in sw_init_vlan()
2359 for (port = 0; port < TOTAL_PORT_NUM; port++) { in sw_init_vlan()
2400 for (i = 0; i < 6; i += 2) { in sw_set_addr()
2444 STP_STATE_DISABLED = 0,
2505 #define STP_ENTRY 0
2521 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) { in sw_clr_sta_mac_table()
2525 entry->override, 0, in sw_clr_sta_mac_table()
2541 entry->mac_addr[0] = 0x01; in sw_init_stp()
2542 entry->mac_addr[1] = 0x80; in sw_init_stp()
2543 entry->mac_addr[2] = 0xC2; in sw_init_stp()
2544 entry->mac_addr[3] = 0x00; in sw_init_stp()
2545 entry->mac_addr[4] = 0x00; in sw_init_stp()
2546 entry->mac_addr[5] = 0x00; in sw_init_stp()
2569 entry->valid = 0; in sw_block_addr()
2625 #define AT93C_CODE 0
2626 #define AT93C_WR_OFF 0x00
2627 #define AT93C_WR_ALL 0x10
2628 #define AT93C_ER_ALL 0x20
2629 #define AT93C_WR_ON 0x30
2674 u16 temp = 0; in spi_r()
2676 for (i = 15; i >= 0; i--) { in spi_r()
2680 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0; in spi_r()
2692 for (i = 15; i >= 0; i--) { in spi_w()
2693 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : in spi_w()
2708 for (i = 1; i >= 0; i--) { in spi_reg()
2709 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : in spi_reg()
2715 for (i = 5; i >= 0; i--) { in spi_reg()
2716 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : in spi_reg()
2722 #define EEPROM_DATA_RESERVED 0
2867 rx = tx = 0; in determine_flow_ctrl()
2925 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { in port_get_link_speed()
3004 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { in port_set_link_speed()
3008 cfg = 0; in port_set_link_speed()
3054 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { in port_force_link_speed()
3078 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) in port_set_power_saving()
3093 * Return 1 if PMEN pin is asserted; otherwise, 0.
3102 return 0; in hw_chk_wol_pme_status()
3192 u8 val = 0; in hw_set_wol_frame()
3199 i *= 0x10; in hw_set_wol_frame()
3200 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i); in hw_set_wol_frame()
3201 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i); in hw_set_wol_frame()
3203 bits = len = from = to = 0; in hw_set_wol_frame()
3242 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 }; in hw_add_wol_arp()
3244 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, in hw_add_wol_arp()
3245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in hw_add_wol_arp()
3246 0x08, 0x06, in hw_add_wol_arp()
3247 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, in hw_add_wol_arp()
3248 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in hw_add_wol_arp()
3249 0x00, 0x00, 0x00, 0x00, in hw_add_wol_arp()
3250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in hw_add_wol_arp()
3251 0x00, 0x00, 0x00, 0x00 }; in hw_add_wol_arp()
3265 static const u8 mask[] = { 0x3F }; in hw_add_wol_bcast()
3266 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; in hw_add_wol_bcast()
3283 static const u8 mask[] = { 0x3F }; in hw_add_wol_mcast()
3284 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 }; in hw_add_wol_mcast()
3301 static const u8 mask[] = { 0x3F }; in hw_add_wol_ucast()
3303 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr); in hw_add_wol_ucast()
3333 * Return number of ports or 0 if not right.
3337 int rc = 0; in hw_init()
3354 return 0; in hw_init()
3378 /* Write 0 to clear device reset. */ in hw_reset()
3379 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET); in hw_reset()
3436 shift = 0; in ksz_check_desc_num()
3463 for (i = 0; i < desc_info->alloc; i++) { in hw_init_desc()
3474 desc_info->last = desc_info->next = 0; in hw_init_desc()
3498 info->last = info->next = 0; in hw_reset_pkts()
3524 if (0 == hw->rx_stop) in hw_start_rx()
3536 hw->rx_stop = 0; in hw_stop_rx()
3573 hw->enabled = 0; in hw_disable()
3597 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3603 return 0; in hw_alloc_pkt()
3638 hw->tx_int_cnt = 0; in hw_send_pkt()
3639 hw->tx_size = 0; in hw_send_pkt()
3647 writel(0, hw->io + KS_DMA_TX_START); in hw_send_pkt()
3655 return 0 == *addr1 && 0 == *addr2; in empty_addr()
3669 for (i = 0; i < ETH_ALEN; i++) in hw_set_addr()
3686 for (i = 0; i < ETH_ALEN; i++) in hw_read_addr()
3708 mac_addr_hi = 0; in hw_ena_add_addr()
3709 for (i = 0; i < 2; i++) { in hw_ena_add_addr()
3714 mac_addr_lo = 0; in hw_ena_add_addr()
3729 for (i = 0; i < ADDITIONAL_ENTRIES; i++) { in hw_set_add_addr()
3731 writel(0, hw->io + ADD_ADDR_INCR * i + in hw_set_add_addr()
3744 return 0; in hw_add_addr()
3745 for (i = 0; i < hw->addr_list_size; i++) { in hw_add_addr()
3747 return 0; in hw_add_addr()
3754 return 0; in hw_add_addr()
3763 for (i = 0; i < hw->addr_list_size; i++) { in hw_del_addr()
3766 writel(0, hw->io + ADD_ADDR_INCR * i + in hw_del_addr()
3768 return 0; in hw_del_addr()
3784 for (i = 0; i < HW_MULTICAST_SIZE; i++) { in hw_clr_multicast()
3785 hw->multi_bits[i] = 0; in hw_clr_multicast()
3787 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i); in hw_clr_multicast()
3805 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE); in hw_set_grp_addr()
3807 for (i = 0; i < hw->multi_list_size; i++) { in hw_set_grp_addr()
3808 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f; in hw_set_grp_addr()
3814 for (i = 0; i < HW_MULTICAST_SIZE; i++) in hw_set_grp_addr()
3872 for (port = 0; port < SWITCH_PORT_NUM; port++) { in sw_enable()
3908 for (port = 0; port < SWITCH_PORT_NUM; port++) in sw_setup()
3936 info->cnt = 0; in ksz_start_timer()
3953 info->max = 0; in ksz_stop_timer()
3961 info->max = 0; in ksz_init_timer()
3963 timer_setup(&info->timer, function, 0); in ksz_init_timer()
3969 if (info->max > 0) { in ksz_update_timer()
3974 info->max = 0; in ksz_update_timer()
3975 } else if (info->max < 0) { in ksz_update_timer()
3989 * Return 0 if successful.
3998 return 0; in ksz_alloc_soft_desc()
4008 * Return 0 if successful.
4026 adapter->desc_pool.alloc_size = 0; in ksz_alloc_desc()
4033 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0); in ksz_alloc_desc()
4046 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0)) in ksz_alloc_desc()
4051 return 0; in ksz_alloc_desc()
4069 dma_buf->dma = 0; in free_dma_buf()
4086 for (i = 0; i < hw->rx_desc_info.alloc; i++) { in ksz_init_rx_buffers()
4115 * Return 0 if successful.
4126 hw->tx_int_cnt = 0; in ksz_alloc_mem()
4136 hw->tx_int_cnt = 0; in ksz_alloc_mem()
4155 return 0; in ksz_alloc_mem()
4172 hw->rx_desc_info.ring_phys = 0; in ksz_free_desc()
4173 hw->tx_desc_info.ring_phys = 0; in ksz_free_desc()
4183 adapter->desc_pool.alloc_size = 0; in ksz_free_desc()
4207 for (i = 0; i < desc_info->alloc; i++) { in ksz_free_buffers()
4241 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); in get_mib_counters()
4242 for (i = 0, port = first; i < cnt; i++, port++) { in get_mib_counters()
4294 frag = 0; in send_packet()
4425 for (port = 0; port < hw->dev_count; port++) { in tx_done()
4451 * Return 0 if successful; otherwise an error code indicating failure.
4460 int rc = 0; in netdev_tx()
4467 memset(&skb->data[skb->len], 0, 50 - skb->len); in netdev_tx()
4474 memset(&skb->data[org_skb->len], 0, in netdev_tx()
4549 transmit_cleanup(hw_priv, 0); in netdev_tx_timeout()
4567 for (port = 0; port < SWITCH_PORT_NUM; port++) { in netdev_tx_timeout()
4638 } while (0); in rx_proc()
4652 return 0; in rx_proc()
4660 struct net_device *dev = hw->port_info[0].pdev; in dev_rcv_packets()
4664 int received = 0; in dev_rcv_packets()
4696 struct net_device *dev = hw->port_info[0].pdev; in port_rcv_packets()
4700 int received = 0; in port_rcv_packets()
4741 struct net_device *dev = hw->port_info[0].pdev; in dev_rcv_special()
4745 int received = 0; in dev_rcv_special()
4835 if (0 == hw->rx_stop) in handle_rx_stop()
4842 hw->rx_stop = 0; in handle_rx_stop()
4860 uint int_enable = 0; in netdev_intr()
4917 } while (0); in netdev_intr()
4953 for (port = 0; port < SWITCH_PORT_NUM; port++) { in bridge_change()
4970 * Return 0 if successful; otherwise an error code indicating failure.
4997 if (port->first_port > 0) in netdev_close()
5023 transmit_cleanup(hw_priv, 0); in netdev_close()
5032 return 0; in netdev_close()
5064 int rc = 0; in prepare_hardware()
5074 hw->promiscuous = 0; in prepare_hardware()
5075 hw->all_multi = 0; in prepare_hardware()
5076 hw->multi_list_size = 0; in prepare_hardware()
5085 return 0; in prepare_hardware()
5107 * Return 0 if successful; otherwise an error code indicating failure.
5118 int rc = 0; in netdev_open()
5121 priv->multicast = 0; in netdev_open()
5122 priv->promiscuous = 0; in netdev_open()
5125 memset(&dev->stats, 0, sizeof(struct net_device_stats)); in netdev_open()
5126 memset((void *) port->counter, 0, in netdev_open()
5133 for (i = 0; i < hw->mib_port_cnt; i++) { in netdev_open()
5143 hw_cfg_wol_pme(hw, 0); in netdev_open()
5149 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { in netdev_open()
5154 hw->port_info[p].partner = 0xFF; in netdev_open()
5161 if (port->first_port > 0) in netdev_open()
5191 return 0; in netdev_open()
5226 dev->stats.multicast = 0; in netdev_query_statistics()
5227 dev->stats.collisions = 0; in netdev_query_statistics()
5228 dev->stats.rx_length_errors = 0; in netdev_query_statistics()
5229 dev->stats.rx_crc_errors = 0; in netdev_query_statistics()
5230 dev->stats.rx_frame_errors = 0; in netdev_query_statistics()
5231 dev->stats.tx_window_errors = 0; in netdev_query_statistics()
5233 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { in netdev_query_statistics()
5267 * Return 0 to indicate success.
5277 if (priv->port.first_port > 0) in netdev_set_mac_address()
5288 if (priv->port.first_port > 0) in netdev_set_mac_address()
5294 return 0; in netdev_set_mac_address()
5376 int i = 0; in netdev_set_rx_mode()
5400 hw->multi_list_size = 0; in netdev_set_rx_mode()
5418 return 0; in netdev_change_mtu()
5432 return 0; in netdev_change_mtu()
5443 * Return 0 to indicate success.
5451 int result = 0; in netdev_ioctl()
5534 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++) in mdio_write()
5542 #define EEPROM_SIZE 0x40
5544 static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5561 * Return 0 if successful; otherwise an error code.
5578 return 0; in netdev_get_link_ksettings()
5588 * Return 0 if successful; otherwise an error code.
5618 if (0 == cmd->base.duplex) in netdev_set_link_ksettings()
5630 port->duplex = 0; in netdev_set_link_ksettings()
5631 port->speed = 0; in netdev_set_link_ksettings()
5632 port->force_link = 0; in netdev_set_link_ksettings()
5638 port->force_link = 0; in netdev_set_link_ksettings()
5659 * Return 0 if successful; otherwise an error code.
5719 { 0, 0 }
5733 int regs_len = 0x10 * sizeof(u32); in netdev_get_regs_len()
5761 regs->version = 0; in netdev_get_regs()
5762 for (len = 0; len < 0x40; len += 4) { in netdev_get_regs()
5796 memset(&wol->sopass, 0, sizeof(wol->sopass)); in netdev_get_wol()
5806 * Return 0 if successful; otherwise an error code.
5826 return 0; in netdev_set_wol()
5871 #define EEPROM_MAGIC 0x10A18842
5881 * Return 0 if successful; otherwise an error code.
5898 return 0; in netdev_get_eeprom()
5909 * Return 0 if successful; otherwise an error code.
5929 for (i = 0; i < EEPROM_SIZE; i++) in netdev_set_eeprom()
5935 return 0; in netdev_set_eeprom()
5952 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1; in netdev_get_pauseparam()
5955 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0; in netdev_get_pauseparam()
5957 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0; in netdev_get_pauseparam()
5961 SWITCH_RX_FLOW_CTRL)) ? 1 : 0; in netdev_get_pauseparam()
5964 SWITCH_TX_FLOW_CTRL)) ? 1 : 0; in netdev_get_pauseparam()
5976 * Return 0 if successful; otherwise an error code.
5993 port->force_link = 0; in netdev_set_pauseparam()
6013 return 0; in netdev_set_pauseparam()
6148 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { in netdev_get_ethtool_stats()
6169 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) { in netdev_get_ethtool_stats()
6170 if (0 == i) { in netdev_get_ethtool_stats()
6188 for (i = 0; i < n; i++) in netdev_get_ethtool_stats()
6199 * Return 0 if successful; otherwise an error code.
6221 return 0; in netdev_set_features()
6271 for (i = 0; i < hw->mib_port_cnt; i++) { in mib_read_work()
6280 hw_priv->counter[i].read = 0; in mib_read_work()
6283 if (0 == mib->cnt_ptr) { in mib_read_work()
6297 mib->link_down = 0; in mib_read_work()
6316 hw_priv->pme_wait = 0; in mib_monitor()
6399 * Return 0 if successful; otherwise an error code indicating failure.
6424 priv->mii_if.phy_id_mask = 0x1; in netdev_init()
6425 priv->mii_if.reg_num_mask = 0x7; in netdev_init()
6434 return 0; in netdev_init()
6477 i = j = num = got_num = 0; in get_mac_addr()
6484 if (digit >= 0) in get_mac_addr()
6505 num = got_num = 0; in get_mac_addr()
6515 #define KS884X_DMA_MASK (~0x0UL)
6523 for (i = 0; i < 3; i++) in read_other_addr()
6525 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) { in read_other_addr()
6526 sw->other_addr[5] = (u8) data[0]; in read_other_addr()
6527 sw->other_addr[4] = (u8)(data[0] >> 8); in read_other_addr()
6531 sw->other_addr[0] = (u8)(data[2] >> 8); in read_other_addr()
6536 #define PCI_VENDOR_ID_MICREL_KS 0x16c6
6568 reg_base = pci_resource_start(pdev, 0); in pcidev_init()
6569 reg_len = pci_resource_len(pdev, 0); in pcidev_init()
6570 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) in pcidev_init()
6601 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */ in pcidev_init()
6609 hw->addr_list_size = 0; in pcidev_init()
6638 for (i = 0; i < hw->mib_port_cnt; i++) in pcidev_init()
6639 hw->port_mib[i].mib_start = 0; in pcidev_init()
6654 for (i = 0; i < TOTAL_PORT_NUM; i++) in pcidev_init()
6657 if (macaddr[0] != ':') in pcidev_init()
6667 if (mac1addr[0] != ':') in pcidev_init()
6676 hw_priv->wol_enable = 0; in pcidev_init()
6685 for (i = 0; i < hw->dev_count; i++) { in pcidev_init()
6705 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) { in pcidev_init()
6740 return 0; in pcidev_init()
6743 for (i = 0; i < hw->dev_count; i++) { in pcidev_init()
6772 release_mem_region(pci_resource_start(pdev, 0), in pcidev_exit()
6773 pci_resource_len(pdev, 0)); in pcidev_exit()
6774 for (i = 0; i < hw_priv->hw.dev_count; i++) { in pcidev_exit()
6796 hw_cfg_wol_pme(hw, 0); in pcidev_resume()
6797 for (i = 0; i < hw->dev_count; i++) { in pcidev_resume()
6807 return 0; in pcidev_resume()
6820 for (i = 0; i < hw->dev_count; i++) { in pcidev_suspend()
6836 return 0; in pcidev_suspend()
6842 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
6843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
6844 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
6845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
6846 { 0 }
6867 module_param_named(message, msg_enable, int, 0);
6868 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
6870 module_param(macaddr, charp, 0);
6871 module_param(mac1addr, charp, 0);
6872 module_param(fast_aging, int, 0);
6873 module_param(multi_dev, int, 0);
6874 module_param(stp, int, 0);