Lines Matching +full:csr +full:- +full:offset
1 /* SPDX-License-Identifier: GPL-2.0 */
43 /* Length, Type, Offset Masks and Shifts */
125 (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1))
152 #define FBNIC_RCD_AL_BUFF_FRAG_MASK (FBNIC_BD_FRAG_COUNT - 1)
211 #define FBNIC_CSR_START_INTR 0x00000 /* CSR section delimiter */
236 #define FBNIC_CSR_END_INTR 0x0005f /* CSR section delimiter */
239 #define FBNIC_CSR_START_INTR_CQ 0x00400 /* CSR section delimiter */
256 #define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */
259 #define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */
309 #define FBNIC_CSR_END_QM_TX 0x00873 /* CSR section delimiter */
312 #define FBNIC_CSR_START_QM_RX 0x00c00 /* CSR section delimiter */
337 #define FBNIC_CSR_END_QM_RX 0x00c34 /* CSR section delimiter */
340 #define FBNIC_CSR_START_TCE 0x04000 /* CSR section delimiter */
440 #define FBNIC_CSR_END_TCE 0x04050 /* CSR section delimiter */
443 #define FBNIC_CSR_START_TCE_RAM 0x04200 /* CSR section delimiter */
452 #define FBNIC_CSR_END_TCE_RAM 0x0421F /* CSR section delimiter */
455 #define FBNIC_CSR_START_TMI 0x04400 /* CSR section delimiter */
484 #define FBNIC_CSR_END_TMI 0x0443f /* CSR section delimiter */
487 #define FBNIC_CSR_START_PTP 0x04800 /* CSR section delimiter */
521 #define FBNIC_CSR_END_PTP 0x0480d /* CSR section delimiter */
524 #define FBNIC_CSR_START_RXB 0x08000 /* CSR section delimiter */
646 #define FBNIC_CSR_END_RXB 0x081b1 /* CSR section delimiter */
649 #define FBNIC_CSR_START_RPC 0x08400 /* CSR section delimiter */
695 (FBNIC_RPC_RSS_KEY_DWORD_LEN - 1)
698 FBNIC_RPC_RSS_KEY_DWORD_LEN * 32 - \
732 #define FBNIC_CSR_END_RPC 0x0856b /* CSR section delimiter */
736 #define FBNIC_CSR_START_RPC_RAM 0x08800 /* CSR section delimiter */
774 #define FBNIC_CSR_END_RPC_RAM 0x08f1f /* CSR section delimiter */
777 #define FBNIC_CSR_START_FAB 0x0C000 /* CSR section delimiter */
781 #define FBNIC_CSR_END_FAB 0x0C020 /* CSR section delimiter */
784 #define FBNIC_CSR_START_MASTER 0x0C400 /* CSR section delimiter */
786 #define FBNIC_CSR_END_MASTER 0x0C452 /* CSR section delimiter */
789 #define FBNIC_CSR_START_PCS 0x10000 /* CSR section delimiter */
790 #define FBNIC_CSR_END_PCS 0x10668 /* CSR section delimiter */
792 #define FBNIC_CSR_START_RSFEC 0x10800 /* CSR section delimiter */
793 #define FBNIC_CSR_END_RSFEC 0x108c8 /* CSR section delimiter */
796 #define FBNIC_CSR_START_MAC_MAC 0x11000 /* CSR section delimiter */
808 #define FBNIC_CSR_END_MAC_MAC 0x11028 /* CSR section delimiter */
810 /* Signals from MAC, AN, PCS, and LED CSR registers (ASIC only) */
811 #define FBNIC_CSR_START_SIG 0x11800 /* CSR section delimiter */
829 #define FBNIC_CSR_END_SIG 0x1184e /* CSR section delimiter */
936 #define FBNIC_CSR_START_PCIE_SS_COMPHY 0x2442e /* CSR section delimiter */
937 #define FBNIC_CSR_END_PCIE_SS_COMPHY 0x279d7 /* CSR section delimiter */
940 #define FBNIC_CSR_START_PUL_USER 0x31000 /* CSR section delimiter */
981 #define FBNIC_CSR_END_PUL_USER 0x310ea /* CSR section delimiter */
986 * find the actual register offset it is necessary to combine FBNIC_QUEUE(n)
987 * with the register to get the actual register offset like so:
990 #define FBNIC_CSR_START_QUEUE 0x40000 /* CSR section delimiter */
1131 #define FBNIC_CSR_END_QUEUE (0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1)
1139 * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just
1140 * have to do the math and determine the offset based on the mailbox