Lines Matching +full:primary +full:- +full:bond
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
41 #include <linux/dma-mapping.h>
43 #include <linux/io-mapping.h>
48 #include <uapi/rdma/mlx4-abi.h>
59 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
77 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi…
105 " flow steering when available, set to -1");
149 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
153 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
154 /* Log2 max number of VLANs per ETH port (0-7) */
166 "(0-7) (default: 0)");
179 ctx->val.vbool = !!mlx4_internal_err_reset; in mlx4_devlink_ierr_reset_get()
187 mlx4_internal_err_reset = ctx->val.vbool; in mlx4_devlink_ierr_reset_set()
195 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_crdump_snapshot_get()
197 ctx->val.vbool = dev->persist->crdump.snapshot_enable; in mlx4_devlink_crdump_snapshot_get()
206 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_crdump_snapshot_set()
208 dev->persist->crdump.snapshot_enable = ctx->val.vbool; in mlx4_devlink_crdump_snapshot_set()
220 return -ERANGE; in mlx4_devlink_max_macs_validate()
224 return -EINVAL; in mlx4_devlink_max_macs_validate()
297 dev->caps.reserved_uars = in mlx4_set_num_reserved_uars()
300 dev_cap->reserved_uars / in mlx4_set_num_reserved_uars()
301 (1 << (PAGE_SHIFT - dev->uar_page_shift))); in mlx4_set_num_reserved_uars()
309 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { in mlx4_check_port_params()
310 for (i = 0; i < dev->caps.num_ports - 1; i++) { in mlx4_check_port_params()
313 return -EOPNOTSUPP; in mlx4_check_port_params()
318 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_check_port_params()
319 if (!(port_type[i] & dev->caps.supported_type[i+1])) { in mlx4_check_port_params()
322 return -EOPNOTSUPP; in mlx4_check_port_params()
332 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_set_port_mask()
333 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
345 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_query_func()
351 dev_cap->max_eqs = func.max_eq; in mlx4_query_func()
352 dev_cap->reserved_eqs = func.rsvd_eqs; in mlx4_query_func()
353 dev_cap->reserved_uars = func.rsvd_uars; in mlx4_query_func()
361 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride()
364 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || in mlx4_enable_cqe_eqe_stride()
365 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) in mlx4_enable_cqe_eqe_stride()
371 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || in mlx4_enable_cqe_eqe_stride()
372 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { in mlx4_enable_cqe_eqe_stride()
373 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
374 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
381 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; in mlx4_enable_cqe_eqe_stride()
382 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; in mlx4_enable_cqe_eqe_stride()
385 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
389 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
390 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
397 dev->caps.vl_cap[port] = port_cap->max_vl; in _mlx4_dev_port()
398 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; in _mlx4_dev_port()
399 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; in _mlx4_dev_port()
400 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; in _mlx4_dev_port()
402 * to non-sriov values in _mlx4_dev_port()
404 dev->caps.gid_table_len[port] = port_cap->max_gids; in _mlx4_dev_port()
405 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; in _mlx4_dev_port()
406 dev->caps.port_width_cap[port] = port_cap->max_port_width; in _mlx4_dev_port()
407 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; in _mlx4_dev_port()
408 dev->caps.max_tc_eth = port_cap->max_tc_eth; in _mlx4_dev_port()
409 dev->caps.def_mac[port] = port_cap->def_mac; in _mlx4_dev_port()
410 dev->caps.supported_type[port] = port_cap->supported_port_types; in _mlx4_dev_port()
411 dev->caps.suggested_type[port] = port_cap->suggested_type; in _mlx4_dev_port()
412 dev->caps.default_sense[port] = port_cap->default_sense; in _mlx4_dev_port()
413 dev->caps.trans_type[port] = port_cap->trans_type; in _mlx4_dev_port()
414 dev->caps.vendor_oui[port] = port_cap->vendor_oui; in _mlx4_dev_port()
415 dev->caps.wavelength[port] = port_cap->wavelength; in _mlx4_dev_port()
416 dev->caps.trans_code[port] = port_cap->trans_code; in _mlx4_dev_port()
436 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) in mlx4_enable_ignore_fcs()
440 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); in mlx4_enable_ignore_fcs()
441 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; in mlx4_enable_ignore_fcs()
445 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { in mlx4_enable_ignore_fcs()
447 "Keep FCS is not supported - Disabling Ignore FCS"); in mlx4_enable_ignore_fcs()
448 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; in mlx4_enable_ignore_fcs()
466 if (dev_cap->min_page_sz > PAGE_SIZE) { in mlx4_dev_cap()
468 dev_cap->min_page_sz, PAGE_SIZE); in mlx4_dev_cap()
469 return -ENODEV; in mlx4_dev_cap()
471 if (dev_cap->num_ports > MLX4_MAX_PORTS) { in mlx4_dev_cap()
473 dev_cap->num_ports, MLX4_MAX_PORTS); in mlx4_dev_cap()
474 return -ENODEV; in mlx4_dev_cap()
477 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { in mlx4_dev_cap()
479 dev_cap->uar_size, in mlx4_dev_cap()
481 pci_resource_len(dev->persist->pdev, 2)); in mlx4_dev_cap()
482 return -ENODEV; in mlx4_dev_cap()
485 dev->caps.num_ports = dev_cap->num_ports; in mlx4_dev_cap()
486 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; in mlx4_dev_cap()
487 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? in mlx4_dev_cap()
488 dev->caps.num_sys_eqs : in mlx4_dev_cap()
490 for (i = 1; i <= dev->caps.num_ports; ++i) { in mlx4_dev_cap()
491 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); in mlx4_dev_cap()
498 dev->caps.map_clock_to_user = dev_cap->map_clock_to_user; in mlx4_dev_cap()
499 dev->caps.uar_page_size = PAGE_SIZE; in mlx4_dev_cap()
500 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; in mlx4_dev_cap()
501 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; in mlx4_dev_cap()
502 dev->caps.bf_reg_size = dev_cap->bf_reg_size; in mlx4_dev_cap()
503 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; in mlx4_dev_cap()
504 dev->caps.max_sq_sg = dev_cap->max_sq_sg; in mlx4_dev_cap()
505 dev->caps.max_rq_sg = dev_cap->max_rq_sg; in mlx4_dev_cap()
506 dev->caps.max_wqes = dev_cap->max_qp_sz; in mlx4_dev_cap()
507 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; in mlx4_dev_cap()
508 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; in mlx4_dev_cap()
509 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; in mlx4_dev_cap()
510 dev->caps.reserved_srqs = dev_cap->reserved_srqs; in mlx4_dev_cap()
511 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; in mlx4_dev_cap()
512 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; in mlx4_dev_cap()
517 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; in mlx4_dev_cap()
518 dev->caps.reserved_cqs = dev_cap->reserved_cqs; in mlx4_dev_cap()
519 dev->caps.reserved_eqs = dev_cap->reserved_eqs; in mlx4_dev_cap()
520 dev->caps.reserved_mtts = dev_cap->reserved_mtts; in mlx4_dev_cap()
521 dev->caps.reserved_mrws = dev_cap->reserved_mrws; in mlx4_dev_cap()
523 dev->caps.reserved_pds = dev_cap->reserved_pds; in mlx4_dev_cap()
524 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? in mlx4_dev_cap()
525 dev_cap->reserved_xrcds : 0; in mlx4_dev_cap()
526 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? in mlx4_dev_cap()
527 dev_cap->max_xrcds : 0; in mlx4_dev_cap()
528 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; in mlx4_dev_cap()
530 dev->caps.max_msg_sz = dev_cap->max_msg_sz; in mlx4_dev_cap()
531 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); in mlx4_dev_cap()
532 dev->caps.flags = dev_cap->flags; in mlx4_dev_cap()
533 dev->caps.flags2 = dev_cap->flags2; in mlx4_dev_cap()
534 dev->caps.bmme_flags = dev_cap->bmme_flags; in mlx4_dev_cap()
535 dev->caps.reserved_lkey = dev_cap->reserved_lkey; in mlx4_dev_cap()
536 dev->caps.stat_rate_support = dev_cap->stat_rate_support; in mlx4_dev_cap()
537 dev->caps.max_gso_sz = dev_cap->max_gso_sz; in mlx4_dev_cap()
538 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; in mlx4_dev_cap()
539 dev->caps.wol_port[1] = dev_cap->wol_port[1]; in mlx4_dev_cap()
540 dev->caps.wol_port[2] = dev_cap->wol_port[2]; in mlx4_dev_cap()
541 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs; in mlx4_dev_cap()
548 if (enable_4k_uar || !dev->persist->num_vfs) in mlx4_dev_cap()
549 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; in mlx4_dev_cap()
551 dev->uar_page_shift = PAGE_SHIFT; in mlx4_dev_cap()
556 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { in mlx4_dev_cap()
568 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; in mlx4_dev_cap()
571 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ in mlx4_dev_cap()
572 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) in mlx4_dev_cap()
573 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; in mlx4_dev_cap()
576 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; in mlx4_dev_cap()
579 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; in mlx4_dev_cap()
580 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; in mlx4_dev_cap()
582 dev->caps.log_num_macs = log_num_mac; in mlx4_dev_cap()
583 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; in mlx4_dev_cap()
586 for (i = 1; i <= dev->caps.num_ports; ++i) { in mlx4_dev_cap()
587 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; in mlx4_dev_cap()
588 if (dev->caps.supported_type[i]) { in mlx4_dev_cap()
589 /* if only ETH is supported - assign ETH */ in mlx4_dev_cap()
590 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) in mlx4_dev_cap()
591 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; in mlx4_dev_cap()
593 else if (dev->caps.supported_type[i] == in mlx4_dev_cap()
595 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; in mlx4_dev_cap()
600 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) in mlx4_dev_cap()
601 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? in mlx4_dev_cap()
604 dev->caps.port_type[i] = port_type_array[i - 1]; in mlx4_dev_cap()
613 mlx4_priv(dev)->sense.sense_allowed[i] = in mlx4_dev_cap()
614 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && in mlx4_dev_cap()
615 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && in mlx4_dev_cap()
616 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); in mlx4_dev_cap()
623 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { in mlx4_dev_cap()
625 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; in mlx4_dev_cap()
628 dev->caps.port_type[i] = sensed_port; in mlx4_dev_cap()
630 dev->caps.possible_type[i] = dev->caps.port_type[i]; in mlx4_dev_cap()
633 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { in mlx4_dev_cap()
634 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; in mlx4_dev_cap()
636 i, 1 << dev->caps.log_num_macs); in mlx4_dev_cap()
638 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { in mlx4_dev_cap()
639 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; in mlx4_dev_cap()
641 i, 1 << dev->caps.log_num_vlans); in mlx4_dev_cap()
645 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && in mlx4_dev_cap()
650 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; in mlx4_dev_cap()
653 dev->caps.max_counters = dev_cap->max_counters; in mlx4_dev_cap()
655 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; in mlx4_dev_cap()
656 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = in mlx4_dev_cap()
657 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = in mlx4_dev_cap()
658 (1 << dev->caps.log_num_macs) * in mlx4_dev_cap()
659 (1 << dev->caps.log_num_vlans) * in mlx4_dev_cap()
660 dev->caps.num_ports; in mlx4_dev_cap()
661 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; in mlx4_dev_cap()
663 if (dev_cap->dmfs_high_rate_qpn_base > 0 && in mlx4_dev_cap()
664 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) in mlx4_dev_cap()
665 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; in mlx4_dev_cap()
667 dev->caps.dmfs_high_rate_qpn_base = in mlx4_dev_cap()
668 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; in mlx4_dev_cap()
670 if (dev_cap->dmfs_high_rate_qpn_range > 0 && in mlx4_dev_cap()
671 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { in mlx4_dev_cap()
672 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; in mlx4_dev_cap()
673 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; in mlx4_dev_cap()
674 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; in mlx4_dev_cap()
676 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; in mlx4_dev_cap()
677 dev->caps.dmfs_high_rate_qpn_base = in mlx4_dev_cap()
678 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; in mlx4_dev_cap()
679 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; in mlx4_dev_cap()
682 dev->caps.rl_caps = dev_cap->rl_caps; in mlx4_dev_cap()
684 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = in mlx4_dev_cap()
685 dev->caps.dmfs_high_rate_qpn_range; in mlx4_dev_cap()
687 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + in mlx4_dev_cap()
688 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + in mlx4_dev_cap()
689 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + in mlx4_dev_cap()
690 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; in mlx4_dev_cap()
692 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; in mlx4_dev_cap()
695 if (dev_cap->flags & in mlx4_dev_cap()
698 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; in mlx4_dev_cap()
699 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; in mlx4_dev_cap()
702 if (dev_cap->flags2 & in mlx4_dev_cap()
706 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; in mlx4_dev_cap()
707 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; in mlx4_dev_cap()
711 if ((dev->caps.flags & in mlx4_dev_cap()
714 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; in mlx4_dev_cap()
718 dev->caps.alloc_res_qp_mask = in mlx4_dev_cap()
719 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | in mlx4_dev_cap()
722 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && in mlx4_dev_cap()
723 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { in mlx4_dev_cap()
726 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; in mlx4_dev_cap()
730 dev->caps.alloc_res_qp_mask = 0; in mlx4_dev_cap()
746 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { in mlx4_how_many_lives_vf()
747 s_state = &priv->mfunc.master.slave_state[i]; in mlx4_how_many_lives_vf()
748 if (s_state->active && s_state->last_cmd != in mlx4_how_many_lives_vf()
762 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || in mlx4_get_parav_qkey()
763 qpn < dev->phys_caps.base_proxy_sqpn) in mlx4_get_parav_qkey()
764 return -EINVAL; in mlx4_get_parav_qkey()
766 if (qpn >= dev->phys_caps.base_tunnel_sqpn) in mlx4_get_parav_qkey()
768 qk += qpn - dev->phys_caps.base_tunnel_sqpn; in mlx4_get_parav_qkey()
770 qk += qpn - dev->phys_caps.base_proxy_sqpn; in mlx4_get_parav_qkey()
783 priv->virt2phys_pkey[slave][port - 1][i] = val; in mlx4_sync_pkey_table()
794 priv->slave_node_guids[slave] = guid; in mlx4_put_slave_node_guid()
805 return priv->slave_node_guids[slave]; in mlx4_get_slave_node_guid()
817 s_slave = &priv->mfunc.master.slave_state[slave]; in mlx4_is_slave_active()
818 return !!s_slave->active; in mlx4_is_slave_active()
825 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || in mlx4_handle_eth_header_mcast_prio()
826 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { in mlx4_handle_eth_header_mcast_prio()
830 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && in mlx4_handle_eth_header_mcast_prio()
831 next_rule->rsvd == 0; in mlx4_handle_eth_header_mcast_prio()
834 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); in mlx4_handle_eth_header_mcast_prio()
843 dev->caps.steering_mode = hca_param->steering_mode; in slave_adjust_steering_mode()
844 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { in slave_adjust_steering_mode()
845 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; in slave_adjust_steering_mode()
846 dev->caps.fs_log_max_ucast_qp_range_size = in slave_adjust_steering_mode()
847 dev_cap->fs_log_max_ucast_qp_range_size; in slave_adjust_steering_mode()
849 dev->caps.num_qp_per_mgm = in slave_adjust_steering_mode()
850 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); in slave_adjust_steering_mode()
853 mlx4_steering_mode_str(dev->caps.steering_mode)); in slave_adjust_steering_mode()
858 kfree(dev->caps.spec_qps); in mlx4_slave_destroy_special_qp_cap()
859 dev->caps.spec_qps = NULL; in mlx4_slave_destroy_special_qp_cap()
865 struct mlx4_caps *caps = &dev->caps; in mlx4_slave_special_qp_cap()
869 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); in mlx4_slave_special_qp_cap()
871 if (!func_cap || !caps->spec_qps) { in mlx4_slave_special_qp_cap()
873 err = -ENOMEM; in mlx4_slave_special_qp_cap()
877 for (i = 1; i <= caps->num_ports; ++i) { in mlx4_slave_special_qp_cap()
884 caps->spec_qps[i - 1] = func_cap->spec_qps; in mlx4_slave_special_qp_cap()
885 caps->port_mask[i] = caps->port_type[i]; in mlx4_slave_special_qp_cap()
886 caps->phys_port_id[i] = func_cap->phys_port_id; in mlx4_slave_special_qp_cap()
888 &caps->gid_table_len[i], in mlx4_slave_special_qp_cap()
889 &caps->pkey_table_len[i]); in mlx4_slave_special_qp_cap()
917 err = -ENOMEM; in mlx4_slave_cap()
930 if (hca_param->global_caps) { in mlx4_slave_cap()
932 err = -EINVAL; in mlx4_slave_cap()
936 dev->caps.hca_core_clock = hca_param->hca_core_clock; in mlx4_slave_cap()
938 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; in mlx4_slave_cap()
949 page_size = ~dev->caps.page_size_cap + 1; in mlx4_slave_cap()
954 err = -ENODEV; in mlx4_slave_cap()
959 dev->uar_page_shift = hca_param->uar_page_sz + 12; in mlx4_slave_cap()
962 if (dev->uar_page_shift > PAGE_SHIFT) { in mlx4_slave_cap()
965 err = -ENODEV; in mlx4_slave_cap()
976 dev->caps.uar_page_size = PAGE_SIZE; in mlx4_slave_cap()
985 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != in mlx4_slave_cap()
988 func_cap->pf_context_behaviour, in mlx4_slave_cap()
990 err = -EINVAL; in mlx4_slave_cap()
994 dev->caps.num_ports = func_cap->num_ports; in mlx4_slave_cap()
995 dev->quotas.qp = func_cap->qp_quota; in mlx4_slave_cap()
996 dev->quotas.srq = func_cap->srq_quota; in mlx4_slave_cap()
997 dev->quotas.cq = func_cap->cq_quota; in mlx4_slave_cap()
998 dev->quotas.mpt = func_cap->mpt_quota; in mlx4_slave_cap()
999 dev->quotas.mtt = func_cap->mtt_quota; in mlx4_slave_cap()
1000 dev->caps.num_qps = 1 << hca_param->log_num_qps; in mlx4_slave_cap()
1001 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; in mlx4_slave_cap()
1002 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; in mlx4_slave_cap()
1003 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; in mlx4_slave_cap()
1004 dev->caps.num_eqs = func_cap->max_eq; in mlx4_slave_cap()
1005 dev->caps.reserved_eqs = func_cap->reserved_eq; in mlx4_slave_cap()
1006 dev->caps.reserved_lkey = func_cap->reserved_lkey; in mlx4_slave_cap()
1007 dev->caps.num_pds = MLX4_NUM_PDS; in mlx4_slave_cap()
1008 dev->caps.num_mgms = 0; in mlx4_slave_cap()
1009 dev->caps.num_amgms = 0; in mlx4_slave_cap()
1011 if (dev->caps.num_ports > MLX4_MAX_PORTS) { in mlx4_slave_cap()
1013 dev->caps.num_ports, MLX4_MAX_PORTS); in mlx4_slave_cap()
1014 err = -ENODEV; in mlx4_slave_cap()
1026 if (dev->caps.uar_page_size * (dev->caps.num_uars - in mlx4_slave_cap()
1027 dev->caps.reserved_uars) > in mlx4_slave_cap()
1028 pci_resource_len(dev->persist->pdev, in mlx4_slave_cap()
1031 dev->caps.uar_page_size * dev->caps.num_uars, in mlx4_slave_cap()
1033 pci_resource_len(dev->persist->pdev, 2)); in mlx4_slave_cap()
1034 err = -ENOMEM; in mlx4_slave_cap()
1038 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { in mlx4_slave_cap()
1039 dev->caps.eqe_size = 64; in mlx4_slave_cap()
1040 dev->caps.eqe_factor = 1; in mlx4_slave_cap()
1042 dev->caps.eqe_size = 32; in mlx4_slave_cap()
1043 dev->caps.eqe_factor = 0; in mlx4_slave_cap()
1046 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { in mlx4_slave_cap()
1047 dev->caps.cqe_size = 64; in mlx4_slave_cap()
1048 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; in mlx4_slave_cap()
1050 dev->caps.cqe_size = 32; in mlx4_slave_cap()
1053 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { in mlx4_slave_cap()
1054 dev->caps.eqe_size = hca_param->eqe_size; in mlx4_slave_cap()
1055 dev->caps.eqe_factor = 0; in mlx4_slave_cap()
1058 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { in mlx4_slave_cap()
1059 dev->caps.cqe_size = hca_param->cqe_size; in mlx4_slave_cap()
1061 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; in mlx4_slave_cap()
1064 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; in mlx4_slave_cap()
1067 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN; in mlx4_slave_cap()
1072 hca_param->rss_ip_frags ? "on" : "off"); in mlx4_slave_cap()
1074 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && in mlx4_slave_cap()
1075 dev->caps.bf_reg_size) in mlx4_slave_cap()
1076 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; in mlx4_slave_cap()
1078 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) in mlx4_slave_cap()
1079 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; in mlx4_slave_cap()
1102 for (port = 0; port < dev->caps.num_ports; port++) { in mlx4_change_port_types()
1105 if (port_types[port] != dev->caps.port_type[port + 1]) in mlx4_change_port_types()
1110 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_change_port_types()
1112 dev->caps.port_type[port] = port_types[port - 1]; in mlx4_change_port_types()
1113 err = mlx4_SET_PORT(dev, port, -1); in mlx4_change_port_types()
1138 struct mlx4_dev *mdev = info->dev; in show_port_type()
1142 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? in show_port_type()
1144 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) in show_port_type()
1155 struct mlx4_dev *mdev = info->dev; in __set_port_type()
1162 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { in __set_port_type()
1165 info->port); in __set_port_type()
1166 return -EOPNOTSUPP; in __set_port_type()
1170 mutex_lock(&priv->port_mutex); in __set_port_type()
1171 info->tmp_type = port_type; in __set_port_type()
1174 mdev->caps.possible_type[info->port] = info->tmp_type; in __set_port_type()
1176 for (i = 0; i < mdev->caps.num_ports; i++) { in __set_port_type()
1177 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : in __set_port_type()
1178 mdev->caps.possible_type[i+1]; in __set_port_type()
1180 types[i] = mdev->caps.port_type[i+1]; in __set_port_type()
1183 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && in __set_port_type()
1184 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { in __set_port_type()
1185 for (i = 1; i <= mdev->caps.num_ports; i++) { in __set_port_type()
1186 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { in __set_port_type()
1187 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; in __set_port_type()
1188 err = -EOPNOTSUPP; in __set_port_type()
1206 for (i = 0; i < mdev->caps.num_ports; i++) in __set_port_type()
1207 priv->port[i + 1].tmp_type = 0; in __set_port_type()
1213 mutex_unlock(&priv->port_mutex); in __set_port_type()
1224 struct mlx4_dev *mdev = info->dev; in set_port_type()
1239 err = -EINVAL; in set_port_type()
1259 default: return -1; in int_to_ibta_mtu()
1271 default: return -1; in ibta_mtu_to_int()
1281 struct mlx4_dev *mdev = info->dev; in show_port_ib_mtu()
1283 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) in show_port_ib_mtu()
1287 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); in show_port_ib_mtu()
1297 struct mlx4_dev *mdev = info->dev; in set_port_ib_mtu()
1299 int err, port, mtu, ibta_mtu = -1; in set_port_ib_mtu()
1301 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { in set_port_ib_mtu()
1303 return -EINVAL; in set_port_ib_mtu()
1312 return -EINVAL; in set_port_ib_mtu()
1315 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; in set_port_ib_mtu()
1318 mutex_lock(&priv->port_mutex); in set_port_ib_mtu()
1320 for (port = 1; port <= mdev->caps.num_ports; port++) { in set_port_ib_mtu()
1322 err = mlx4_SET_PORT(mdev, port, -1); in set_port_ib_mtu()
1331 mutex_unlock(&priv->port_mutex); in set_port_ib_mtu()
1336 /* bond for multi-function device */
1350 dev->persist->num_vfs + 1) > 1) { in mlx4_mf_bond()
1352 return -EINVAL; in mlx4_mf_bond()
1358 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + in mlx4_mf_bond()
1359 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; in mlx4_mf_bond()
1365 return -EINVAL; in mlx4_mf_bond()
1368 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { in mlx4_mf_bond()
1370 return -EINVAL; in mlx4_mf_bond()
1416 mutex_lock(&priv->bond_mutex); in mlx4_bond()
1421 mlx4_err(dev, "Failed to bond device: %d\n", ret); in mlx4_bond()
1425 mlx4_err(dev, "bond for multifunction failed\n"); in mlx4_bond()
1431 mutex_unlock(&priv->bond_mutex); in mlx4_bond()
1443 mutex_lock(&priv->bond_mutex); in mlx4_unbond()
1459 mutex_unlock(&priv->bond_mutex); in mlx4_unbond()
1468 u8 port1 = v2p->port1; in mlx4_port_map_set()
1469 u8 port2 = v2p->port2; in mlx4_port_map_set()
1473 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) in mlx4_port_map_set()
1474 return -EOPNOTSUPP; in mlx4_port_map_set()
1476 mutex_lock(&priv->bond_mutex); in mlx4_port_map_set()
1480 port1 = priv->v2p.port1; in mlx4_port_map_set()
1482 port2 = priv->v2p.port2; in mlx4_port_map_set()
1489 err = -EINVAL; in mlx4_port_map_set()
1490 } else if ((port1 == priv->v2p.port1) && in mlx4_port_map_set()
1491 (port2 == priv->v2p.port2)) { in mlx4_port_map_set()
1498 priv->v2p.port1 = port1; in mlx4_port_map_set()
1499 priv->v2p.port2 = port2; in mlx4_port_map_set()
1505 mutex_unlock(&priv->bond_mutex); in mlx4_port_map_set()
1518 struct mlx4_bond *bond = container_of(work, struct mlx4_bond, work); in mlx4_bond_work() local
1521 if (bond->is_bonded) { in mlx4_bond_work()
1522 if (!mlx4_is_bonded(bond->dev)) { in mlx4_bond_work()
1523 err = mlx4_bond(bond->dev); in mlx4_bond_work()
1525 mlx4_err(bond->dev, "Fail to bond device\n"); in mlx4_bond_work()
1528 err = mlx4_port_map_set(bond->dev, &bond->port_map); in mlx4_bond_work()
1530 mlx4_err(bond->dev, in mlx4_bond_work()
1532 bond->port_map.port1, in mlx4_bond_work()
1533 bond->port_map.port2, err); in mlx4_bond_work()
1535 } else if (mlx4_is_bonded(bond->dev)) { in mlx4_bond_work()
1536 err = mlx4_unbond(bond->dev); in mlx4_bond_work()
1538 mlx4_err(bond->dev, "Fail to unbond device\n"); in mlx4_bond_work()
1540 put_device(&bond->dev->persist->pdev->dev); in mlx4_bond_work()
1541 kfree(bond); in mlx4_bond_work()
1547 struct mlx4_bond *bond; in mlx4_queue_bond_work() local
1549 bond = kzalloc(sizeof(*bond), GFP_ATOMIC); in mlx4_queue_bond_work()
1550 if (!bond) in mlx4_queue_bond_work()
1551 return -ENOMEM; in mlx4_queue_bond_work()
1553 INIT_WORK(&bond->work, mlx4_bond_work); in mlx4_queue_bond_work()
1554 get_device(&dev->persist->pdev->dev); in mlx4_queue_bond_work()
1555 bond->dev = dev; in mlx4_queue_bond_work()
1556 bond->is_bonded = is_bonded; in mlx4_queue_bond_work()
1557 bond->port_map.port1 = v2p_p1; in mlx4_queue_bond_work()
1558 bond->port_map.port2 = v2p_p2; in mlx4_queue_bond_work()
1559 queue_work(mlx4_wq, &bond->work); in mlx4_queue_bond_work()
1569 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, in mlx4_load_fw()
1571 if (!priv->fw.fw_icm) { in mlx4_load_fw()
1573 return -ENOMEM; in mlx4_load_fw()
1576 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); in mlx4_load_fw()
1594 mlx4_free_icm(dev, priv->fw.fw_icm, 0); in mlx4_load_fw()
1605 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, in mlx4_init_cmpt_table()
1609 cmpt_entry_sz, dev->caps.num_qps, in mlx4_init_cmpt_table()
1610 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_cmpt_table()
1615 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, in mlx4_init_cmpt_table()
1619 cmpt_entry_sz, dev->caps.num_srqs, in mlx4_init_cmpt_table()
1620 dev->caps.reserved_srqs, 0, 0); in mlx4_init_cmpt_table()
1624 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, in mlx4_init_cmpt_table()
1628 cmpt_entry_sz, dev->caps.num_cqs, in mlx4_init_cmpt_table()
1629 dev->caps.reserved_cqs, 0, 0); in mlx4_init_cmpt_table()
1633 num_eqs = dev->phys_caps.num_phys_eqs; in mlx4_init_cmpt_table()
1634 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, in mlx4_init_cmpt_table()
1645 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); in mlx4_init_cmpt_table()
1648 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); in mlx4_init_cmpt_table()
1651 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); in mlx4_init_cmpt_table()
1675 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, in mlx4_init_icm()
1677 if (!priv->fw.aux_icm) { in mlx4_init_icm()
1679 return -ENOMEM; in mlx4_init_icm()
1682 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); in mlx4_init_icm()
1688 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); in mlx4_init_icm()
1695 num_eqs = dev->phys_caps.num_phys_eqs; in mlx4_init_icm()
1696 err = mlx4_init_icm_table(dev, &priv->eq_table.table, in mlx4_init_icm()
1697 init_hca->eqc_base, dev_cap->eqc_entry_sz, in mlx4_init_icm()
1708 * dev->caps.mtt_entry_sz below is really the MTT segment in mlx4_init_icm()
1711 dev->caps.reserved_mtts = in mlx4_init_icm()
1712 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, in mlx4_init_icm()
1713 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; in mlx4_init_icm()
1715 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, in mlx4_init_icm()
1716 init_hca->mtt_base, in mlx4_init_icm()
1717 dev->caps.mtt_entry_sz, in mlx4_init_icm()
1718 dev->caps.num_mtts, in mlx4_init_icm()
1719 dev->caps.reserved_mtts, 1, 0); in mlx4_init_icm()
1725 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, in mlx4_init_icm()
1726 init_hca->dmpt_base, in mlx4_init_icm()
1727 dev_cap->dmpt_entry_sz, in mlx4_init_icm()
1728 dev->caps.num_mpts, in mlx4_init_icm()
1729 dev->caps.reserved_mrws, 1, 1); in mlx4_init_icm()
1735 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, in mlx4_init_icm()
1736 init_hca->qpc_base, in mlx4_init_icm()
1737 dev_cap->qpc_entry_sz, in mlx4_init_icm()
1738 dev->caps.num_qps, in mlx4_init_icm()
1739 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_icm()
1746 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, in mlx4_init_icm()
1747 init_hca->auxc_base, in mlx4_init_icm()
1748 dev_cap->aux_entry_sz, in mlx4_init_icm()
1749 dev->caps.num_qps, in mlx4_init_icm()
1750 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_icm()
1757 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, in mlx4_init_icm()
1758 init_hca->altc_base, in mlx4_init_icm()
1759 dev_cap->altc_entry_sz, in mlx4_init_icm()
1760 dev->caps.num_qps, in mlx4_init_icm()
1761 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_icm()
1768 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, in mlx4_init_icm()
1769 init_hca->rdmarc_base, in mlx4_init_icm()
1770 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, in mlx4_init_icm()
1771 dev->caps.num_qps, in mlx4_init_icm()
1772 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_icm()
1779 err = mlx4_init_icm_table(dev, &priv->cq_table.table, in mlx4_init_icm()
1780 init_hca->cqc_base, in mlx4_init_icm()
1781 dev_cap->cqc_entry_sz, in mlx4_init_icm()
1782 dev->caps.num_cqs, in mlx4_init_icm()
1783 dev->caps.reserved_cqs, 0, 0); in mlx4_init_icm()
1789 err = mlx4_init_icm_table(dev, &priv->srq_table.table, in mlx4_init_icm()
1790 init_hca->srqc_base, in mlx4_init_icm()
1791 dev_cap->srq_entry_sz, in mlx4_init_icm()
1792 dev->caps.num_srqs, in mlx4_init_icm()
1793 dev->caps.reserved_srqs, 0, 0); in mlx4_init_icm()
1806 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, in mlx4_init_icm()
1807 init_hca->mc_base, in mlx4_init_icm()
1809 dev->caps.num_mgms + dev->caps.num_amgms, in mlx4_init_icm()
1810 dev->caps.num_mgms + dev->caps.num_amgms, in mlx4_init_icm()
1820 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); in mlx4_init_icm()
1823 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); in mlx4_init_icm()
1826 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); in mlx4_init_icm()
1829 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); in mlx4_init_icm()
1832 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); in mlx4_init_icm()
1835 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); in mlx4_init_icm()
1838 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); in mlx4_init_icm()
1841 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); in mlx4_init_icm()
1844 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); in mlx4_init_icm()
1847 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); in mlx4_init_icm()
1848 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); in mlx4_init_icm()
1849 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); in mlx4_init_icm()
1850 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); in mlx4_init_icm()
1856 mlx4_free_icm(dev, priv->fw.aux_icm, 0); in mlx4_init_icm()
1865 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); in mlx4_free_icms()
1866 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); in mlx4_free_icms()
1867 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); in mlx4_free_icms()
1868 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); in mlx4_free_icms()
1869 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); in mlx4_free_icms()
1870 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); in mlx4_free_icms()
1871 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); in mlx4_free_icms()
1872 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); in mlx4_free_icms()
1873 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); in mlx4_free_icms()
1874 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); in mlx4_free_icms()
1875 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); in mlx4_free_icms()
1876 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); in mlx4_free_icms()
1877 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); in mlx4_free_icms()
1878 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); in mlx4_free_icms()
1881 mlx4_free_icm(dev, priv->fw.aux_icm, 0); in mlx4_free_icms()
1888 mutex_lock(&priv->cmd.slave_cmd_mutex); in mlx4_slave_exit()
1892 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_slave_exit()
1902 if (!dev->caps.bf_reg_size) in map_bf_area()
1903 return -ENXIO; in map_bf_area()
1905 bf_start = pci_resource_start(dev->persist->pdev, 2) + in map_bf_area()
1906 (dev->caps.num_uars << PAGE_SHIFT); in map_bf_area()
1907 bf_len = pci_resource_len(dev->persist->pdev, 2) - in map_bf_area()
1908 (dev->caps.num_uars << PAGE_SHIFT); in map_bf_area()
1909 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); in map_bf_area()
1910 if (!priv->bf_mapping) in map_bf_area()
1911 err = -ENOMEM; in map_bf_area()
1918 if (mlx4_priv(dev)->bf_mapping) in unmap_bf_area()
1919 io_mapping_free(mlx4_priv(dev)->bf_mapping); in unmap_bf_area()
1930 clockhi = swab32(readl(priv->clock_mapping)); in mlx4_read_clock()
1931 clocklo = swab32(readl(priv->clock_mapping + 4)); in mlx4_read_clock()
1932 clockhi1 = swab32(readl(priv->clock_mapping)); in mlx4_read_clock()
1948 priv->clock_mapping = in map_internal_clock()
1949 ioremap(pci_resource_start(dev->persist->pdev, in map_internal_clock()
1950 priv->fw.clock_bar) + in map_internal_clock()
1951 priv->fw.clock_offset, MLX4_CLOCK_SIZE); in map_internal_clock()
1953 if (!priv->clock_mapping) in map_internal_clock()
1954 return -ENOMEM; in map_internal_clock()
1965 return -EOPNOTSUPP; in mlx4_get_internal_clock_params()
1967 if (!dev->caps.map_clock_to_user) { in mlx4_get_internal_clock_params()
1969 return -EOPNOTSUPP; in mlx4_get_internal_clock_params()
1973 return -EINVAL; in mlx4_get_internal_clock_params()
1975 params->bar = priv->fw.clock_bar; in mlx4_get_internal_clock_params()
1976 params->offset = priv->fw.clock_offset; in mlx4_get_internal_clock_params()
1977 params->size = MLX4_CLOCK_SIZE; in mlx4_get_internal_clock_params()
1987 if (priv->clock_mapping) in unmap_internal_clock()
1988 iounmap(priv->clock_mapping); in unmap_internal_clock()
2007 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); in mlx4_close_fw()
2022 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + in mlx4_comm_check_offline()
2032 if (dev->persist->interface_state & in mlx4_comm_check_offline()
2044 return -EIO; in mlx4_comm_check_offline()
2055 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + in mlx4_reset_vf_support()
2060 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; in mlx4_reset_vf_support()
2066 u64 dma = (u64) priv->mfunc.vhcr_dma; in mlx4_init_slave()
2072 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); in mlx4_init_slave()
2073 return -EPROBE_DEFER; in mlx4_init_slave()
2076 mutex_lock(&priv->cmd.slave_cmd_mutex); in mlx4_init_slave()
2077 priv->cmd.max_cmds = 1; in mlx4_init_slave()
2091 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); in mlx4_init_slave()
2092 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_init_slave()
2093 return -EPROBE_DEFER; in mlx4_init_slave()
2098 /* check the driver version - the slave I/F revision in mlx4_init_slave()
2100 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); in mlx4_init_slave()
2123 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_init_slave()
2129 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_init_slave()
2130 return -EIO; in mlx4_init_slave()
2137 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_parav_master_pf_caps()
2138 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) in mlx4_parav_master_pf_caps()
2139 dev->caps.gid_table_len[i] = in mlx4_parav_master_pf_caps()
2142 dev->caps.gid_table_len[i] = 1; in mlx4_parav_master_pf_caps()
2143 dev->caps.pkey_table_len[i] = in mlx4_parav_master_pf_caps()
2144 dev->phys_caps.pkey_phys_table_len[i] - 1; in mlx4_parav_master_pf_caps()
2154 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) in choose_log_fs_mgm_entry_size()
2158 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; in choose_log_fs_mgm_entry_size()
2190 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { in choose_steering_mode()
2191 if (dev->caps.dmfs_high_steer_mode == in choose_steering_mode()
2195 dev->caps.dmfs_high_steer_mode = in choose_steering_mode()
2201 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && in choose_steering_mode()
2203 (dev_cap->fs_max_num_qp_per_entry >= in choose_steering_mode()
2204 (dev->persist->num_vfs + 1))) && in choose_steering_mode()
2205 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= in choose_steering_mode()
2207 dev->oper_log_mgm_entry_size = in choose_steering_mode()
2208 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); in choose_steering_mode()
2209 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; in choose_steering_mode()
2210 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; in choose_steering_mode()
2211 dev->caps.fs_log_max_ucast_qp_range_size = in choose_steering_mode()
2212 dev_cap->fs_log_max_ucast_qp_range_size; in choose_steering_mode()
2214 if (dev->caps.dmfs_high_steer_mode != in choose_steering_mode()
2216 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; in choose_steering_mode()
2217 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && in choose_steering_mode()
2218 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) in choose_steering_mode()
2219 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; in choose_steering_mode()
2221 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; in choose_steering_mode()
2223 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || in choose_steering_mode()
2224 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) in choose_steering_mode()
2225 …mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back t… in choose_steering_mode()
2227 dev->oper_log_mgm_entry_size = in choose_steering_mode()
2231 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); in choose_steering_mode()
2234 mlx4_steering_mode_str(dev->caps.steering_mode), in choose_steering_mode()
2235 dev->oper_log_mgm_entry_size, in choose_steering_mode()
2242 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && in choose_tunnel_offload_mode()
2243 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) in choose_tunnel_offload_mode()
2244 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; in choose_tunnel_offload_mode()
2246 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; in choose_tunnel_offload_mode()
2248 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode in choose_tunnel_offload_mode()
2257 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) in mlx4_validate_optimized_steering()
2258 return -EINVAL; in mlx4_validate_optimized_steering()
2260 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_validate_optimized_steering()
2264 } else if ((dev->caps.dmfs_high_steer_mode != in mlx4_validate_optimized_steering()
2267 !!(dev->caps.dmfs_high_steer_mode == in mlx4_validate_optimized_steering()
2272 dev->caps.dmfs_high_steer_mode), in mlx4_validate_optimized_steering()
2289 if (err == -EACCES) in mlx4_init_fw()
2290 mlx4_info(dev, "non-primary physical function, skipping\n"); in mlx4_init_fw()
2328 err = -ENOMEM; in mlx4_init_hca()
2341 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && in mlx4_init_hca()
2343 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; in mlx4_init_hca()
2358 if (dev->caps.steering_mode == in mlx4_init_hca()
2369 if (enable_4k_uar || !dev->persist->num_vfs) { in mlx4_init_hca()
2370 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) + in mlx4_init_hca()
2371 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; in mlx4_init_hca()
2372 init_hca->uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; in mlx4_init_hca()
2374 init_hca->log_uar_sz = ilog2(dev->caps.num_uars); in mlx4_init_hca()
2375 init_hca->uar_page_sz = PAGE_SHIFT - 12; in mlx4_init_hca()
2378 init_hca->mw_enabled = 0; in mlx4_init_hca()
2379 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || in mlx4_init_hca()
2380 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) in mlx4_init_hca()
2381 init_hca->mw_enabled = INIT_HCA_TPT_MW_ENABLE; in mlx4_init_hca()
2393 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_init_hca()
2399 dev->caps.num_eqs = dev_cap->max_eqs; in mlx4_init_hca()
2400 dev->caps.reserved_eqs = dev_cap->reserved_eqs; in mlx4_init_hca()
2401 dev->caps.reserved_uars = dev_cap->reserved_uars; in mlx4_init_hca()
2409 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { in mlx4_init_hca()
2413 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; in mlx4_init_hca()
2415 dev->caps.hca_core_clock = in mlx4_init_hca()
2416 init_hca->hca_core_clock; in mlx4_init_hca()
2419 /* In case we got HCA frequency 0 - disable timestamping in mlx4_init_hca()
2422 if (!dev->caps.hca_core_clock) { in mlx4_init_hca()
2423 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; in mlx4_init_hca()
2425 "HCA frequency is 0 - timestamping is not supported\n"); in mlx4_init_hca()
2431 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; in mlx4_init_hca()
2436 if (dev->caps.dmfs_high_steer_mode != in mlx4_init_hca()
2441 if (dev->caps.dmfs_high_steer_mode == in mlx4_init_hca()
2443 dev->caps.dmfs_high_rate_qpn_base = in mlx4_init_hca()
2444 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; in mlx4_init_hca()
2445 dev->caps.dmfs_high_rate_qpn_range = in mlx4_init_hca()
2451 dev->caps.dmfs_high_steer_mode)); in mlx4_init_hca()
2456 if (err != -EPROBE_DEFER) in mlx4_init_hca()
2483 if (err && err != -EOPNOTSUPP) { in mlx4_init_hca()
2486 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; in mlx4_init_hca()
2487 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; in mlx4_init_hca()
2489 priv->eq_table.inta_pin = adapter.inta_pin; in mlx4_init_hca()
2490 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); in mlx4_init_hca()
2524 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) in mlx4_init_counters_table()
2525 return -ENOENT; in mlx4_init_counters_table()
2527 if (!dev->caps.max_counters) in mlx4_init_counters_table()
2528 return -ENOSPC; in mlx4_init_counters_table()
2530 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); in mlx4_init_counters_table()
2532 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, in mlx4_init_counters_table()
2533 nent_pow2 - 1, 0, in mlx4_init_counters_table()
2534 nent_pow2 - dev->caps.max_counters + 1); in mlx4_init_counters_table()
2539 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) in mlx4_cleanup_counters_table()
2542 if (!dev->caps.max_counters) in mlx4_cleanup_counters_table()
2545 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); in mlx4_cleanup_counters_table()
2553 for (port = 0; port < dev->caps.num_ports; port++) in mlx4_cleanup_default_counters()
2554 if (priv->def_counter[port] != -1) in mlx4_cleanup_default_counters()
2555 mlx4_counter_free(dev, priv->def_counter[port]); in mlx4_cleanup_default_counters()
2564 for (port = 0; port < dev->caps.num_ports; port++) in mlx4_allocate_default_counters()
2565 priv->def_counter[port] = -1; in mlx4_allocate_default_counters()
2567 for (port = 0; port < dev->caps.num_ports; port++) { in mlx4_allocate_default_counters()
2570 if (!err || err == -ENOSPC) { in mlx4_allocate_default_counters()
2571 priv->def_counter[port] = idx; in mlx4_allocate_default_counters()
2573 } else if (err == -ENOENT) { in mlx4_allocate_default_counters()
2576 } else if (mlx4_is_slave(dev) && err == -EINVAL) { in mlx4_allocate_default_counters()
2577 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); in mlx4_allocate_default_counters()
2589 __func__, priv->def_counter[port], port + 1); in mlx4_allocate_default_counters()
2599 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) in __mlx4_counter_alloc()
2600 return -ENOENT; in __mlx4_counter_alloc()
2602 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); in __mlx4_counter_alloc()
2603 if (*idx == -1) { in __mlx4_counter_alloc()
2605 return -ENOSPC; in __mlx4_counter_alloc()
2623 if (WARN_ON(err == -ENOSPC)) in mlx4_counter_alloc()
2624 err = -EINVAL; in mlx4_counter_alloc()
2642 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, in __mlx4_clear_if_stat()
2652 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) in __mlx4_counter_free()
2660 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); in __mlx4_counter_free()
2683 return priv->def_counter[port - 1]; in mlx4_get_default_counter_index()
2691 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; in mlx4_set_admin_guid()
2699 return priv->mfunc.master.vf_admin[entry].vport[port].guid; in mlx4_get_admin_guid()
2715 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; in mlx4_set_random_admin_guid()
2731 err = mlx4_uar_alloc(dev, &priv->driver_uar); in mlx4_setup_hca()
2737 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); in mlx4_setup_hca()
2738 if (!priv->kar) { in mlx4_setup_hca()
2740 err = -ENOMEM; in mlx4_setup_hca()
2783 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); in mlx4_setup_hca()
2789 if (dev->flags & MLX4_FLAG_MSI_X) { in mlx4_setup_hca()
2790 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", in mlx4_setup_hca()
2791 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); in mlx4_setup_hca()
2792 mlx4_warn(dev, "Trying again without MSI-X\n"); in mlx4_setup_hca()
2795 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); in mlx4_setup_hca()
2824 if (err && err != -ENOENT) { in mlx4_setup_hca()
2837 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_setup_hca()
2844 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; in mlx4_setup_hca()
2846 /* initialize per-slave default ib port capabilities */ in mlx4_setup_hca()
2849 for (i = 0; i < dev->num_slaves; i++) { in mlx4_setup_hca()
2852 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = in mlx4_setup_hca()
2858 dev->caps.port_ib_mtu[port] = IB_MTU_2048; in mlx4_setup_hca()
2860 dev->caps.port_ib_mtu[port] = IB_MTU_4096; in mlx4_setup_hca()
2863 dev->caps.pkey_table_len[port] : -1); in mlx4_setup_hca()
2910 iounmap(priv->kar); in mlx4_setup_hca()
2913 mlx4_uar_free(dev, &priv->driver_uar); in mlx4_setup_hca()
2928 if (eqn > dev->caps.num_comp_vectors) in mlx4_init_affinity_hint()
2929 return -EINVAL; in mlx4_init_affinity_hint()
2934 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); in mlx4_init_affinity_hint()
2940 eq = &priv->eq_table.eq[eqn]; in mlx4_init_affinity_hint()
2942 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) in mlx4_init_affinity_hint()
2943 return -ENOMEM; in mlx4_init_affinity_hint()
2945 cpumask_set_cpu(requested_cpu, eq->affinity_mask); in mlx4_init_affinity_hint()
2958 int nreq = min3(dev->caps.num_ports * in mlx4_enable_msi_x()
2960 dev->caps.num_eqs - dev->caps.reserved_eqs, in mlx4_enable_msi_x()
2973 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, in mlx4_enable_msi_x()
2981 dev->caps.num_comp_vectors = nreq - 1; in mlx4_enable_msi_x()
2983 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; in mlx4_enable_msi_x()
2984 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, in mlx4_enable_msi_x()
2985 dev->caps.num_ports); in mlx4_enable_msi_x()
2987 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { in mlx4_enable_msi_x()
2991 priv->eq_table.eq[i].irq = in mlx4_enable_msi_x()
2992 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; in mlx4_enable_msi_x()
2994 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { in mlx4_enable_msi_x()
2995 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, in mlx4_enable_msi_x()
2996 dev->caps.num_ports); in mlx4_enable_msi_x()
3002 priv->eq_table.eq[i].actv_ports.ports); in mlx4_enable_msi_x()
3008 * (dev->caps.num_comp_vectors / dev->caps.num_ports) in mlx4_enable_msi_x()
3016 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && in mlx4_enable_msi_x()
3018 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == in mlx4_enable_msi_x()
3020 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, in mlx4_enable_msi_x()
3026 dev->flags |= MLX4_FLAG_MSI_X; in mlx4_enable_msi_x()
3033 dev->caps.num_comp_vectors = 1; in mlx4_enable_msi_x()
3037 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; in mlx4_enable_msi_x()
3039 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, in mlx4_enable_msi_x()
3040 dev->caps.num_ports); in mlx4_enable_msi_x()
3064 return -EOPNOTSUPP; in mlx4_devlink_port_type_set()
3077 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; in mlx4_init_port_info()
3080 err = devl_port_register_with_ops(devlink, &info->devlink_port, port, in mlx4_init_port_info()
3090 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) in mlx4_init_port_info()
3091 devlink_port_type_eth_set(&info->devlink_port); in mlx4_init_port_info()
3093 dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) in mlx4_init_port_info()
3094 devlink_port_type_ib_set(&info->devlink_port, NULL); in mlx4_init_port_info()
3096 info->dev = dev; in mlx4_init_port_info()
3097 info->port = port; in mlx4_init_port_info()
3099 mlx4_init_mac_table(dev, &info->mac_table); in mlx4_init_port_info()
3100 mlx4_init_vlan_table(dev, &info->vlan_table); in mlx4_init_port_info()
3101 mlx4_init_roce_gid_table(dev, &info->gid_table); in mlx4_init_port_info()
3102 info->base_qpn = mlx4_get_base_qpn(dev, port); in mlx4_init_port_info()
3105 sprintf(info->dev_name, "mlx4_port%d", port); in mlx4_init_port_info()
3106 info->port_attr.attr.name = info->dev_name; in mlx4_init_port_info()
3108 info->port_attr.attr.mode = 0444; in mlx4_init_port_info()
3110 info->port_attr.attr.mode = 0644; in mlx4_init_port_info()
3111 info->port_attr.store = set_port_type; in mlx4_init_port_info()
3113 info->port_attr.show = show_port_type; in mlx4_init_port_info()
3114 sysfs_attr_init(&info->port_attr.attr); in mlx4_init_port_info()
3116 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); in mlx4_init_port_info()
3119 devlink_port_type_clear(&info->devlink_port); in mlx4_init_port_info()
3120 devl_port_unregister(&info->devlink_port); in mlx4_init_port_info()
3121 info->port = -1; in mlx4_init_port_info()
3125 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); in mlx4_init_port_info()
3126 info->port_mtu_attr.attr.name = info->dev_mtu_name; in mlx4_init_port_info()
3128 info->port_mtu_attr.attr.mode = 0444; in mlx4_init_port_info()
3130 info->port_mtu_attr.attr.mode = 0644; in mlx4_init_port_info()
3131 info->port_mtu_attr.store = set_port_ib_mtu; in mlx4_init_port_info()
3133 info->port_mtu_attr.show = show_port_ib_mtu; in mlx4_init_port_info()
3134 sysfs_attr_init(&info->port_mtu_attr.attr); in mlx4_init_port_info()
3136 err = device_create_file(&dev->persist->pdev->dev, in mlx4_init_port_info()
3137 &info->port_mtu_attr); in mlx4_init_port_info()
3140 device_remove_file(&info->dev->persist->pdev->dev, in mlx4_init_port_info()
3141 &info->port_attr); in mlx4_init_port_info()
3142 devlink_port_type_clear(&info->devlink_port); in mlx4_init_port_info()
3143 devl_port_unregister(&info->devlink_port); in mlx4_init_port_info()
3144 info->port = -1; in mlx4_init_port_info()
3153 if (info->port < 0) in mlx4_cleanup_port_info()
3156 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); in mlx4_cleanup_port_info()
3157 device_remove_file(&info->dev->persist->pdev->dev, in mlx4_cleanup_port_info()
3158 &info->port_mtu_attr); in mlx4_cleanup_port_info()
3159 devlink_port_type_clear(&info->devlink_port); in mlx4_cleanup_port_info()
3160 devl_port_unregister(&info->devlink_port); in mlx4_cleanup_port_info()
3163 free_irq_cpu_rmap(info->rmap); in mlx4_cleanup_port_info()
3164 info->rmap = NULL; in mlx4_cleanup_port_info()
3171 int num_entries = dev->caps.num_ports; in mlx4_init_steering()
3174 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer), in mlx4_init_steering()
3176 if (!priv->steer) in mlx4_init_steering()
3177 return -ENOMEM; in mlx4_init_steering()
3181 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); in mlx4_init_steering()
3182 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); in mlx4_init_steering()
3192 int num_entries = dev->caps.num_ports; in mlx4_clear_steering()
3198 &priv->steer[i].promisc_qps[j], in mlx4_clear_steering()
3200 list_del(&pqp->list); in mlx4_clear_steering()
3204 &priv->steer[i].steer_entries[j], in mlx4_clear_steering()
3206 list_del(&entry->list); in mlx4_clear_steering()
3208 &entry->duplicates, in mlx4_clear_steering()
3210 list_del(&pqp->list); in mlx4_clear_steering()
3217 kfree(priv->steer); in mlx4_clear_steering()
3222 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); in extended_func_num()
3233 if (pci_channel_offline(dev->persist->pdev)) in mlx4_get_ownership()
3234 return -EIO; in mlx4_get_ownership()
3236 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + in mlx4_get_ownership()
3241 return -ENOMEM; in mlx4_get_ownership()
3253 if (pci_channel_offline(dev->persist->pdev)) in mlx4_free_ownership()
3256 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + in mlx4_free_ownership()
3274 u64 dev_flags = dev->flags; in mlx4_enable_sriov()
3280 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), in mlx4_enable_sriov()
3282 if (!dev->dev_vfs) in mlx4_enable_sriov()
3288 if (dev->flags & MLX4_FLAG_SRIOV) { in mlx4_enable_sriov()
3290 … mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", in mlx4_enable_sriov()
3296 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL); in mlx4_enable_sriov()
3297 if (NULL == dev->dev_vfs) { in mlx4_enable_sriov()
3302 if (!(dev->flags & MLX4_FLAG_SRIOV)) { in mlx4_enable_sriov()
3306 err = -ENOMEM; in mlx4_enable_sriov()
3309 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); in mlx4_enable_sriov()
3313 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", in mlx4_enable_sriov()
3321 dev->persist->num_vfs = total_vfs; in mlx4_enable_sriov()
3328 dev->persist->num_vfs = 0; in mlx4_enable_sriov()
3329 kfree(dev->dev_vfs); in mlx4_enable_sriov()
3330 dev->dev_vfs = NULL; in mlx4_enable_sriov()
3335 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3343 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && in mlx4_check_dev_cap()
3354 struct pci_dev *pdev = dev->persist->pdev; in mlx4_pci_enable_device()
3357 mutex_lock(&dev->persist->pci_status_mutex); in mlx4_pci_enable_device()
3358 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { in mlx4_pci_enable_device()
3361 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; in mlx4_pci_enable_device()
3363 mutex_unlock(&dev->persist->pci_status_mutex); in mlx4_pci_enable_device()
3370 struct pci_dev *pdev = dev->persist->pdev; in mlx4_pci_disable_device()
3372 mutex_lock(&dev->persist->pci_status_mutex); in mlx4_pci_disable_device()
3373 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { in mlx4_pci_disable_device()
3375 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; in mlx4_pci_disable_device()
3377 mutex_unlock(&dev->persist->pci_status_mutex); in mlx4_pci_disable_device()
3394 dev = &priv->dev; in mlx4_load_one()
3400 ATOMIC_INIT_NOTIFIER_HEAD(&priv->event_nh); in mlx4_load_one()
3402 mutex_init(&priv->port_mutex); in mlx4_load_one()
3403 mutex_init(&priv->bond_mutex); in mlx4_load_one()
3405 INIT_LIST_HEAD(&priv->pgdir_list); in mlx4_load_one()
3406 mutex_init(&priv->pgdir_mutex); in mlx4_load_one()
3407 spin_lock_init(&priv->cmd.context_lock); in mlx4_load_one()
3409 INIT_LIST_HEAD(&priv->bf_list); in mlx4_load_one()
3410 mutex_init(&priv->bf_mutex); in mlx4_load_one()
3412 dev->rev_id = pdev->revision; in mlx4_load_one()
3413 dev->numa_node = dev_to_node(&pdev->dev); in mlx4_load_one()
3417 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); in mlx4_load_one()
3418 dev->flags |= MLX4_FLAG_SLAVE; in mlx4_load_one()
3422 * if already taken, skip -- do not allow multiple PFs */ in mlx4_load_one()
3428 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); in mlx4_load_one()
3429 err = -EINVAL; in mlx4_load_one()
3434 atomic_set(&priv->opreq_count, 0); in mlx4_load_one()
3435 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); in mlx4_load_one()
3449 dev->flags = MLX4_FLAG_MASTER; in mlx4_load_one()
3452 dev->flags |= MLX4_FLAG_SRIOV; in mlx4_load_one()
3453 dev->persist->num_vfs = total_vfs; in mlx4_load_one()
3460 dev->persist->state = MLX4_DEVICE_STATE_UP; in mlx4_load_one()
3474 dev->num_slaves = MLX4_MAX_NUM_SLAVES; in mlx4_load_one()
3477 dev->num_slaves = 0; in mlx4_load_one()
3498 err = -ENOMEM; in mlx4_load_one()
3511 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { in mlx4_load_one()
3519 dev->flags = dev_flags; in mlx4_load_one()
3520 if (!SRIOV_VALID_STATE(dev->flags)) { in mlx4_load_one()
3550 if (err == -EACCES) { in mlx4_load_one()
3551 /* Not primary Physical function in mlx4_load_one()
3555 if (dev->flags & MLX4_FLAG_SRIOV) { in mlx4_load_one()
3560 dev->flags &= ~MLX4_FLAG_SRIOV; in mlx4_load_one()
3564 dev->flags |= MLX4_FLAG_SLAVE; in mlx4_load_one()
3565 dev->flags &= ~MLX4_FLAG_MASTER; in mlx4_load_one()
3571 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { in mlx4_load_one()
3575 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { in mlx4_load_one()
3577 dev->flags = dev_flags; in mlx4_load_one()
3587 dev->flags = dev_flags; in mlx4_load_one()
3590 if (!SRIOV_VALID_STATE(dev->flags)) { in mlx4_load_one()
3592 err = -EINVAL; in mlx4_load_one()
3599 * express device capabilities are under-satisfied by the bus. in mlx4_load_one()
3602 pcie_print_link_status(dev->persist->pdev); in mlx4_load_one()
3607 if (dev->caps.num_ports < 2 && in mlx4_load_one()
3609 err = -EINVAL; in mlx4_load_one()
3612 dev->caps.num_ports); in mlx4_load_one()
3615 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); in mlx4_load_one()
3618 i < sizeof(dev->persist->nvfs)/ in mlx4_load_one()
3619 sizeof(dev->persist->nvfs[0]); i++) { in mlx4_load_one()
3622 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { in mlx4_load_one()
3623 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; in mlx4_load_one()
3624 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : in mlx4_load_one()
3625 dev->caps.num_ports; in mlx4_load_one()
3643 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); in mlx4_load_one()
3644 mutex_init(&priv->msix_ctl.pool_lock); in mlx4_load_one()
3648 !(dev->flags & MLX4_FLAG_MSI_X)) { in mlx4_load_one()
3649 err = -EOPNOTSUPP; in mlx4_load_one()
3650 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); in mlx4_load_one()
3663 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && in mlx4_load_one()
3665 dev->flags &= ~MLX4_FLAG_MSI_X; in mlx4_load_one()
3666 dev->caps.num_comp_vectors = 1; in mlx4_load_one()
3686 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_load_one()
3692 priv->v2p.port1 = 1; in mlx4_load_one()
3693 priv->v2p.port2 = 2; in mlx4_load_one()
3702 priv->removed = 0; in mlx4_load_one()
3704 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) in mlx4_load_one()
3711 for (--port; port >= 1; --port) in mlx4_load_one()
3712 mlx4_cleanup_port_info(&priv->port[port]); in mlx4_load_one()
3733 if (dev->flags & MLX4_FLAG_MSI_X) in mlx4_load_one()
3762 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { in mlx4_load_one()
3764 dev->flags &= ~MLX4_FLAG_SRIOV; in mlx4_load_one()
3767 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) in mlx4_load_one()
3770 kfree(priv->dev.dev_vfs); in mlx4_load_one()
3795 err = mlx4_pci_enable_device(&priv->dev); in __mlx4_init_one()
3797 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in __mlx4_init_one()
3806 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { in __mlx4_init_one()
3807 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; in __mlx4_init_one()
3809 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); in __mlx4_init_one()
3810 err = -EINVAL; in __mlx4_init_one()
3816 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; in __mlx4_init_one()
3818 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); in __mlx4_init_one()
3819 err = -EINVAL; in __mlx4_init_one()
3824 dev_err(&pdev->dev, in __mlx4_init_one()
3827 err = -EINVAL; in __mlx4_init_one()
3833 dev_err(&pdev->dev, in __mlx4_init_one()
3837 err = -EINVAL; in __mlx4_init_one()
3845 …dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\… in __mlx4_init_one()
3847 err = -ENODEV; in __mlx4_init_one()
3851 dev_err(&pdev->dev, "Missing UAR, aborting\n"); in __mlx4_init_one()
3852 err = -ENODEV; in __mlx4_init_one()
3858 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); in __mlx4_init_one()
3864 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in __mlx4_init_one()
3866 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); in __mlx4_init_one()
3867 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in __mlx4_init_one()
3869 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); in __mlx4_init_one()
3875 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); in __mlx4_init_one()
3889 err = -ENODEV; in __mlx4_init_one()
3892 if ((extended_func_num(pdev) - vfs_offset) in __mlx4_init_one()
3894 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", in __mlx4_init_one()
3896 err = -ENODEV; in __mlx4_init_one()
3902 err = mlx4_crdump_init(&priv->dev); in __mlx4_init_one()
3906 err = mlx4_catas_init(&priv->dev); in __mlx4_init_one()
3917 mlx4_catas_end(&priv->dev); in __mlx4_init_one()
3920 mlx4_crdump_end(&priv->dev); in __mlx4_init_one()
3926 mlx4_pci_disable_device(&priv->dev); in __mlx4_init_one()
3933 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_param_load_driverinit_values()
3934 struct mlx4_fw_crdump *crdump = &dev->persist->crdump; in mlx4_devlink_param_load_driverinit_values()
3965 if (!err && crdump->snapshot_enable != saved_value.vbool) { in mlx4_devlink_param_load_driverinit_values()
3966 crdump->snapshot_enable = saved_value.vbool; in mlx4_devlink_param_load_driverinit_values()
3982 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_reload_down()
3983 struct mlx4_dev_persistent *persist = dev->persist; in mlx4_devlink_reload_down()
3987 return -EOPNOTSUPP; in mlx4_devlink_reload_down()
3989 if (persist->num_vfs) in mlx4_devlink_reload_down()
3990 …mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n… in mlx4_devlink_reload_down()
3991 mlx4_restart_one_down(persist->pdev); in mlx4_devlink_reload_down()
4000 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_reload_up()
4001 struct mlx4_dev_persistent *persist = dev->persist; in mlx4_devlink_reload_up()
4005 err = mlx4_restart_one_up(persist->pdev, true, devlink); in mlx4_devlink_reload_up()
4007 mlx4_err(persist->dev, "mlx4_restart_one_up failed, ret=%d\n", in mlx4_devlink_reload_up()
4028 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv), &pdev->dev); in mlx4_init_one()
4030 return -ENOMEM; in mlx4_init_one()
4034 dev = &priv->dev; in mlx4_init_one()
4035 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); in mlx4_init_one()
4036 if (!dev->persist) { in mlx4_init_one()
4037 ret = -ENOMEM; in mlx4_init_one()
4040 dev->persist->pdev = pdev; in mlx4_init_one()
4041 dev->persist->dev = dev; in mlx4_init_one()
4042 pci_set_drvdata(pdev, dev->persist); in mlx4_init_one()
4043 priv->pci_dev_data = id->driver_data; in mlx4_init_one()
4044 mutex_init(&dev->persist->device_state_mutex); in mlx4_init_one()
4045 mutex_init(&dev->persist->interface_state_mutex); in mlx4_init_one()
4046 mutex_init(&dev->persist->pci_status_mutex); in mlx4_init_one()
4053 ret = __mlx4_init_one(pdev, id->driver_data, priv); in mlx4_init_one()
4066 kfree(dev->persist); in mlx4_init_one()
4075 struct mlx4_dev_persistent *persist = dev->persist; in mlx4_clean_dev()
4077 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); in mlx4_clean_dev()
4080 priv->dev.persist = persist; in mlx4_clean_dev()
4081 priv->dev.flags = flags; in mlx4_clean_dev()
4087 struct mlx4_dev *dev = persist->dev; in mlx4_unload_one()
4095 if (priv->removed) in mlx4_unload_one()
4099 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_unload_one()
4100 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; in mlx4_unload_one()
4101 dev->persist->curr_port_poss_type[i] = dev->caps. in mlx4_unload_one()
4105 pci_dev_data = priv->pci_dev_data; in mlx4_unload_one()
4110 for (p = 1; p <= dev->caps.num_ports; p++) { in mlx4_unload_one()
4111 mlx4_cleanup_port_info(&priv->port[p]); in mlx4_unload_one()
4136 iounmap(priv->kar); in mlx4_unload_one()
4137 mlx4_uar_free(dev, &priv->driver_uar); in mlx4_unload_one()
4150 if (dev->flags & MLX4_FLAG_MSI_X) in mlx4_unload_one()
4157 kfree(dev->dev_vfs); in mlx4_unload_one()
4162 priv->pci_dev_data = pci_dev_data; in mlx4_unload_one()
4163 priv->removed = 1; in mlx4_unload_one()
4169 struct mlx4_dev *dev = persist->dev; in mlx4_remove_one()
4178 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; in mlx4_remove_one()
4180 mutex_lock(&persist->interface_state_mutex); in mlx4_remove_one()
4181 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; in mlx4_remove_one()
4182 mutex_unlock(&persist->interface_state_mutex); in mlx4_remove_one()
4184 /* Disabling SR-IOV is not allowed while there are active vf's */ in mlx4_remove_one()
4185 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { in mlx4_remove_one()
4189 pr_warn("Will not disable SR-IOV.\n"); in mlx4_remove_one()
4196 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_remove_one()
4202 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { in mlx4_remove_one()
4203 mlx4_warn(dev, "Disabling SR-IOV\n"); in mlx4_remove_one()
4211 kfree(dev->persist); in mlx4_remove_one()
4225 mutex_lock(&priv->port_mutex); in restore_current_port_types()
4226 for (i = 0; i < dev->caps.num_ports; i++) in restore_current_port_types()
4227 dev->caps.possible_type[i + 1] = poss_types[i]; in restore_current_port_types()
4230 mutex_unlock(&priv->port_mutex); in restore_current_port_types()
4244 struct mlx4_dev *dev = persist->dev; in mlx4_restart_one_up()
4249 pci_dev_data = priv->pci_dev_data; in mlx4_restart_one_up()
4250 total_vfs = dev->persist->num_vfs; in mlx4_restart_one_up()
4251 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); in mlx4_restart_one_up()
4262 err = restore_current_port_types(dev, dev->persist->curr_port_type, in mlx4_restart_one_up()
4263 dev->persist->curr_port_poss_type); in mlx4_restart_one_up()
4291 /* MT25458 ConnectX EN 10GBASE-T */
4300 /* MT25400 Family [ConnectX-2] */
4303 /* MT27500 Family [ConnectX-3] */
4333 struct mlx4_dev *dev = persist->dev; in mlx4_pci_err_detected()
4336 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); in mlx4_pci_err_detected()
4341 mutex_lock(&persist->interface_state_mutex); in mlx4_pci_err_detected()
4342 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_pci_err_detected()
4345 mutex_unlock(&persist->interface_state_mutex); in mlx4_pci_err_detected()
4350 mlx4_pci_disable_device(persist->dev); in mlx4_pci_err_detected()
4357 struct mlx4_dev *dev = persist->dev; in mlx4_pci_slot_reset()
4363 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); in mlx4_pci_slot_reset()
4376 struct mlx4_dev *dev = persist->dev; in mlx4_pci_resume()
4384 total_vfs = dev->persist->num_vfs; in mlx4_pci_resume()
4385 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); in mlx4_pci_resume()
4389 mutex_lock(&persist->interface_state_mutex); in mlx4_pci_resume()
4390 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { in mlx4_pci_resume()
4391 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, in mlx4_pci_resume()
4399 err = restore_current_port_types(dev, dev->persist-> in mlx4_pci_resume()
4400 curr_port_type, dev->persist-> in mlx4_pci_resume()
4406 mutex_unlock(&persist->interface_state_mutex); in mlx4_pci_resume()
4413 struct mlx4_dev *dev = persist->dev; in mlx4_shutdown()
4416 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); in mlx4_shutdown()
4419 mutex_lock(&persist->interface_state_mutex); in mlx4_shutdown()
4420 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_shutdown()
4422 mutex_unlock(&persist->interface_state_mutex); in mlx4_shutdown()
4437 struct mlx4_dev *dev = persist->dev; in mlx4_suspend()
4443 mutex_lock(&persist->interface_state_mutex); in mlx4_suspend()
4444 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_suspend()
4446 mutex_unlock(&persist->interface_state_mutex); in mlx4_suspend()
4456 struct mlx4_dev *dev = persist->dev; in mlx4_resume()
4464 total_vfs = dev->persist->num_vfs; in mlx4_resume()
4465 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); in mlx4_resume()
4469 mutex_lock(&persist->interface_state_mutex); in mlx4_resume()
4470 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { in mlx4_resume()
4471 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, in mlx4_resume()
4475 dev->persist->curr_port_type, in mlx4_resume()
4476 dev->persist->curr_port_poss_type); in mlx4_resume()
4481 mutex_unlock(&persist->interface_state_mutex); in mlx4_resume()
4503 return -1; in mlx4_verify_params()
4508 return -1; in mlx4_verify_params()
4512 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", in mlx4_verify_params()
4516 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); in mlx4_verify_params()
4521 return -1; in mlx4_verify_params()
4530 if (mlx4_log_num_mgm_entry_size < -7 || in mlx4_verify_params()
4534 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", in mlx4_verify_params()
4538 return -1; in mlx4_verify_params()
4552 return -EINVAL; in mlx4_init()
4557 return -ENOMEM; in mlx4_init()