Lines Matching +full:rxc +full:- +full:inverse
1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/dma-mapping.h>
77 /* Flow-Control Configuration Register */
133 /* Delay-Macro Register */
201 * reuse the same structure for both TX and RX - the layout is the same, only
291 return priv->ndev->dev.parent; in mtk_star_get_dev()
305 ring->descs = descs; in mtk_star_ring_init()
306 ring->head = 0; in mtk_star_ring_init()
307 ring->tail = 0; in mtk_star_ring_init()
313 struct mtk_star_ring_desc *desc = &ring->descs[ring->tail]; in mtk_star_ring_pop_tail()
316 status = READ_ONCE(desc->status); in mtk_star_ring_pop_tail()
320 return -1; in mtk_star_ring_pop_tail()
322 desc_data->len = status & MTK_STAR_DESC_MSK_LEN; in mtk_star_ring_pop_tail()
323 desc_data->flags = status & ~MTK_STAR_DESC_MSK_LEN; in mtk_star_ring_pop_tail()
324 desc_data->dma_addr = ring->dma_addrs[ring->tail]; in mtk_star_ring_pop_tail()
325 desc_data->skb = ring->skbs[ring->tail]; in mtk_star_ring_pop_tail()
327 ring->dma_addrs[ring->tail] = 0; in mtk_star_ring_pop_tail()
328 ring->skbs[ring->tail] = NULL; in mtk_star_ring_pop_tail()
332 WRITE_ONCE(desc->data_ptr, 0); in mtk_star_ring_pop_tail()
333 WRITE_ONCE(desc->status, status); in mtk_star_ring_pop_tail()
335 ring->tail = (ring->tail + 1) % MTK_STAR_RING_NUM_DESCS; in mtk_star_ring_pop_tail()
344 struct mtk_star_ring_desc *desc = &ring->descs[ring->head]; in mtk_star_ring_push_head()
347 status = READ_ONCE(desc->status); in mtk_star_ring_push_head()
349 ring->skbs[ring->head] = desc_data->skb; in mtk_star_ring_push_head()
350 ring->dma_addrs[ring->head] = desc_data->dma_addr; in mtk_star_ring_push_head()
352 status |= desc_data->len; in mtk_star_ring_push_head()
356 WRITE_ONCE(desc->data_ptr, desc_data->dma_addr); in mtk_star_ring_push_head()
357 WRITE_ONCE(desc->status, status); in mtk_star_ring_push_head()
361 WRITE_ONCE(desc->status, status); in mtk_star_ring_push_head()
363 ring->head = (ring->head + 1) % MTK_STAR_RING_NUM_DESCS; in mtk_star_ring_push_head()
388 if (ring->tail > ring->head) in mtk_star_tx_ring_avail()
389 avail = ring->tail - ring->head - 1; in mtk_star_tx_ring_avail()
391 avail = MTK_STAR_RING_NUM_DESCS - ring->head + ring->tail - 1; in mtk_star_tx_ring_avail()
402 return dma_map_single(dev, skb_tail_pointer(skb) - 2, in mtk_star_dma_map_rx()
411 dma_unmap_single(dev, desc_data->dma_addr, in mtk_star_dma_unmap_rx()
412 skb_tailroom(desc_data->skb), DMA_FROM_DEVICE); in mtk_star_dma_unmap_rx()
420 return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); in mtk_star_dma_map_tx()
428 return dma_unmap_single(dev, desc_data->dma_addr, in mtk_star_dma_unmap_tx()
429 skb_headlen(desc_data->skb), DMA_TO_DEVICE); in mtk_star_dma_unmap_tx()
434 regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG, in mtk_star_nic_disable_pd()
443 regmap_read(priv->regs, MTK_STAR_REG_INT_MASK, &value); in mtk_star_enable_dma_irq()
450 regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, value); in mtk_star_enable_dma_irq()
458 regmap_read(priv->regs, MTK_STAR_REG_INT_MASK, &value); in mtk_star_disable_dma_irq()
465 regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, value); in mtk_star_disable_dma_irq()
475 regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~val); in mtk_star_intr_enable()
480 regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~0); in mtk_star_intr_disable()
487 regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val); in mtk_star_intr_ack_all()
488 regmap_write(priv->regs, MTK_STAR_REG_INT_STS, val); in mtk_star_intr_ack_all()
499 priv->descs_base = (struct mtk_star_ring_desc *)priv->ring_base; in mtk_star_dma_init()
502 desc = &priv->descs_base[i]; in mtk_star_dma_init()
505 desc->status = MTK_STAR_DESC_BIT_COWN; in mtk_star_dma_init()
506 if ((i == MTK_STAR_NUM_TX_DESCS - 1) || in mtk_star_dma_init()
507 (i == MTK_STAR_NUM_DESCS_TOTAL - 1)) in mtk_star_dma_init()
508 desc->status |= MTK_STAR_DESC_BIT_EOR; in mtk_star_dma_init()
511 mtk_star_ring_init(&priv->tx_ring, priv->descs_base); in mtk_star_dma_init()
512 mtk_star_ring_init(&priv->rx_ring, in mtk_star_dma_init()
513 priv->descs_base + MTK_STAR_NUM_TX_DESCS); in mtk_star_dma_init()
516 val = (unsigned int)priv->dma_addr; in mtk_star_dma_init()
517 regmap_write(priv->regs, MTK_STAR_REG_TX_BASE_ADDR, val); in mtk_star_dma_init()
518 regmap_write(priv->regs, MTK_STAR_REG_TX_DPTR, val); in mtk_star_dma_init()
521 regmap_write(priv->regs, MTK_STAR_REG_RX_BASE_ADDR, val); in mtk_star_dma_init()
522 regmap_write(priv->regs, MTK_STAR_REG_RX_DPTR, val); in mtk_star_dma_init()
527 regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL, in mtk_star_dma_start()
529 regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL, in mtk_star_dma_start()
535 regmap_write(priv->regs, MTK_STAR_REG_TX_DMA_CTRL, in mtk_star_dma_stop()
537 regmap_write(priv->regs, MTK_STAR_REG_RX_DMA_CTRL, in mtk_star_dma_stop()
549 priv->descs_base[i].status |= MTK_STAR_DESC_BIT_COWN; in mtk_star_dma_disable()
554 regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL, in mtk_star_dma_resume_rx()
560 regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL, in mtk_star_dma_resume_tx()
567 const u8 *mac_addr = ndev->dev_addr; in mtk_star_set_mac_addr()
574 regmap_write(priv->regs, MTK_STAR_REG_MY_MAC_H, high); in mtk_star_set_mac_addr()
575 regmap_write(priv->regs, MTK_STAR_REG_MY_MAC_L, low); in mtk_star_set_mac_addr()
614 regmap_read(priv->regs, counter_regs[i], &val); in mtk_star_reset_counters()
622 regmap_read(priv->regs, reg, &val); in mtk_star_update_stat()
631 struct rtnl_link_stats64 *stats = &priv->stats; in mtk_star_update_stats()
634 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXOKPKT, &stats->rx_packets); in mtk_star_update_stats()
635 mtk_star_update_stat(priv, MTK_STAR_REG_C_TXOKPKT, &stats->tx_packets); in mtk_star_update_stats()
636 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXOKBYTE, &stats->rx_bytes); in mtk_star_update_stats()
637 mtk_star_update_stat(priv, MTK_STAR_REG_C_TXOKBYTE, &stats->tx_bytes); in mtk_star_update_stats()
640 mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_MULTI, &stats->multicast); in mtk_star_update_stats()
641 mtk_star_update_stat(priv, MTK_STAR_REG_C_TX_MULTI, &stats->multicast); in mtk_star_update_stats()
645 &stats->collisions); in mtk_star_update_stats()
647 &stats->collisions); in mtk_star_update_stats()
648 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXRUNT, &stats->collisions); in mtk_star_update_stats()
652 &stats->rx_length_errors); in mtk_star_update_stats()
654 &stats->rx_over_errors); in mtk_star_update_stats()
655 mtk_star_update_stat(priv, MTK_STAR_REG_C_RXCRC, &stats->rx_crc_errors); in mtk_star_update_stats()
657 &stats->rx_frame_errors); in mtk_star_update_stats()
659 &stats->rx_fifo_errors); in mtk_star_update_stats()
661 mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_RERR, &stats->rx_errors); in mtk_star_update_stats()
662 stats->rx_errors += stats->rx_length_errors; in mtk_star_update_stats()
663 stats->rx_errors += stats->rx_over_errors; in mtk_star_update_stats()
664 stats->rx_errors += stats->rx_crc_errors; in mtk_star_update_stats()
665 stats->rx_errors += stats->rx_frame_errors; in mtk_star_update_stats()
666 stats->rx_errors += stats->rx_fifo_errors; in mtk_star_update_stats()
680 if (tail & (MTK_STAR_SKB_ALIGNMENT - 1)) { in mtk_star_alloc_skb()
681 offset = tail & (MTK_STAR_SKB_ALIGNMENT - 1); in mtk_star_alloc_skb()
682 skb_reserve(skb, MTK_STAR_SKB_ALIGNMENT - offset); in mtk_star_alloc_skb()
685 /* Ensure 16-byte alignment of the skb pointer: eth_type_trans() will in mtk_star_alloc_skb()
696 struct mtk_star_ring *ring = &priv->rx_ring; in mtk_star_prepare_rx_skbs()
706 return -ENOMEM; in mtk_star_prepare_rx_skbs()
711 return -ENOMEM; in mtk_star_prepare_rx_skbs()
714 desc = &ring->descs[i]; in mtk_star_prepare_rx_skbs()
715 desc->data_ptr = dma_addr; in mtk_star_prepare_rx_skbs()
716 desc->status |= skb_tailroom(skb) & MTK_STAR_DESC_MSK_LEN; in mtk_star_prepare_rx_skbs()
717 desc->status &= ~MTK_STAR_DESC_BIT_COWN; in mtk_star_prepare_rx_skbs()
718 ring->skbs[i] = skb; in mtk_star_prepare_rx_skbs()
719 ring->dma_addrs[i] = dma_addr; in mtk_star_prepare_rx_skbs()
734 if (!ring->dma_addrs[i]) in mtk_star_ring_free_skbs()
737 desc_data.dma_addr = ring->dma_addrs[i]; in mtk_star_ring_free_skbs()
738 desc_data.skb = ring->skbs[i]; in mtk_star_ring_free_skbs()
747 struct mtk_star_ring *ring = &priv->rx_ring; in mtk_star_free_rx_skbs()
754 struct mtk_star_ring *ring = &priv->tx_ring; in mtk_star_free_tx_skbs()
760 * mtk_star_handle_irq - Interrupt Handler.
777 napi_schedule_prep(&priv->rx_napi); in mtk_star_handle_irq()
779 napi_schedule_prep(&priv->tx_napi); in mtk_star_handle_irq()
782 spin_lock(&priv->lock); in mtk_star_handle_irq()
785 spin_unlock(&priv->lock); in mtk_star_handle_irq()
788 __napi_schedule(&priv->rx_napi); in mtk_star_handle_irq()
790 __napi_schedule(&priv->tx_napi); in mtk_star_handle_irq()
802 /* Wait for the completion of any previous command - CMD_START bit must be
809 return regmap_read_poll_timeout_atomic(priv->regs, in mtk_star_hash_wait_cmd_start()
821 ret = regmap_read_poll_timeout_atomic(priv->regs, in mtk_star_hash_wait_ok()
829 if (!regmap_test_bits(priv->regs, MTK_STAR_REG_HASH_CTRL, in mtk_star_hash_wait_ok()
831 return -EIO; in mtk_star_hash_wait_ok()
851 regmap_write(priv->regs, MTK_STAR_REG_HASH_CTRL, val); in mtk_star_set_hashbit()
864 regmap_set_bits(priv->regs, MTK_STAR_REG_HASH_CTRL, in mtk_star_reset_hash_table()
866 regmap_set_bits(priv->regs, MTK_STAR_REG_TEST1, in mtk_star_reset_hash_table()
876 if (priv->speed == SPEED_1000) in mtk_star_phy_config()
878 else if (priv->speed == SPEED_100) in mtk_star_phy_config()
885 if (priv->pause) { in mtk_star_phy_config()
894 regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL1, val); in mtk_star_phy_config()
899 regmap_update_bits(priv->regs, MTK_STAR_REG_FC_CFG, in mtk_star_phy_config()
905 regmap_update_bits(priv->regs, MTK_STAR_REG_EXT_CFG, in mtk_star_phy_config()
912 struct phy_device *phydev = priv->phydev; in mtk_star_adjust_link()
915 if (phydev->link) { in mtk_star_adjust_link()
916 if (!priv->link) { in mtk_star_adjust_link()
917 priv->link = phydev->link; in mtk_star_adjust_link()
921 if (priv->speed != phydev->speed) { in mtk_star_adjust_link()
922 priv->speed = phydev->speed; in mtk_star_adjust_link()
926 if (priv->pause != phydev->pause) { in mtk_star_adjust_link()
927 priv->pause = phydev->pause; in mtk_star_adjust_link()
931 if (priv->link) { in mtk_star_adjust_link()
932 priv->link = phydev->link; in mtk_star_adjust_link()
938 if (phydev->link) in mtk_star_adjust_link()
941 phy_print_status(ndev->phydev); in mtk_star_adjust_link()
953 regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val); in mtk_star_init_config()
954 regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF, in mtk_star_init_config()
956 priv->compat_data->bit_clk_div); in mtk_star_init_config()
977 regmap_write(priv->regs, MTK_STAR_REG_MAC_CFG, val); in mtk_star_enable()
985 regmap_clear_bits(priv->regs, MTK_STAR_REG_ARL_CFG, in mtk_star_enable()
990 regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG, in mtk_star_enable()
1001 ret = request_irq(ndev->irq, mtk_star_handle_irq, in mtk_star_enable()
1002 IRQF_TRIGGER_NONE, ndev->name, ndev); in mtk_star_enable()
1006 napi_enable(&priv->tx_napi); in mtk_star_enable()
1007 napi_enable(&priv->rx_napi); in mtk_star_enable()
1013 priv->phydev = of_phy_connect(ndev, priv->phy_node, in mtk_star_enable()
1014 mtk_star_adjust_link, 0, priv->phy_intf); in mtk_star_enable()
1015 if (!priv->phydev) { in mtk_star_enable()
1017 ret = -ENODEV; in mtk_star_enable()
1022 phy_start(priv->phydev); in mtk_star_enable()
1028 napi_disable(&priv->rx_napi); in mtk_star_enable()
1029 napi_disable(&priv->tx_napi); in mtk_star_enable()
1030 free_irq(ndev->irq, ndev); in mtk_star_enable()
1042 napi_disable(&priv->tx_napi); in mtk_star_disable()
1043 napi_disable(&priv->rx_napi); in mtk_star_disable()
1047 phy_stop(priv->phydev); in mtk_star_disable()
1048 phy_disconnect(priv->phydev); in mtk_star_disable()
1049 free_irq(ndev->irq, ndev); in mtk_star_disable()
1070 return -EINVAL; in mtk_star_netdev_ioctl()
1072 return phy_mii_ioctl(ndev->phydev, req, cmd); in mtk_star_netdev_ioctl()
1077 netif_stop_queue(priv->ndev); in __mtk_star_maybe_stop_tx()
1081 if (likely(mtk_star_tx_ring_avail(&priv->tx_ring) < size)) in __mtk_star_maybe_stop_tx()
1082 return -EBUSY; in __mtk_star_maybe_stop_tx()
1084 netif_start_queue(priv->ndev); in __mtk_star_maybe_stop_tx()
1091 if (likely(mtk_star_tx_ring_avail(&priv->tx_ring) >= size)) in mtk_star_maybe_stop_tx()
1101 struct mtk_star_ring *ring = &priv->tx_ring; in mtk_star_netdev_start_xmit()
1104 int nfrags = skb_shinfo(skb)->nr_frags; in mtk_star_netdev_start_xmit()
1120 desc_data.len = skb->len; in mtk_star_netdev_start_xmit()
1123 netdev_sent_queue(ndev, skb->len); in mtk_star_netdev_start_xmit()
1133 ndev->stats.tx_dropped++; in mtk_star_netdev_start_xmit()
1142 struct mtk_star_ring *ring = &priv->tx_ring; in mtk_star_tx_complete_one()
1151 ret = desc_data.skb->len; in mtk_star_tx_complete_one()
1162 struct mtk_star_ring *ring = &priv->tx_ring; in mtk_star_tx_poll()
1163 struct net_device *ndev = priv->ndev; in mtk_star_tx_poll()
1164 unsigned int head = ring->head; in mtk_star_tx_poll()
1165 unsigned int entry = ring->tail; in mtk_star_tx_poll()
1167 while (entry != head && count < (MTK_STAR_RING_NUM_DESCS - 1)) { in mtk_star_tx_poll()
1175 entry = ring->tail; in mtk_star_tx_poll()
1185 spin_lock(&priv->lock); in mtk_star_tx_poll()
1187 spin_unlock(&priv->lock); in mtk_star_tx_poll()
1200 memcpy(stats, &priv->stats, sizeof(*stats)); in mtk_star_netdev_get_stats64()
1210 if (ndev->flags & IFF_PROMISC) { in mtk_star_set_rx_mode()
1211 regmap_set_bits(priv->regs, MTK_STAR_REG_ARL_CFG, in mtk_star_set_rx_mode()
1214 ndev->flags & IFF_ALLMULTI) { in mtk_star_set_rx_mode()
1227 hash_addr = (hw_addr->addr[0] & 0x01) << 8; in mtk_star_set_rx_mode()
1228 hash_addr += hw_addr->addr[5]; in mtk_star_set_rx_mode()
1238 if (ret == -ETIMEDOUT) in mtk_star_set_rx_mode()
1241 /* Should be -EIO */ in mtk_star_set_rx_mode()
1259 strscpy(info->driver, MTK_STAR_DRVNAME, sizeof(info->driver)); in mtk_star_get_drvinfo()
1272 struct mtk_star_ring *ring = &priv->rx_ring; in mtk_star_rx()
1275 struct net_device *ndev = priv->ndev; in mtk_star_rx()
1283 return -1; in mtk_star_rx()
1289 /* Error packet -> drop and reuse skb. */ in mtk_star_rx()
1299 ndev->stats.rx_dropped++; in mtk_star_rx()
1306 ndev->stats.rx_dropped++; in mtk_star_rx()
1319 desc_data.skb->ip_summed = CHECKSUM_NONE; in mtk_star_rx()
1320 desc_data.skb->protocol = eth_type_trans(desc_data.skb, ndev); in mtk_star_rx()
1321 desc_data.skb->dev = ndev; in mtk_star_rx()
1351 spin_lock(&priv->lock); in mtk_star_rx_poll()
1353 spin_unlock(&priv->lock); in mtk_star_rx_poll()
1361 regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0, in mtk_star_mdio_rwok_clear()
1369 return regmap_read_poll_timeout(priv->regs, MTK_STAR_REG_PHY_CTRL0, in mtk_star_mdio_rwok_wait()
1376 struct mtk_star_priv *priv = mii->priv; in mtk_star_mdio_read()
1386 regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0, val); in mtk_star_mdio_read()
1392 regmap_read(priv->regs, MTK_STAR_REG_PHY_CTRL0, &data); in mtk_star_mdio_read()
1403 struct mtk_star_priv *priv = mii->priv; in mtk_star_mdio_write()
1416 regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0, val); in mtk_star_mdio_write()
1428 of_node = dev->of_node; in mtk_star_mdio_init()
1432 return -ENODEV; in mtk_star_mdio_init()
1435 ret = -ENODEV; in mtk_star_mdio_init()
1439 priv->mii = devm_mdiobus_alloc(dev); in mtk_star_mdio_init()
1440 if (!priv->mii) { in mtk_star_mdio_init()
1441 ret = -ENOMEM; in mtk_star_mdio_init()
1445 snprintf(priv->mii->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); in mtk_star_mdio_init()
1446 priv->mii->name = "mtk-mac-mdio"; in mtk_star_mdio_init()
1447 priv->mii->parent = dev; in mtk_star_mdio_init()
1448 priv->mii->read = mtk_star_mdio_read; in mtk_star_mdio_init()
1449 priv->mii->write = mtk_star_mdio_write; in mtk_star_mdio_init()
1450 priv->mii->priv = priv; in mtk_star_mdio_init()
1452 ret = devm_of_mdiobus_register(dev, priv->mii, mdio_node); in mtk_star_mdio_init()
1470 clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); in mtk_star_suspend()
1484 ret = clk_bulk_prepare_enable(MTK_STAR_NCLKS, priv->clks); in mtk_star_resume()
1491 clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); in mtk_star_resume()
1501 clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); in mtk_star_clk_disable_unprepare()
1509 switch (priv->phy_intf) { in mtk_star_set_timing()
1512 delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); in mtk_star_set_timing()
1513 delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); in mtk_star_set_timing()
1517 return -EINVAL; in mtk_star_set_timing()
1520 return regmap_write(priv->regs, MTK_STAR_REG_TEST0, delay_val); in mtk_star_set_timing()
1533 dev = &pdev->dev; in mtk_star_probe()
1534 of_node = dev->of_node; in mtk_star_probe()
1538 return -ENOMEM; in mtk_star_probe()
1541 priv->ndev = ndev; in mtk_star_probe()
1542 priv->compat_data = of_device_get_match_data(&pdev->dev); in mtk_star_probe()
1546 ndev->min_mtu = ETH_ZLEN; in mtk_star_probe()
1547 ndev->max_mtu = MTK_STAR_MAX_FRAME_SIZE; in mtk_star_probe()
1549 spin_lock_init(&priv->lock); in mtk_star_probe()
1559 priv->regs = devm_regmap_init_mmio(dev, base, in mtk_star_probe()
1561 if (IS_ERR(priv->regs)) in mtk_star_probe()
1562 return PTR_ERR(priv->regs); in mtk_star_probe()
1564 priv->pericfg = syscon_regmap_lookup_by_phandle(of_node, in mtk_star_probe()
1566 if (IS_ERR(priv->pericfg)) { in mtk_star_probe()
1568 return PTR_ERR(priv->pericfg); in mtk_star_probe()
1571 ndev->irq = platform_get_irq(pdev, 0); in mtk_star_probe()
1572 if (ndev->irq < 0) in mtk_star_probe()
1573 return ndev->irq; in mtk_star_probe()
1576 priv->clks[i].id = mtk_star_clk_names[i]; in mtk_star_probe()
1577 ret = devm_clk_bulk_get(dev, MTK_STAR_NCLKS, priv->clks); in mtk_star_probe()
1581 ret = clk_bulk_prepare_enable(MTK_STAR_NCLKS, priv->clks); in mtk_star_probe()
1590 ret = of_get_phy_mode(of_node, &priv->phy_intf); in mtk_star_probe()
1593 } else if (priv->phy_intf != PHY_INTERFACE_MODE_RMII && in mtk_star_probe()
1594 priv->phy_intf != PHY_INTERFACE_MODE_MII) { in mtk_star_probe()
1596 phy_modes(priv->phy_intf)); in mtk_star_probe()
1597 return -EINVAL; in mtk_star_probe()
1600 priv->phy_node = of_parse_phandle(of_node, "phy-handle", 0); in mtk_star_probe()
1601 if (!priv->phy_node) { in mtk_star_probe()
1603 return -ENODEV; in mtk_star_probe()
1606 priv->rmii_rxc = of_property_read_bool(of_node, "mediatek,rmii-rxc"); in mtk_star_probe()
1607 priv->rx_inv = of_property_read_bool(of_node, "mediatek,rxc-inverse"); in mtk_star_probe()
1608 priv->tx_inv = of_property_read_bool(of_node, "mediatek,txc-inverse"); in mtk_star_probe()
1610 if (priv->compat_data->set_interface_mode) { in mtk_star_probe()
1611 ret = priv->compat_data->set_interface_mode(ndev); in mtk_star_probe()
1614 return -EINVAL; in mtk_star_probe()
1621 return -EINVAL; in mtk_star_probe()
1630 priv->ring_base = dmam_alloc_coherent(dev, MTK_STAR_DMA_SIZE, in mtk_star_probe()
1631 &priv->dma_addr, in mtk_star_probe()
1633 if (!priv->ring_base) in mtk_star_probe()
1634 return -ENOMEM; in mtk_star_probe()
1644 if (ret || !is_valid_ether_addr(ndev->dev_addr)) in mtk_star_probe()
1647 ndev->netdev_ops = &mtk_star_netdev_ops; in mtk_star_probe()
1648 ndev->ethtool_ops = &mtk_star_ethtool_ops; in mtk_star_probe()
1650 netif_napi_add(ndev, &priv->rx_napi, mtk_star_rx_poll); in mtk_star_probe()
1651 netif_napi_add_tx(ndev, &priv->tx_napi, mtk_star_tx_poll); in mtk_star_probe()
1653 phydev = of_phy_find_device(priv->phy_node); in mtk_star_probe()
1655 phydev->mac_managed_pm = true; in mtk_star_probe()
1656 put_device(&phydev->mdio.dev); in mtk_star_probe()
1669 switch (priv->phy_intf) { in mt8516_set_interface_mode()
1676 rmii_rxc = priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK; in mt8516_set_interface_mode()
1680 return -EINVAL; in mt8516_set_interface_mode()
1683 ret = regmap_update_bits(priv->pericfg, in mt8516_set_interface_mode()
1690 return regmap_update_bits(priv->pericfg, in mt8516_set_interface_mode()
1702 switch (priv->phy_intf) { in mt8365_set_interface_mode()
1708 intf_val |= priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2; in mt8365_set_interface_mode()
1712 return -EINVAL; in mt8365_set_interface_mode()
1715 return regmap_update_bits(priv->pericfg, in mt8365_set_interface_mode()
1733 { .compatible = "mediatek,mt8516-eth",
1735 { .compatible = "mediatek,mt8518-eth",
1737 { .compatible = "mediatek,mt8175-eth",
1739 { .compatible = "mediatek,mt8365-eth",