Lines Matching +full:0 +full:x10300
26 #define MTK_DSA_PORT_MASK GENMASK(2, 0)
32 #define MTK_TX_DMA_BUF_LEN 0x3fff
33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff
40 #define MTK_DMA_DUMMY_DESC 0xffffffff
64 #define MTK_QRX_OFFSET 0x10
81 #define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
85 #define MTK_RST_GL 0x04
86 #define RST_GL_PSE BIT(0)
89 #define MTK_INT_STATUS2 0x08
90 #define MTK_FE_INT_ENABLE 0x0c
101 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
104 #define MTK_FE_INT_GRP 0x20
107 #define MTK_CDMQ_IG_CTRL 0x1400
108 #define MTK_CDMQ_STAG_EN BIT(0)
111 #define MTK_CDMQ_EG_CTRL 0x1404
114 #define MTK_CDMP_IG_CTRL 0x400
115 #define MTK_CDMP_STAG_EN BIT(0)
118 #define MTK_CDMP_EG_CTRL 0x404
122 0x540 : 0x500 + (_x * 0x1000); })
128 #define MTK_GDMA_TO_PDMA 0x0
129 #define MTK_GDMA_DROP_ALL 0x7777
133 0x544 : 0x504 + (_x * 0x1000); })
138 0x548 : 0x508 + (_x * 0x1000); })
142 0x54C : 0x50C + (_x * 0x1000); })
145 #define MTK_ETH_SRAM_OFFSET 0x40000
148 #define MTK_FE_GLO_MISC 0x124
151 #define PSE_FQFC_CFG1 0x100
152 #define PSE_FQFC_CFG2 0x104
153 #define PSE_DROP_CFG 0x108
154 #define PSE_PPE0_DROP 0x110
157 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
160 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2))
163 #define MTK_GDM2_THRES 0x1530
164 #define MTK_CDMW0_THRES 0x164c
165 #define MTK_CDMW1_THRES 0x1650
166 #define MTK_CDME0_THRES 0x1654
167 #define MTK_CDME1_THRES 0x1658
168 #define MTK_CDMM_THRES 0x165c
171 #define MTK_PDMA_LRO_CTRL_DW0 0x980
172 #define MTK_LRO_EN BIT(0)
176 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
177 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24)
178 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
179 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28)
181 #define MTK_PDMA_LRO_CTRL_DW1 0x984
182 #define MTK_PDMA_LRO_CTRL_DW2 0x988
183 #define MTK_PDMA_LRO_CTRL_DW3 0x98c
192 #define MTK_PDMA_LRO_SDL 0x3000
200 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
203 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0
210 #define MTK_PDMA_DELAY_PINT_MASK 0x7f
211 #define MTK_PDMA_DELAY_PTIME_MASK 0xff
214 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
217 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04
218 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
222 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
223 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
224 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
225 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
226 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
227 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
228 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
229 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
232 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
233 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
234 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
237 #define MTK_QTX_OFFSET 0x10
252 #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0)
266 #define MTK_TX_DMA_EN BIT(0)
273 #define MTK_RESV_BUF (0x40 << 16)
274 #define MTK_MUTLI_CNT (0x4 << 12)
280 #define FC_THRES_MIN 0x4444
292 #define MTK_TX_DONE_INT0 BIT(0)
301 #define MTK_RLS_DONE_INT BIT(0)
304 #define QID_BITS_V2(x) (((x) & 0x3f) << 16)
312 #define TX_DMA_CHKSUM_V2 (0x7 << 28)
319 #define TX_DMA_FPORT_MASK_V2 0xf
323 #define TX_DMA_CHKSUM (0x7 << 29)
326 #define TX_DMA_FPORT_MASK 0x7
335 #define TX_DMA_PQID GENMASK(3, 0)
336 #define TX_DMA_ADDR64_MASK GENMASK(3, 0)
341 # define TX_DMA_GET_ADDR64(x) (0)
342 # define TX_DMA_PREP_ADDR64(x) (0)
356 #define RX_DMA_ADDR64_MASK GENMASK(3, 0)
361 # define RX_DMA_GET_ADDR64(x) (0)
362 # define RX_DMA_PREP_ADDR64(x) (0)
368 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff)
371 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
382 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0)
386 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7)
387 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf)
390 #define RX_DMA_VTAG_V2 BIT(0)
394 #define MTK_PPSC 0x10000
401 #define MTK_PHY_IAC 0x10004
408 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
413 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
415 #define PHY_IAC_DATA_MASK GENMASK(15, 0)
419 #define MTK_MAC_MISC 0x1000c
420 #define MTK_MAC_MISC_V3 0x10010
421 #define MTK_MUX_TO_ESW BIT(0)
425 #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
431 #define MTK_XGMAC_LINK_STS BIT(0)
434 #define MTK_GSW_CFG (0x10080)
437 #define GSWRX_IPG_MASK GENMASK(3, 0)
438 #define GSWRX_IPG_SHIFT 0
442 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
445 #define MAC_MCR_MAX_RX_1518 0x0
446 #define MAC_MCR_MAX_RX_1536 0x1
447 #define MAC_MCR_MAX_RX_1552 0x2
448 #define MAC_MCR_MAX_RX_2048 0x3
461 #define MAC_MCR_FORCE_LINK BIT(0)
465 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
474 #define MAC_MSR_LINK BIT(0)
477 #define TRGMII_RCK_CTRL 0x10300
478 #define DQSI0(x) ((x << 0) & GENMASK(6, 0))
489 #define TRGMII_TCK_CTRL 0x10340
496 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
497 #define TD_DM_DRVP(x) ((x) & 0xf)
498 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
501 #define INTF_MODE 0x10390
502 #define TRGMII_INTF_DIS BIT(0)
506 #define INTF_MODE_RGMII_10_100 0
509 #define GPIO_OD33_CTRL8 0x4c0
510 #define GPIO_BIAS_CTRL 0xed0
511 #define GPIO_DRV_SEL10 0xf00
514 #define ETHSYS_CHIPID0_3 0x0
515 #define ETHSYS_CHIPID4_7 0x4
521 #define ETHSYS_SYSCFG 0x10
525 #define ETHSYS_SYSCFG0 0x14
526 #define SYSCFG0_GE_MASK 0x3
536 #define ETHSYS_CLKCFG0 0x2c
543 #define ETHSYS_RSTCTRL 0x34
557 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
560 #define ETHSYS_DMA_AG_MAP 0x408
561 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
566 #define INFRA_MISC2 0x70c
567 #define CO_QPHY_SEL BIT(0)
571 #define USB_PHY_SWITCH_REG 0x218
572 #define QPHY_SEL_MASK GENMASK(1, 0)
573 #define SGMII_QPHY_SEL 0x2
576 #define MT7628_PDMA_OFFSET 0x0800
577 #define MT7628_SDM_OFFSET 0x0c00
579 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
580 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
581 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
582 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
583 #define MT7628_PST_DTX_IDX0 BIT(0)
585 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
586 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
589 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100)
590 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104)
591 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108)
592 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
593 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
595 #define MTK_FE_CDM1_FSM 0x220
596 #define MTK_FE_CDM2_FSM 0x224
597 #define MTK_FE_CDM3_FSM 0x238
598 #define MTK_FE_CDM4_FSM 0x298
599 #define MTK_FE_CDM5_FSM 0x318
600 #define MTK_FE_CDM6_FSM 0x328
601 #define MTK_FE_GDM1_FSM 0x228
602 #define MTK_FE_GDM2_FSM 0x22C
604 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
689 MTK_TX_FLAGS_SINGLE0 = 0x01,
690 MTK_TX_FLAGS_PAGE0 = 0x02,
756 #define MT7621_CLKS_BITMAP (0)
757 #define MT7628_CLKS_BITMAP (0)
822 PSE_ADMA_PORT = 0,
843 MTK_GMAC1_ID = 0,
903 MTK_RX_FLAGS_NORMAL = 0,
932 MTK_RGMII_BIT = 0,
1017 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
1020 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
1024 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
1033 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */