Lines Matching +full:mt7622 +full:- +full:sgmiisys
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
294 __raw_writel(val, eth->base + reg); in mtk_w32()
299 return __raw_readl(eth->base + reg); in mtk_r32()
325 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
326 return -ETIMEDOUT; in mtk_mdio_busy_wait()
449 struct mtk_eth *eth = bus->priv; in mtk_mdio_write_c22()
457 struct mtk_eth *eth = bus->priv; in mtk_mdio_write_c45()
464 struct mtk_eth *eth = bus->priv; in mtk_mdio_read_c22()
472 struct mtk_eth *eth = bus->priv; in mtk_mdio_read_c45()
485 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, in mt7621_gmac0_rgmii_adjust()
498 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); in mtk_gmac0_rgmii_adjust()
500 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); in mtk_gmac0_rgmii_adjust()
504 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); in mtk_gmac0_rgmii_adjust()
525 struct mtk_eth *eth = mac->hw; in mtk_mac_select_pcs()
530 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? in mtk_mac_select_pcs()
531 0 : mac->id; in mtk_mac_select_pcs()
533 return eth->sgmii_pcs[sid]; in mtk_mac_select_pcs()
544 struct mtk_eth *eth = mac->hw; in mtk_mac_config()
549 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && in mtk_mac_config()
550 mac->interface != state->interface) { in mtk_mac_config()
552 switch (state->interface) { in mtk_mac_config()
559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { in mtk_mac_config()
560 err = mtk_gmac_rgmii_path_setup(eth, mac->id); in mtk_mac_config()
568 err = mtk_gmac_sgmii_path_setup(eth, mac->id); in mtk_mac_config()
573 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { in mtk_mac_config()
574 err = mtk_gmac_gephy_path_setup(eth, mac->id); in mtk_mac_config()
586 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && in mtk_mac_config()
587 !phy_interface_mode_is_8023z(state->interface) && in mtk_mac_config()
588 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { in mtk_mac_config()
589 if (MTK_HAS_CAPS(mac->hw->soc->caps, in mtk_mac_config()
591 if (mt7621_gmac0_rgmii_adjust(mac->hw, in mtk_mac_config()
592 state->interface)) in mtk_mac_config()
595 mtk_gmac0_rgmii_adjust(mac->hw, in mtk_mac_config()
596 state->interface); in mtk_mac_config()
600 mtk_w32(mac->hw, in mtk_mac_config()
605 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, in mtk_mac_config()
607 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); in mtk_mac_config()
611 switch (state->interface) { in mtk_mac_config()
622 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
623 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); in mtk_mac_config()
624 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); in mtk_mac_config()
625 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); in mtk_mac_config()
627 mac->interface = state->interface; in mtk_mac_config()
631 if (state->interface == PHY_INTERFACE_MODE_SGMII || in mtk_mac_config()
632 phy_interface_mode_is_8023z(state->interface)) { in mtk_mac_config()
633 /* The path GMAC to SGMII will be enabled once the SGMIISYS is in mtk_mac_config()
636 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
638 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_config()
643 mac->syscfg0 = val; in mtk_mac_config()
645 dev_err(eth->dev, in mtk_mac_config()
646 "In-band mode not supported in non SGMII mode!\n"); in mtk_mac_config()
652 mac->interface == PHY_INTERFACE_MODE_INTERNAL) { in mtk_mac_config()
653 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); in mtk_mac_config()
654 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); in mtk_mac_config()
662 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, in mtk_mac_config()
663 mac->id, phy_modes(state->interface)); in mtk_mac_config()
667 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, in mtk_mac_config()
668 mac->id, phy_modes(state->interface), err); in mtk_mac_config()
676 struct mtk_eth *eth = mac->hw; in mtk_mac_finish()
682 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_finish()
683 SYSCFG0_SGMII_MASK, mac->syscfg0); in mtk_mac_finish()
686 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); in mtk_mac_finish()
693 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); in mtk_mac_finish()
703 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); in mtk_mac_link_down()
706 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); in mtk_mac_link_down()
712 const struct mtk_soc_data *soc = eth->soc; in mtk_set_queue_speed()
715 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) in mtk_set_queue_speed()
775 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); in mtk_set_queue_speed()
787 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); in mtk_mac_link_up()
793 mac->speed = speed; in mtk_mac_link_up()
808 /* Configure pause modes - phylink will avoid these for half duplex */ in mtk_mac_link_up()
815 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); in mtk_mac_link_up()
833 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); in mtk_mdio_init()
835 dev_err(eth->dev, "no %s child node found", "mdio-bus"); in mtk_mdio_init()
836 return -ENODEV; in mtk_mdio_init()
840 ret = -ENODEV; in mtk_mdio_init()
844 eth->mii_bus = devm_mdiobus_alloc(eth->dev); in mtk_mdio_init()
845 if (!eth->mii_bus) { in mtk_mdio_init()
846 ret = -ENOMEM; in mtk_mdio_init()
850 eth->mii_bus->name = "mdio"; in mtk_mdio_init()
851 eth->mii_bus->read = mtk_mdio_read_c22; in mtk_mdio_init()
852 eth->mii_bus->write = mtk_mdio_write_c22; in mtk_mdio_init()
853 eth->mii_bus->read_c45 = mtk_mdio_read_c45; in mtk_mdio_init()
854 eth->mii_bus->write_c45 = mtk_mdio_write_c45; in mtk_mdio_init()
855 eth->mii_bus->priv = eth; in mtk_mdio_init()
856 eth->mii_bus->parent = eth->dev; in mtk_mdio_init()
858 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); in mtk_mdio_init()
860 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { in mtk_mdio_init()
862 dev_err(eth->dev, "MDIO clock frequency out of range"); in mtk_mdio_init()
863 ret = -EINVAL; in mtk_mdio_init()
880 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); in mtk_mdio_init()
882 ret = of_mdiobus_register(eth->mii_bus, mii_np); in mtk_mdio_init()
891 if (!eth->mii_bus) in mtk_mdio_cleanup()
894 mdiobus_unregister(eth->mii_bus); in mtk_mdio_cleanup()
902 spin_lock_irqsave(ð->tx_irq_lock, flags); in mtk_tx_irq_disable()
903 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); in mtk_tx_irq_disable()
904 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); in mtk_tx_irq_disable()
905 spin_unlock_irqrestore(ð->tx_irq_lock, flags); in mtk_tx_irq_disable()
913 spin_lock_irqsave(ð->tx_irq_lock, flags); in mtk_tx_irq_enable()
914 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); in mtk_tx_irq_enable()
915 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); in mtk_tx_irq_enable()
916 spin_unlock_irqrestore(ð->tx_irq_lock, flags); in mtk_tx_irq_enable()
924 spin_lock_irqsave(ð->rx_irq_lock, flags); in mtk_rx_irq_disable()
925 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_disable()
926 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_disable()
927 spin_unlock_irqrestore(ð->rx_irq_lock, flags); in mtk_rx_irq_disable()
935 spin_lock_irqsave(ð->rx_irq_lock, flags); in mtk_rx_irq_enable()
936 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_enable()
937 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); in mtk_rx_irq_enable()
938 spin_unlock_irqrestore(ð->rx_irq_lock, flags); in mtk_rx_irq_enable()
945 struct mtk_eth *eth = mac->hw; in mtk_set_mac_address()
946 const char *macaddr = dev->dev_addr; in mtk_set_mac_address()
951 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_set_mac_address()
952 return -EBUSY; in mtk_set_mac_address()
954 spin_lock_bh(&mac->hw->page_lock); in mtk_set_mac_address()
955 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_set_mac_address()
956 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
958 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | in mtk_set_mac_address()
962 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
963 MTK_GDMA_MAC_ADRH(mac->id)); in mtk_set_mac_address()
964 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | in mtk_set_mac_address()
966 MTK_GDMA_MAC_ADRL(mac->id)); in mtk_set_mac_address()
968 spin_unlock_bh(&mac->hw->page_lock); in mtk_set_mac_address()
975 struct mtk_hw_stats *hw_stats = mac->hw_stats; in mtk_stats_update_mac()
976 struct mtk_eth *eth = mac->hw; in mtk_stats_update_mac()
978 u64_stats_update_begin(&hw_stats->syncp); in mtk_stats_update_mac()
980 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_stats_update_mac()
981 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); in mtk_stats_update_mac()
982 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); in mtk_stats_update_mac()
983 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); in mtk_stats_update_mac()
984 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); in mtk_stats_update_mac()
985 hw_stats->rx_checksum_errors += in mtk_stats_update_mac()
986 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); in mtk_stats_update_mac()
988 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_stats_update_mac()
989 unsigned int offs = hw_stats->reg_offset; in mtk_stats_update_mac()
992 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); in mtk_stats_update_mac()
993 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); in mtk_stats_update_mac()
995 hw_stats->rx_bytes += (stats << 32); in mtk_stats_update_mac()
996 hw_stats->rx_packets += in mtk_stats_update_mac()
997 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); in mtk_stats_update_mac()
998 hw_stats->rx_overflow += in mtk_stats_update_mac()
999 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); in mtk_stats_update_mac()
1000 hw_stats->rx_fcs_errors += in mtk_stats_update_mac()
1001 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); in mtk_stats_update_mac()
1002 hw_stats->rx_short_errors += in mtk_stats_update_mac()
1003 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); in mtk_stats_update_mac()
1004 hw_stats->rx_long_errors += in mtk_stats_update_mac()
1005 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); in mtk_stats_update_mac()
1006 hw_stats->rx_checksum_errors += in mtk_stats_update_mac()
1007 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); in mtk_stats_update_mac()
1008 hw_stats->rx_flow_control_packets += in mtk_stats_update_mac()
1009 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); in mtk_stats_update_mac()
1012 hw_stats->tx_skip += in mtk_stats_update_mac()
1013 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); in mtk_stats_update_mac()
1014 hw_stats->tx_collisions += in mtk_stats_update_mac()
1015 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); in mtk_stats_update_mac()
1016 hw_stats->tx_bytes += in mtk_stats_update_mac()
1017 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); in mtk_stats_update_mac()
1018 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); in mtk_stats_update_mac()
1020 hw_stats->tx_bytes += (stats << 32); in mtk_stats_update_mac()
1021 hw_stats->tx_packets += in mtk_stats_update_mac()
1022 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); in mtk_stats_update_mac()
1024 hw_stats->tx_skip += in mtk_stats_update_mac()
1025 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); in mtk_stats_update_mac()
1026 hw_stats->tx_collisions += in mtk_stats_update_mac()
1027 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); in mtk_stats_update_mac()
1028 hw_stats->tx_bytes += in mtk_stats_update_mac()
1029 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); in mtk_stats_update_mac()
1030 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); in mtk_stats_update_mac()
1032 hw_stats->tx_bytes += (stats << 32); in mtk_stats_update_mac()
1033 hw_stats->tx_packets += in mtk_stats_update_mac()
1034 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); in mtk_stats_update_mac()
1038 u64_stats_update_end(&hw_stats->syncp); in mtk_stats_update_mac()
1046 if (!eth->mac[i] || !eth->mac[i]->hw_stats) in mtk_stats_update()
1048 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { in mtk_stats_update()
1049 mtk_stats_update_mac(eth->mac[i]); in mtk_stats_update()
1050 spin_unlock(ð->mac[i]->hw_stats->stats_lock); in mtk_stats_update()
1059 struct mtk_hw_stats *hw_stats = mac->hw_stats; in mtk_get_stats64()
1063 if (spin_trylock_bh(&hw_stats->stats_lock)) { in mtk_get_stats64()
1065 spin_unlock_bh(&hw_stats->stats_lock); in mtk_get_stats64()
1070 start = u64_stats_fetch_begin(&hw_stats->syncp); in mtk_get_stats64()
1071 storage->rx_packets = hw_stats->rx_packets; in mtk_get_stats64()
1072 storage->tx_packets = hw_stats->tx_packets; in mtk_get_stats64()
1073 storage->rx_bytes = hw_stats->rx_bytes; in mtk_get_stats64()
1074 storage->tx_bytes = hw_stats->tx_bytes; in mtk_get_stats64()
1075 storage->collisions = hw_stats->tx_collisions; in mtk_get_stats64()
1076 storage->rx_length_errors = hw_stats->rx_short_errors + in mtk_get_stats64()
1077 hw_stats->rx_long_errors; in mtk_get_stats64()
1078 storage->rx_over_errors = hw_stats->rx_overflow; in mtk_get_stats64()
1079 storage->rx_crc_errors = hw_stats->rx_fcs_errors; in mtk_get_stats64()
1080 storage->rx_errors = hw_stats->rx_checksum_errors; in mtk_get_stats64()
1081 storage->tx_aborted_errors = hw_stats->tx_skip; in mtk_get_stats64()
1082 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); in mtk_get_stats64()
1084 storage->tx_errors = dev->stats.tx_errors; in mtk_get_stats64()
1085 storage->rx_dropped = dev->stats.rx_dropped; in mtk_get_stats64()
1086 storage->tx_dropped = dev->stats.tx_dropped; in mtk_get_stats64()
1093 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; in mtk_max_frag_size()
1101 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - in mtk_max_buf_size()
1112 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); in mtk_rx_get_desc()
1113 if (!(rxd->rxd2 & RX_DMA_DONE)) in mtk_rx_get_desc()
1116 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); in mtk_rx_get_desc()
1117 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); in mtk_rx_get_desc()
1118 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); in mtk_rx_get_desc()
1120 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); in mtk_rx_get_desc()
1121 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); in mtk_rx_get_desc()
1141 const struct mtk_soc_data *soc = eth->soc; in mtk_init_fq_dma()
1143 int cnt = soc->tx.fq_dma_size; in mtk_init_fq_dma()
1147 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) in mtk_init_fq_dma()
1148 eth->scratch_ring = eth->sram_base; in mtk_init_fq_dma()
1150 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, in mtk_init_fq_dma()
1151 cnt * soc->tx.desc_size, in mtk_init_fq_dma()
1152 ð->phy_scratch_ring, in mtk_init_fq_dma()
1155 if (unlikely(!eth->scratch_ring)) in mtk_init_fq_dma()
1156 return -ENOMEM; in mtk_init_fq_dma()
1158 phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1); in mtk_init_fq_dma()
1160 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) { in mtk_init_fq_dma()
1161 len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH); in mtk_init_fq_dma()
1162 eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); in mtk_init_fq_dma()
1164 if (unlikely(!eth->scratch_head[j])) in mtk_init_fq_dma()
1165 return -ENOMEM; in mtk_init_fq_dma()
1167 dma_addr = dma_map_single(eth->dma_dev, in mtk_init_fq_dma()
1168 eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE, in mtk_init_fq_dma()
1171 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) in mtk_init_fq_dma()
1172 return -ENOMEM; in mtk_init_fq_dma()
1177 txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size; in mtk_init_fq_dma()
1178 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; in mtk_init_fq_dma()
1180 txd->txd2 = eth->phy_scratch_ring + in mtk_init_fq_dma()
1181 (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size; in mtk_init_fq_dma()
1183 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); in mtk_init_fq_dma()
1184 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA)) in mtk_init_fq_dma()
1185 txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE); in mtk_init_fq_dma()
1187 txd->txd4 = 0; in mtk_init_fq_dma()
1189 txd->txd5 = 0; in mtk_init_fq_dma()
1190 txd->txd6 = 0; in mtk_init_fq_dma()
1191 txd->txd7 = 0; in mtk_init_fq_dma()
1192 txd->txd8 = 0; in mtk_init_fq_dma()
1197 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); in mtk_init_fq_dma()
1198 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); in mtk_init_fq_dma()
1199 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); in mtk_init_fq_dma()
1200 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); in mtk_init_fq_dma()
1207 return ring->dma + (desc - ring->phys); in mtk_qdma_phys_to_virt()
1213 int idx = (txd - ring->dma) / txd_size; in mtk_desc_to_tx_buf()
1215 return &ring->buf[idx]; in mtk_desc_to_tx_buf()
1221 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; in qdma_to_pdma()
1226 return (dma - ring->dma) / txd_size; in txd_to_idx()
1232 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_tx_unmap()
1233 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { in mtk_tx_unmap()
1234 dma_unmap_single(eth->dma_dev, in mtk_tx_unmap()
1238 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { in mtk_tx_unmap()
1239 dma_unmap_page(eth->dma_dev, in mtk_tx_unmap()
1246 dma_unmap_page(eth->dma_dev, in mtk_tx_unmap()
1253 dma_unmap_page(eth->dma_dev, in mtk_tx_unmap()
1260 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { in mtk_tx_unmap()
1261 if (tx_buf->type == MTK_TYPE_SKB) { in mtk_tx_unmap()
1262 struct sk_buff *skb = tx_buf->data; in mtk_tx_unmap()
1269 struct xdp_frame *xdpf = tx_buf->data; in mtk_tx_unmap()
1271 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) in mtk_tx_unmap()
1279 tx_buf->flags = 0; in mtk_tx_unmap()
1280 tx_buf->data = NULL; in mtk_tx_unmap()
1287 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in setup_tx_buf()
1292 txd->txd3 = mapped_addr; in setup_tx_buf()
1293 txd->txd2 |= TX_DMA_PLEN1(size); in setup_tx_buf()
1297 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; in setup_tx_buf()
1298 txd->txd1 = mapped_addr; in setup_tx_buf()
1299 txd->txd2 = TX_DMA_PLEN0(size); in setup_tx_buf()
1310 struct mtk_eth *eth = mac->hw; in mtk_tx_set_dma_desc_v1()
1314 WRITE_ONCE(desc->txd1, info->addr); in mtk_tx_set_dma_desc_v1()
1316 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | in mtk_tx_set_dma_desc_v1()
1317 FIELD_PREP(TX_DMA_PQID, info->qid); in mtk_tx_set_dma_desc_v1()
1318 if (info->last) in mtk_tx_set_dma_desc_v1()
1320 WRITE_ONCE(desc->txd3, data); in mtk_tx_set_dma_desc_v1()
1322 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ in mtk_tx_set_dma_desc_v1()
1323 if (info->first) { in mtk_tx_set_dma_desc_v1()
1324 if (info->gso) in mtk_tx_set_dma_desc_v1()
1327 if (info->csum) in mtk_tx_set_dma_desc_v1()
1330 if (info->vlan) in mtk_tx_set_dma_desc_v1()
1331 data |= TX_DMA_INS_VLAN | info->vlan_tci; in mtk_tx_set_dma_desc_v1()
1333 WRITE_ONCE(desc->txd4, data); in mtk_tx_set_dma_desc_v1()
1341 struct mtk_eth *eth = mac->hw; in mtk_tx_set_dma_desc_v2()
1344 WRITE_ONCE(desc->txd1, info->addr); in mtk_tx_set_dma_desc_v2()
1346 data = TX_DMA_PLEN0(info->size); in mtk_tx_set_dma_desc_v2()
1347 if (info->last) in mtk_tx_set_dma_desc_v2()
1350 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) in mtk_tx_set_dma_desc_v2()
1351 data |= TX_DMA_PREP_ADDR64(info->addr); in mtk_tx_set_dma_desc_v2()
1353 WRITE_ONCE(desc->txd3, data); in mtk_tx_set_dma_desc_v2()
1356 switch (mac->id) { in mtk_tx_set_dma_desc_v2()
1368 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); in mtk_tx_set_dma_desc_v2()
1369 WRITE_ONCE(desc->txd4, data); in mtk_tx_set_dma_desc_v2()
1372 if (info->first) { in mtk_tx_set_dma_desc_v2()
1373 if (info->gso) in mtk_tx_set_dma_desc_v2()
1376 if (info->csum) in mtk_tx_set_dma_desc_v2()
1381 WRITE_ONCE(desc->txd5, data); in mtk_tx_set_dma_desc_v2()
1384 if (info->first && info->vlan) in mtk_tx_set_dma_desc_v2()
1385 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; in mtk_tx_set_dma_desc_v2()
1386 WRITE_ONCE(desc->txd6, data); in mtk_tx_set_dma_desc_v2()
1388 WRITE_ONCE(desc->txd7, 0); in mtk_tx_set_dma_desc_v2()
1389 WRITE_ONCE(desc->txd8, 0); in mtk_tx_set_dma_desc_v2()
1396 struct mtk_eth *eth = mac->hw; in mtk_tx_set_dma_desc()
1410 .csum = skb->ip_summed == CHECKSUM_PARTIAL, in mtk_tx_map()
1419 struct mtk_eth *eth = mac->hw; in mtk_tx_map()
1420 const struct mtk_soc_data *soc = eth->soc; in mtk_tx_map()
1429 itxd = ring->next_free; in mtk_tx_map()
1431 if (itxd == ring->last_free) in mtk_tx_map()
1432 return -ENOMEM; in mtk_tx_map()
1434 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); in mtk_tx_map()
1437 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, in mtk_tx_map()
1439 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) in mtk_tx_map()
1440 return -ENOMEM; in mtk_tx_map()
1444 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; in mtk_tx_map()
1445 itx_buf->mac_id = mac->id; in mtk_tx_map()
1453 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_tx_map()
1454 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in mtk_tx_map()
1461 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || in mtk_tx_map()
1463 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); in mtk_tx_map()
1465 if (txd == ring->last_free) in mtk_tx_map()
1475 soc->tx.dma_max_len); in mtk_tx_map()
1477 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && in mtk_tx_map()
1478 !(frag_size - txd_info.size); in mtk_tx_map()
1479 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, in mtk_tx_map()
1482 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) in mtk_tx_map()
1488 soc->tx.desc_size); in mtk_tx_map()
1491 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; in mtk_tx_map()
1492 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; in mtk_tx_map()
1493 tx_buf->mac_id = mac->id; in mtk_tx_map()
1498 frag_size -= txd_info.size; in mtk_tx_map()
1504 itx_buf->type = MTK_TYPE_SKB; in mtk_tx_map()
1505 itx_buf->data = skb; in mtk_tx_map()
1507 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_tx_map()
1509 txd_pdma->txd2 |= TX_DMA_LS0; in mtk_tx_map()
1511 txd_pdma->txd2 |= TX_DMA_LS1; in mtk_tx_map()
1514 netdev_tx_sent_queue(txq, skb->len); in mtk_tx_map()
1517 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); in mtk_tx_map()
1518 atomic_sub(n_desc, &ring->free_count); in mtk_tx_map()
1525 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_tx_map()
1527 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); in mtk_tx_map()
1531 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size), in mtk_tx_map()
1532 ring->dma_size); in mtk_tx_map()
1540 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); in mtk_tx_map()
1545 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; in mtk_tx_map()
1546 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) in mtk_tx_map()
1547 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; in mtk_tx_map()
1549 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); in mtk_tx_map()
1553 return -ENOMEM; in mtk_tx_map()
1562 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_cal_txd_req()
1563 frag = &skb_shinfo(skb)->frags[i]; in mtk_cal_txd_req()
1565 eth->soc->tx.dma_max_len); in mtk_cal_txd_req()
1568 nfrags += skb_shinfo(skb)->nr_frags; in mtk_cal_txd_req()
1579 if (!eth->netdev[i]) in mtk_queue_stopped()
1581 if (netif_queue_stopped(eth->netdev[i])) in mtk_queue_stopped()
1593 if (!eth->netdev[i]) in mtk_wake_queue()
1595 netif_tx_wake_all_queues(eth->netdev[i]); in mtk_wake_queue()
1602 struct mtk_eth *eth = mac->hw; in mtk_start_xmit()
1603 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_start_xmit()
1604 struct net_device_stats *stats = &dev->stats; in mtk_start_xmit()
1612 spin_lock(ð->page_lock); in mtk_start_xmit()
1614 if (unlikely(test_bit(MTK_RESETTING, ð->state))) in mtk_start_xmit()
1618 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { in mtk_start_xmit()
1622 spin_unlock(ð->page_lock); in mtk_start_xmit()
1634 if (skb_shinfo(skb)->gso_type & in mtk_start_xmit()
1637 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); in mtk_start_xmit()
1644 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) in mtk_start_xmit()
1647 spin_unlock(ð->page_lock); in mtk_start_xmit()
1652 spin_unlock(ð->page_lock); in mtk_start_xmit()
1653 stats->tx_dropped++; in mtk_start_xmit()
1664 if (!eth->hwlro) in mtk_get_rx_ring()
1665 return ð->rx_ring[0]; in mtk_get_rx_ring()
1670 ring = ð->rx_ring[i]; in mtk_get_rx_ring()
1671 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); in mtk_get_rx_ring()
1672 rxd = ring->dma + idx * eth->soc->rx.desc_size; in mtk_get_rx_ring()
1673 if (rxd->rxd2 & RX_DMA_DONE) { in mtk_get_rx_ring()
1674 ring->calc_idx_update = true; in mtk_get_rx_ring()
1687 if (!eth->hwlro) { in mtk_update_rx_cpu_idx()
1688 ring = ð->rx_ring[0]; in mtk_update_rx_cpu_idx()
1689 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); in mtk_update_rx_cpu_idx()
1692 ring = ð->rx_ring[i]; in mtk_update_rx_cpu_idx()
1693 if (ring->calc_idx_update) { in mtk_update_rx_cpu_idx()
1694 ring->calc_idx_update = false; in mtk_update_rx_cpu_idx()
1695 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); in mtk_update_rx_cpu_idx()
1715 .dev = eth->dma_dev, in mtk_create_page_pool()
1722 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL in mtk_create_page_pool()
1728 err = __xdp_rxq_info_reg(xdp_q, eth->dummy_dev, id, in mtk_create_page_pool()
1729 eth->rx_napi.napi_id, PAGE_SIZE); in mtk_create_page_pool()
1762 if (ring->page_pool) in mtk_rx_put_buff()
1763 page_pool_put_full_page(ring->page_pool, in mtk_rx_put_buff()
1774 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_xdp_frame_map()
1779 txd_info->addr = dma_map_single(eth->dma_dev, data, in mtk_xdp_frame_map()
1780 txd_info->size, DMA_TO_DEVICE); in mtk_xdp_frame_map()
1781 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) in mtk_xdp_frame_map()
1782 return -ENOMEM; in mtk_xdp_frame_map()
1784 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; in mtk_xdp_frame_map()
1788 txd_info->addr = page_pool_get_dma_addr(page) + in mtk_xdp_frame_map()
1790 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, in mtk_xdp_frame_map()
1791 txd_info->size, DMA_BIDIRECTIONAL); in mtk_xdp_frame_map()
1795 tx_buf->mac_id = mac->id; in mtk_xdp_frame_map()
1796 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; in mtk_xdp_frame_map()
1797 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; in mtk_xdp_frame_map()
1800 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, in mtk_xdp_frame_map()
1810 const struct mtk_soc_data *soc = eth->soc; in mtk_xdp_submit_frame()
1811 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_xdp_submit_frame()
1814 .size = xdpf->len, in mtk_xdp_submit_frame()
1817 .qid = mac->id, in mtk_xdp_submit_frame()
1822 void *data = xdpf->data; in mtk_xdp_submit_frame()
1824 if (unlikely(test_bit(MTK_RESETTING, ð->state))) in mtk_xdp_submit_frame()
1825 return -EBUSY; in mtk_xdp_submit_frame()
1827 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; in mtk_xdp_submit_frame()
1828 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) in mtk_xdp_submit_frame()
1829 return -EBUSY; in mtk_xdp_submit_frame()
1831 spin_lock(ð->page_lock); in mtk_xdp_submit_frame()
1833 txd = ring->next_free; in mtk_xdp_submit_frame()
1834 if (txd == ring->last_free) { in mtk_xdp_submit_frame()
1835 spin_unlock(ð->page_lock); in mtk_xdp_submit_frame()
1836 return -ENOMEM; in mtk_xdp_submit_frame()
1840 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size); in mtk_xdp_submit_frame()
1846 data, xdpf->headroom, index, dma_map); in mtk_xdp_submit_frame()
1853 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { in mtk_xdp_submit_frame()
1854 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); in mtk_xdp_submit_frame()
1855 if (txd == ring->last_free) in mtk_xdp_submit_frame()
1859 soc->tx.desc_size); in mtk_xdp_submit_frame()
1865 txd_info.size = skb_frag_size(&sinfo->frags[index]); in mtk_xdp_submit_frame()
1867 txd_info.qid = mac->id; in mtk_xdp_submit_frame()
1868 data = skb_frag_address(&sinfo->frags[index]); in mtk_xdp_submit_frame()
1873 htx_buf->data = xdpf; in mtk_xdp_submit_frame()
1875 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_xdp_submit_frame()
1879 txd_pdma->txd2 |= TX_DMA_LS0; in mtk_xdp_submit_frame()
1881 txd_pdma->txd2 |= TX_DMA_LS1; in mtk_xdp_submit_frame()
1884 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); in mtk_xdp_submit_frame()
1885 atomic_sub(n_desc, &ring->free_count); in mtk_xdp_submit_frame()
1892 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_xdp_submit_frame()
1893 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); in mtk_xdp_submit_frame()
1897 idx = txd_to_idx(ring, txd, soc->tx.desc_size); in mtk_xdp_submit_frame()
1898 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), in mtk_xdp_submit_frame()
1902 spin_unlock(ð->page_lock); in mtk_xdp_submit_frame()
1908 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size); in mtk_xdp_submit_frame()
1911 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; in mtk_xdp_submit_frame()
1912 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_xdp_submit_frame()
1915 txd_pdma->txd2 = TX_DMA_DESP2_DEF; in mtk_xdp_submit_frame()
1918 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); in mtk_xdp_submit_frame()
1921 spin_unlock(ð->page_lock); in mtk_xdp_submit_frame()
1930 struct mtk_hw_stats *hw_stats = mac->hw_stats; in mtk_xdp_xmit()
1931 struct mtk_eth *eth = mac->hw; in mtk_xdp_xmit()
1935 return -EINVAL; in mtk_xdp_xmit()
1943 u64_stats_update_begin(&hw_stats->syncp); in mtk_xdp_xmit()
1944 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; in mtk_xdp_xmit()
1945 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; in mtk_xdp_xmit()
1946 u64_stats_update_end(&hw_stats->syncp); in mtk_xdp_xmit()
1955 struct mtk_hw_stats *hw_stats = mac->hw_stats; in mtk_xdp_run()
1956 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; in mtk_xdp_run()
1962 prog = rcu_dereference(eth->prog); in mtk_xdp_run()
1969 count = &hw_stats->xdp_stats.rx_xdp_pass; in mtk_xdp_run()
1977 count = &hw_stats->xdp_stats.rx_xdp_redirect; in mtk_xdp_run()
1983 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; in mtk_xdp_run()
1988 count = &hw_stats->xdp_stats.rx_xdp_tx; in mtk_xdp_run()
2001 page_pool_put_full_page(ring->page_pool, in mtk_xdp_run()
2002 virt_to_head_page(xdp->data), true); in mtk_xdp_run()
2005 u64_stats_update_begin(&hw_stats->syncp); in mtk_xdp_run()
2007 u64_stats_update_end(&hw_stats->syncp); in mtk_xdp_run()
2039 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); in mtk_poll_rx()
2040 rxd = ring->dma + idx * eth->soc->rx.desc_size; in mtk_poll_rx()
2041 data = ring->data[idx]; in mtk_poll_rx()
2053 mac = val - 1; in mtk_poll_rx()
2061 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && in mtk_poll_rx()
2063 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; in mtk_poll_rx()
2067 !eth->netdev[mac])) in mtk_poll_rx()
2070 netdev = eth->netdev[mac]; in mtk_poll_rx()
2071 ppe_idx = eth->mac[mac]->ppe_idx; in mtk_poll_rx()
2073 if (unlikely(test_bit(MTK_RESETTING, ð->state))) in mtk_poll_rx()
2079 if (ring->page_pool) { in mtk_poll_rx()
2084 new_data = mtk_page_pool_get_buff(ring->page_pool, in mtk_poll_rx()
2088 netdev->stats.rx_dropped++; in mtk_poll_rx()
2092 dma_sync_single_for_cpu(eth->dma_dev, in mtk_poll_rx()
2094 pktlen, page_pool_get_dma_dir(ring->page_pool)); in mtk_poll_rx()
2096 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); in mtk_poll_rx()
2110 page_pool_put_full_page(ring->page_pool, in mtk_poll_rx()
2112 netdev->stats.rx_dropped++; in mtk_poll_rx()
2116 skb_reserve(skb, xdp.data - xdp.data_hard_start); in mtk_poll_rx()
2117 skb_put(skb, xdp.data_end - xdp.data); in mtk_poll_rx()
2120 if (ring->frag_size <= PAGE_SIZE) in mtk_poll_rx()
2121 new_data = napi_alloc_frag(ring->frag_size); in mtk_poll_rx()
2126 netdev->stats.rx_dropped++; in mtk_poll_rx()
2130 dma_addr = dma_map_single(eth->dma_dev, in mtk_poll_rx()
2131 new_data + NET_SKB_PAD + eth->ip_align, in mtk_poll_rx()
2132 ring->buf_size, DMA_FROM_DEVICE); in mtk_poll_rx()
2133 if (unlikely(dma_mapping_error(eth->dma_dev, in mtk_poll_rx()
2136 netdev->stats.rx_dropped++; in mtk_poll_rx()
2140 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) in mtk_poll_rx()
2143 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64), in mtk_poll_rx()
2144 ring->buf_size, DMA_FROM_DEVICE); in mtk_poll_rx()
2146 skb = build_skb(data, ring->frag_size); in mtk_poll_rx()
2148 netdev->stats.rx_dropped++; in mtk_poll_rx()
2157 skb->dev = netdev; in mtk_poll_rx()
2158 bytes += skb->len; in mtk_poll_rx()
2176 if (*rxdcsum & eth->soc->rx.dma_l4_valid) in mtk_poll_rx()
2177 skb->ip_summed = CHECKSUM_UNNECESSARY; in mtk_poll_rx()
2180 skb->protocol = eth_type_trans(skb, netdev); in mtk_poll_rx()
2189 if (port < ARRAY_SIZE(eth->dsa_meta) && in mtk_poll_rx()
2190 eth->dsa_meta[port]) in mtk_poll_rx()
2191 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); in mtk_poll_rx()
2195 mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash); in mtk_poll_rx()
2201 ring->data[idx] = new_data; in mtk_poll_rx()
2202 rxd->rxd1 = (unsigned int)dma_addr; in mtk_poll_rx()
2204 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_poll_rx()
2205 rxd->rxd2 = RX_DMA_LSO; in mtk_poll_rx()
2207 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); in mtk_poll_rx()
2209 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA) && in mtk_poll_rx()
2211 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); in mtk_poll_rx()
2213 ring->calc_idx = idx; in mtk_poll_rx()
2226 eth->rx_packets += done; in mtk_poll_rx()
2227 eth->rx_bytes += bytes; in mtk_poll_rx()
2228 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, in mtk_poll_rx()
2230 net_dim(ð->rx_dim, &dim_sample); in mtk_poll_rx()
2251 unsigned int bytes = skb->len; in mtk_poll_tx_done()
2253 state->total++; in mtk_poll_tx_done()
2254 eth->tx_packets++; in mtk_poll_tx_done()
2255 eth->tx_bytes += bytes; in mtk_poll_tx_done()
2257 dev = eth->netdev[mac]; in mtk_poll_tx_done()
2262 if (state->txq == txq) { in mtk_poll_tx_done()
2263 state->done++; in mtk_poll_tx_done()
2264 state->bytes += bytes; in mtk_poll_tx_done()
2268 if (state->txq) in mtk_poll_tx_done()
2269 netdev_tx_completed_queue(state->txq, state->done, state->bytes); in mtk_poll_tx_done()
2271 state->txq = txq; in mtk_poll_tx_done()
2272 state->done = 1; in mtk_poll_tx_done()
2273 state->bytes = bytes; in mtk_poll_tx_done()
2279 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_poll_tx_qdma()
2280 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_poll_tx_qdma()
2286 cpu = ring->last_free_ptr; in mtk_poll_tx_qdma()
2287 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); in mtk_poll_tx_qdma()
2293 u32 next_cpu = desc->txd2; in mtk_poll_tx_qdma()
2295 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); in mtk_poll_tx_qdma()
2296 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) in mtk_poll_tx_qdma()
2300 eth->soc->tx.desc_size); in mtk_poll_tx_qdma()
2301 if (!tx_buf->data) in mtk_poll_tx_qdma()
2304 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { in mtk_poll_tx_qdma()
2305 if (tx_buf->type == MTK_TYPE_SKB) in mtk_poll_tx_qdma()
2306 mtk_poll_tx_done(eth, state, tx_buf->mac_id, in mtk_poll_tx_qdma()
2307 tx_buf->data); in mtk_poll_tx_qdma()
2309 budget--; in mtk_poll_tx_qdma()
2313 ring->last_free = desc; in mtk_poll_tx_qdma()
2314 atomic_inc(&ring->free_count); in mtk_poll_tx_qdma()
2320 ring->last_free_ptr = cpu; in mtk_poll_tx_qdma()
2321 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); in mtk_poll_tx_qdma()
2329 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_poll_tx_pdma()
2335 cpu = ring->cpu_idx; in mtk_poll_tx_pdma()
2340 tx_buf = &ring->buf[cpu]; in mtk_poll_tx_pdma()
2341 if (!tx_buf->data) in mtk_poll_tx_pdma()
2344 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { in mtk_poll_tx_pdma()
2345 if (tx_buf->type == MTK_TYPE_SKB) in mtk_poll_tx_pdma()
2346 mtk_poll_tx_done(eth, state, 0, tx_buf->data); in mtk_poll_tx_pdma()
2347 budget--; in mtk_poll_tx_pdma()
2351 desc = ring->dma + cpu * eth->soc->tx.desc_size; in mtk_poll_tx_pdma()
2352 ring->last_free = desc; in mtk_poll_tx_pdma()
2353 atomic_inc(&ring->free_count); in mtk_poll_tx_pdma()
2355 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); in mtk_poll_tx_pdma()
2359 ring->cpu_idx = cpu; in mtk_poll_tx_pdma()
2366 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_poll_tx()
2370 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_poll_tx()
2378 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, in mtk_poll_tx()
2380 net_dim(ð->tx_dim, &dim_sample); in mtk_poll_tx()
2383 (atomic_read(&ring->free_count) > ring->thresh)) in mtk_poll_tx()
2403 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_napi_tx()
2406 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_napi_tx()
2408 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); in mtk_napi_tx()
2412 dev_info(eth->dev, in mtk_napi_tx()
2414 mtk_r32(eth, reg_map->tx_irq_status), in mtk_napi_tx()
2415 mtk_r32(eth, reg_map->tx_irq_mask)); in mtk_napi_tx()
2421 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) in mtk_napi_tx()
2433 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_napi_rx()
2441 mtk_w32(eth, eth->soc->rx.irq_done_mask, in mtk_napi_rx()
2442 reg_map->pdma.irq_status); in mtk_napi_rx()
2443 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); in mtk_napi_rx()
2447 dev_info(eth->dev, in mtk_napi_rx()
2449 mtk_r32(eth, reg_map->pdma.irq_status), in mtk_napi_rx()
2450 mtk_r32(eth, reg_map->pdma.irq_mask)); in mtk_napi_rx()
2456 } while (mtk_r32(eth, reg_map->pdma.irq_status) & in mtk_napi_rx()
2457 eth->soc->rx.irq_done_mask); in mtk_napi_rx()
2460 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); in mtk_napi_rx()
2467 const struct mtk_soc_data *soc = eth->soc; in mtk_tx_alloc()
2468 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_tx_alloc()
2469 int i, sz = soc->tx.desc_size; in mtk_tx_alloc()
2474 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) in mtk_tx_alloc()
2477 ring_size = soc->tx.dma_size; in mtk_tx_alloc()
2479 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), in mtk_tx_alloc()
2481 if (!ring->buf) in mtk_tx_alloc()
2484 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) { in mtk_tx_alloc()
2485 ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz; in mtk_tx_alloc()
2486 ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz; in mtk_tx_alloc()
2488 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, in mtk_tx_alloc()
2489 &ring->phys, GFP_KERNEL); in mtk_tx_alloc()
2492 if (!ring->dma) in mtk_tx_alloc()
2497 u32 next_ptr = ring->phys + next * sz; in mtk_tx_alloc()
2499 txd = ring->dma + i * sz; in mtk_tx_alloc()
2500 txd->txd2 = next_ptr; in mtk_tx_alloc()
2501 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; in mtk_tx_alloc()
2502 txd->txd4 = 0; in mtk_tx_alloc()
2504 txd->txd5 = 0; in mtk_tx_alloc()
2505 txd->txd6 = 0; in mtk_tx_alloc()
2506 txd->txd7 = 0; in mtk_tx_alloc()
2507 txd->txd8 = 0; in mtk_tx_alloc()
2511 /* On MT7688 (PDMA only) this driver uses the ring->dma structs in mtk_tx_alloc()
2513 * descriptors in ring->dma_pdma. in mtk_tx_alloc()
2515 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_tx_alloc()
2516 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, in mtk_tx_alloc()
2517 &ring->phys_pdma, GFP_KERNEL); in mtk_tx_alloc()
2518 if (!ring->dma_pdma) in mtk_tx_alloc()
2522 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; in mtk_tx_alloc()
2523 ring->dma_pdma[i].txd4 = 0; in mtk_tx_alloc()
2527 ring->dma_size = ring_size; in mtk_tx_alloc()
2528 atomic_set(&ring->free_count, ring_size - 2); in mtk_tx_alloc()
2529 ring->next_free = ring->dma; in mtk_tx_alloc()
2530 ring->last_free = (void *)txd; in mtk_tx_alloc()
2531 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); in mtk_tx_alloc()
2532 ring->thresh = MAX_SKB_FRAGS; in mtk_tx_alloc()
2539 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { in mtk_tx_alloc()
2540 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); in mtk_tx_alloc()
2541 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); in mtk_tx_alloc()
2543 ring->phys + ((ring_size - 1) * sz), in mtk_tx_alloc()
2544 soc->reg_map->qdma.crx_ptr); in mtk_tx_alloc()
2545 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); in mtk_tx_alloc()
2549 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); in mtk_tx_alloc()
2558 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); in mtk_tx_alloc()
2562 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); in mtk_tx_alloc()
2564 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); in mtk_tx_alloc()
2566 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); in mtk_tx_alloc()
2569 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); in mtk_tx_alloc()
2575 return -ENOMEM; in mtk_tx_alloc()
2580 const struct mtk_soc_data *soc = eth->soc; in mtk_tx_clean()
2581 struct mtk_tx_ring *ring = ð->tx_ring; in mtk_tx_clean()
2584 if (ring->buf) { in mtk_tx_clean()
2585 for (i = 0; i < ring->dma_size; i++) in mtk_tx_clean()
2586 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); in mtk_tx_clean()
2587 kfree(ring->buf); in mtk_tx_clean()
2588 ring->buf = NULL; in mtk_tx_clean()
2590 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { in mtk_tx_clean()
2591 dma_free_coherent(eth->dma_dev, in mtk_tx_clean()
2592 ring->dma_size * soc->tx.desc_size, in mtk_tx_clean()
2593 ring->dma, ring->phys); in mtk_tx_clean()
2594 ring->dma = NULL; in mtk_tx_clean()
2597 if (ring->dma_pdma) { in mtk_tx_clean()
2598 dma_free_coherent(eth->dma_dev, in mtk_tx_clean()
2599 ring->dma_size * soc->tx.desc_size, in mtk_tx_clean()
2600 ring->dma_pdma, ring->phys_pdma); in mtk_tx_clean()
2601 ring->dma_pdma = NULL; in mtk_tx_clean()
2607 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_rx_alloc()
2608 const struct mtk_soc_data *soc = eth->soc; in mtk_rx_alloc()
2613 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_rx_alloc()
2616 tx_ring_size = soc->tx.dma_size; in mtk_rx_alloc()
2620 return -EINVAL; in mtk_rx_alloc()
2621 ring = ð->rx_ring_qdma; in mtk_rx_alloc()
2623 ring = ð->rx_ring[ring_no]; in mtk_rx_alloc()
2631 rx_dma_size = soc->rx.dma_size; in mtk_rx_alloc()
2634 ring->frag_size = mtk_max_frag_size(rx_data_len); in mtk_rx_alloc()
2635 ring->buf_size = mtk_max_buf_size(ring->frag_size); in mtk_rx_alloc()
2636 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), in mtk_rx_alloc()
2638 if (!ring->data) in mtk_rx_alloc()
2639 return -ENOMEM; in mtk_rx_alloc()
2644 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, in mtk_rx_alloc()
2649 ring->page_pool = pp; in mtk_rx_alloc()
2652 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || in mtk_rx_alloc()
2654 ring->dma = dma_alloc_coherent(eth->dma_dev, in mtk_rx_alloc()
2655 rx_dma_size * eth->soc->rx.desc_size, in mtk_rx_alloc()
2656 &ring->phys, GFP_KERNEL); in mtk_rx_alloc()
2658 struct mtk_tx_ring *tx_ring = ð->tx_ring; in mtk_rx_alloc()
2660 ring->dma = tx_ring->dma + tx_ring_size * in mtk_rx_alloc()
2661 eth->soc->tx.desc_size * (ring_no + 1); in mtk_rx_alloc()
2662 ring->phys = tx_ring->phys + tx_ring_size * in mtk_rx_alloc()
2663 eth->soc->tx.desc_size * (ring_no + 1); in mtk_rx_alloc()
2666 if (!ring->dma) in mtk_rx_alloc()
2667 return -ENOMEM; in mtk_rx_alloc()
2674 rxd = ring->dma + i * eth->soc->rx.desc_size; in mtk_rx_alloc()
2675 if (ring->page_pool) { in mtk_rx_alloc()
2676 data = mtk_page_pool_get_buff(ring->page_pool, in mtk_rx_alloc()
2679 return -ENOMEM; in mtk_rx_alloc()
2681 if (ring->frag_size <= PAGE_SIZE) in mtk_rx_alloc()
2682 data = netdev_alloc_frag(ring->frag_size); in mtk_rx_alloc()
2687 return -ENOMEM; in mtk_rx_alloc()
2689 dma_addr = dma_map_single(eth->dma_dev, in mtk_rx_alloc()
2690 data + NET_SKB_PAD + eth->ip_align, in mtk_rx_alloc()
2691 ring->buf_size, DMA_FROM_DEVICE); in mtk_rx_alloc()
2692 if (unlikely(dma_mapping_error(eth->dma_dev, in mtk_rx_alloc()
2695 return -ENOMEM; in mtk_rx_alloc()
2698 rxd->rxd1 = (unsigned int)dma_addr; in mtk_rx_alloc()
2699 ring->data[i] = data; in mtk_rx_alloc()
2701 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_rx_alloc()
2702 rxd->rxd2 = RX_DMA_LSO; in mtk_rx_alloc()
2704 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); in mtk_rx_alloc()
2706 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) in mtk_rx_alloc()
2707 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr); in mtk_rx_alloc()
2709 rxd->rxd3 = 0; in mtk_rx_alloc()
2710 rxd->rxd4 = 0; in mtk_rx_alloc()
2712 rxd->rxd5 = 0; in mtk_rx_alloc()
2713 rxd->rxd6 = 0; in mtk_rx_alloc()
2714 rxd->rxd7 = 0; in mtk_rx_alloc()
2715 rxd->rxd8 = 0; in mtk_rx_alloc()
2719 ring->dma_size = rx_dma_size; in mtk_rx_alloc()
2720 ring->calc_idx_update = false; in mtk_rx_alloc()
2721 ring->calc_idx = rx_dma_size - 1; in mtk_rx_alloc()
2723 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + in mtk_rx_alloc()
2726 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + in mtk_rx_alloc()
2734 mtk_w32(eth, ring->phys, in mtk_rx_alloc()
2735 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2737 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2739 reg_map->qdma.rst_idx); in mtk_rx_alloc()
2741 mtk_w32(eth, ring->phys, in mtk_rx_alloc()
2742 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2744 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); in mtk_rx_alloc()
2746 reg_map->pdma.rst_idx); in mtk_rx_alloc()
2748 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); in mtk_rx_alloc()
2758 if (ring->data && ring->dma) { in mtk_rx_clean()
2759 for (i = 0; i < ring->dma_size; i++) { in mtk_rx_clean()
2762 if (!ring->data[i]) in mtk_rx_clean()
2765 rxd = ring->dma + i * eth->soc->rx.desc_size; in mtk_rx_clean()
2766 if (!rxd->rxd1) in mtk_rx_clean()
2769 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) in mtk_rx_clean()
2770 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2); in mtk_rx_clean()
2772 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64), in mtk_rx_clean()
2773 ring->buf_size, DMA_FROM_DEVICE); in mtk_rx_clean()
2774 mtk_rx_put_buff(ring, ring->data[i], false); in mtk_rx_clean()
2776 kfree(ring->data); in mtk_rx_clean()
2777 ring->data = NULL; in mtk_rx_clean()
2780 if (!in_sram && ring->dma) { in mtk_rx_clean()
2781 dma_free_coherent(eth->dma_dev, in mtk_rx_clean()
2782 ring->dma_size * eth->soc->rx.desc_size, in mtk_rx_clean()
2783 ring->dma, ring->phys); in mtk_rx_clean()
2784 ring->dma = NULL; in mtk_rx_clean()
2787 if (ring->page_pool) { in mtk_rx_clean()
2788 if (xdp_rxq_info_is_reg(&ring->xdp_q)) in mtk_rx_clean()
2789 xdp_rxq_info_unreg(&ring->xdp_q); in mtk_rx_clean()
2790 page_pool_destroy(ring->page_pool); in mtk_rx_clean()
2791 ring->page_pool = NULL; in mtk_rx_clean()
2801 /* set LRO rings to auto-learn modes */ in mtk_hwlro_rx_init()
2833 /* auto-learn score delta setting */ in mtk_hwlro_rx_init()
2914 if (mac->hwlro_ip[i]) in mtk_hwlro_get_ip_cnt()
2925 (struct ethtool_rx_flow_spec *)&cmd->fs; in mtk_hwlro_add_ipaddr()
2927 struct mtk_eth *eth = mac->hw; in mtk_hwlro_add_ipaddr()
2930 if ((fsp->flow_type != TCP_V4_FLOW) || in mtk_hwlro_add_ipaddr()
2931 (!fsp->h_u.tcp_ip4_spec.ip4dst) || in mtk_hwlro_add_ipaddr()
2932 (fsp->location > 1)) in mtk_hwlro_add_ipaddr()
2933 return -EINVAL; in mtk_hwlro_add_ipaddr()
2935 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); in mtk_hwlro_add_ipaddr()
2936 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; in mtk_hwlro_add_ipaddr()
2938 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); in mtk_hwlro_add_ipaddr()
2940 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); in mtk_hwlro_add_ipaddr()
2949 (struct ethtool_rx_flow_spec *)&cmd->fs; in mtk_hwlro_del_ipaddr()
2951 struct mtk_eth *eth = mac->hw; in mtk_hwlro_del_ipaddr()
2954 if (fsp->location > 1) in mtk_hwlro_del_ipaddr()
2955 return -EINVAL; in mtk_hwlro_del_ipaddr()
2957 mac->hwlro_ip[fsp->location] = 0; in mtk_hwlro_del_ipaddr()
2958 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; in mtk_hwlro_del_ipaddr()
2960 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); in mtk_hwlro_del_ipaddr()
2970 struct mtk_eth *eth = mac->hw; in mtk_hwlro_netdev_disable()
2974 mac->hwlro_ip[i] = 0; in mtk_hwlro_netdev_disable()
2975 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; in mtk_hwlro_netdev_disable()
2980 mac->hwlro_ip_cnt = 0; in mtk_hwlro_netdev_disable()
2988 (struct ethtool_rx_flow_spec *)&cmd->fs; in mtk_hwlro_get_fdir_entry()
2990 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) in mtk_hwlro_get_fdir_entry()
2991 return -EINVAL; in mtk_hwlro_get_fdir_entry()
2994 fsp->flow_type = TCP_V4_FLOW; in mtk_hwlro_get_fdir_entry()
2995 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); in mtk_hwlro_get_fdir_entry()
2996 fsp->m_u.tcp_ip4_spec.ip4dst = 0; in mtk_hwlro_get_fdir_entry()
2998 fsp->h_u.tcp_ip4_spec.ip4src = 0; in mtk_hwlro_get_fdir_entry()
2999 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; in mtk_hwlro_get_fdir_entry()
3000 fsp->h_u.tcp_ip4_spec.psrc = 0; in mtk_hwlro_get_fdir_entry()
3001 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; in mtk_hwlro_get_fdir_entry()
3002 fsp->h_u.tcp_ip4_spec.pdst = 0; in mtk_hwlro_get_fdir_entry()
3003 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; in mtk_hwlro_get_fdir_entry()
3004 fsp->h_u.tcp_ip4_spec.tos = 0; in mtk_hwlro_get_fdir_entry()
3005 fsp->m_u.tcp_ip4_spec.tos = 0xff; in mtk_hwlro_get_fdir_entry()
3019 if (cnt == cmd->rule_cnt) in mtk_hwlro_get_fdir_all()
3020 return -EMSGSIZE; in mtk_hwlro_get_fdir_all()
3022 if (mac->hwlro_ip[i]) { in mtk_hwlro_get_fdir_all()
3028 cmd->rule_cnt = cnt; in mtk_hwlro_get_fdir_all()
3052 netdev_features_t diff = dev->features ^ features; in mtk_set_features()
3067 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_dma_busy_wait()
3068 reg = eth->soc->reg_map->qdma.glo_cfg; in mtk_dma_busy_wait()
3070 reg = eth->soc->reg_map->pdma.glo_cfg; in mtk_dma_busy_wait()
3072 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, in mtk_dma_busy_wait()
3076 dev_err(eth->dev, "DMA init timeout\n"); in mtk_dma_busy_wait()
3087 return -EBUSY; in mtk_dma_init()
3089 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_dma_init()
3102 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_dma_init()
3112 if (eth->hwlro) { in mtk_dma_init()
3123 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_dma_init()
3128 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); in mtk_dma_init()
3129 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); in mtk_dma_init()
3137 const struct mtk_soc_data *soc = eth->soc; in mtk_dma_free()
3141 if (eth->netdev[i]) in mtk_dma_free()
3142 netdev_reset_queue(eth->netdev[i]); in mtk_dma_free()
3143 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { in mtk_dma_free()
3144 dma_free_coherent(eth->dma_dev, in mtk_dma_free()
3145 MTK_QDMA_RING_SIZE * soc->tx.desc_size, in mtk_dma_free()
3146 eth->scratch_ring, eth->phy_scratch_ring); in mtk_dma_free()
3147 eth->scratch_ring = NULL; in mtk_dma_free()
3148 eth->phy_scratch_ring = 0; in mtk_dma_free()
3151 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); in mtk_dma_free()
3152 mtk_rx_clean(eth, ð->rx_ring_qdma, false); in mtk_dma_free()
3154 if (eth->hwlro) { in mtk_dma_free()
3157 mtk_rx_clean(eth, ð->rx_ring[i], false); in mtk_dma_free()
3160 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) { in mtk_dma_free()
3161 kfree(eth->scratch_head[i]); in mtk_dma_free()
3162 eth->scratch_head[i] = NULL; in mtk_dma_free()
3178 struct mtk_eth *eth = mac->hw; in mtk_tx_timeout()
3180 if (test_bit(MTK_RESETTING, ð->state)) in mtk_tx_timeout()
3186 eth->netdev[mac->id]->stats.tx_errors++; in mtk_tx_timeout()
3189 schedule_work(ð->pending_work); in mtk_tx_timeout()
3196 eth->rx_events++; in mtk_handle_irq_rx()
3197 if (likely(napi_schedule_prep(ð->rx_napi))) { in mtk_handle_irq_rx()
3198 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); in mtk_handle_irq_rx()
3199 __napi_schedule(ð->rx_napi); in mtk_handle_irq_rx()
3209 eth->tx_events++; in mtk_handle_irq_tx()
3210 if (likely(napi_schedule_prep(ð->tx_napi))) { in mtk_handle_irq_tx()
3212 __napi_schedule(ð->tx_napi); in mtk_handle_irq_tx()
3221 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_handle_irq()
3223 if (mtk_r32(eth, reg_map->pdma.irq_mask) & in mtk_handle_irq()
3224 eth->soc->rx.irq_done_mask) { in mtk_handle_irq()
3225 if (mtk_r32(eth, reg_map->pdma.irq_status) & in mtk_handle_irq()
3226 eth->soc->rx.irq_done_mask) in mtk_handle_irq()
3229 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { in mtk_handle_irq()
3230 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) in mtk_handle_irq()
3241 struct mtk_eth *eth = mac->hw; in mtk_poll_controller()
3244 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); in mtk_poll_controller()
3245 mtk_handle_irq_rx(eth->irq[2], dev); in mtk_poll_controller()
3247 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); in mtk_poll_controller()
3254 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_start_dma()
3263 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_start_dma()
3264 val = mtk_r32(eth, reg_map->qdma.glo_cfg); in mtk_start_dma()
3275 mtk_w32(eth, val, reg_map->qdma.glo_cfg); in mtk_start_dma()
3280 reg_map->pdma.glo_cfg); in mtk_start_dma()
3284 reg_map->pdma.glo_cfg); in mtk_start_dma()
3294 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_gdm_config()
3307 if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id])) in mtk_gdm_config()
3318 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; in mtk_uses_dsa()
3327 struct mtk_eth *eth = mac->hw; in mtk_device_event()
3351 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) in mtk_device_event()
3355 if (dp->index >= MTK_QDMA_NUM_QUEUES) in mtk_device_event()
3358 if (mac->speed > 0 && mac->speed <= s.base.speed) in mtk_device_event()
3361 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); in mtk_device_event()
3369 struct mtk_eth *eth = mac->hw; in mtk_open()
3373 ppe_num = eth->soc->ppe_num; in mtk_open()
3375 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); in mtk_open()
3383 if (!refcount_read(ð->dma_refcnt)) { in mtk_open()
3384 const struct mtk_soc_data *soc = eth->soc; in mtk_open()
3390 phylink_disconnect_phy(mac->phylink); in mtk_open()
3394 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_open()
3395 mtk_ppe_start(eth->ppe[i]); in mtk_open()
3398 if (!eth->netdev[i]) in mtk_open()
3401 target_mac = netdev_priv(eth->netdev[i]); in mtk_open()
3402 if (!soc->offload_version) { in mtk_open()
3403 target_mac->ppe_idx = 0; in mtk_open()
3405 } else if (ppe_num >= 3 && target_mac->id == 2) { in mtk_open()
3406 target_mac->ppe_idx = 2; in mtk_open()
3407 gdm_config = soc->reg_map->gdma_to_ppe[2]; in mtk_open()
3408 } else if (ppe_num >= 2 && target_mac->id == 1) { in mtk_open()
3409 target_mac->ppe_idx = 1; in mtk_open()
3410 gdm_config = soc->reg_map->gdma_to_ppe[1]; in mtk_open()
3412 target_mac->ppe_idx = 0; in mtk_open()
3413 gdm_config = soc->reg_map->gdma_to_ppe[0]; in mtk_open()
3415 mtk_gdm_config(eth, target_mac->id, gdm_config); in mtk_open()
3421 napi_enable(ð->tx_napi); in mtk_open()
3422 napi_enable(ð->rx_napi); in mtk_open()
3424 mtk_rx_irq_enable(eth, soc->rx.irq_done_mask); in mtk_open()
3425 refcount_set(ð->dma_refcnt, 1); in mtk_open()
3427 refcount_inc(ð->dma_refcnt); in mtk_open()
3430 phylink_start(mac->phylink); in mtk_open()
3436 if (mtk_uses_dsa(dev) && !eth->prog) { in mtk_open()
3437 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_open()
3438 struct metadata_dst *md_dst = eth->dsa_meta[i]; in mtk_open()
3446 return -ENOMEM; in mtk_open()
3448 md_dst->u.port_info.port_id = i; in mtk_open()
3449 eth->dsa_meta[i] = md_dst; in mtk_open()
3472 spin_lock_bh(ð->page_lock); in mtk_stop_dma()
3476 spin_unlock_bh(ð->page_lock); in mtk_stop_dma()
3492 struct mtk_eth *eth = mac->hw; in mtk_stop()
3495 phylink_stop(mac->phylink); in mtk_stop()
3499 phylink_disconnect_phy(mac->phylink); in mtk_stop()
3502 if (!refcount_dec_and_test(ð->dma_refcnt)) in mtk_stop()
3509 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); in mtk_stop()
3510 napi_disable(ð->tx_napi); in mtk_stop()
3511 napi_disable(ð->rx_napi); in mtk_stop()
3513 cancel_work_sync(ð->rx_dim.work); in mtk_stop()
3514 cancel_work_sync(ð->tx_dim.work); in mtk_stop()
3516 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_stop()
3517 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); in mtk_stop()
3518 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); in mtk_stop()
3522 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_stop()
3523 mtk_ppe_stop(eth->ppe[i]); in mtk_stop()
3532 struct mtk_eth *eth = mac->hw; in mtk_xdp_setup()
3536 if (eth->hwlro) { in mtk_xdp_setup()
3538 return -EOPNOTSUPP; in mtk_xdp_setup()
3541 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { in mtk_xdp_setup()
3543 return -EOPNOTSUPP; in mtk_xdp_setup()
3546 need_update = !!eth->prog != !!prog; in mtk_xdp_setup()
3550 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); in mtk_xdp_setup()
3562 switch (xdp->command) { in mtk_xdp()
3564 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); in mtk_xdp()
3566 return -EINVAL; in mtk_xdp()
3572 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3577 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3587 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) in mtk_clk_disable()
3588 clk_disable_unprepare(eth->clks[clk]); in mtk_clk_disable()
3596 ret = clk_prepare_enable(eth->clks[clk]); in mtk_clk_enable()
3604 while (--clk >= 0) in mtk_clk_enable()
3605 clk_disable_unprepare(eth->clks[clk]); in mtk_clk_enable()
3614 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_dim_rx()
3618 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, in mtk_dim_rx()
3619 dim->profile_ix); in mtk_dim_rx()
3620 spin_lock_bh(ð->dim_lock); in mtk_dim_rx()
3622 val = mtk_r32(eth, reg_map->pdma.delay_irq); in mtk_dim_rx()
3632 mtk_w32(eth, val, reg_map->pdma.delay_irq); in mtk_dim_rx()
3633 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_dim_rx()
3634 mtk_w32(eth, val, reg_map->qdma.delay_irq); in mtk_dim_rx()
3636 spin_unlock_bh(ð->dim_lock); in mtk_dim_rx()
3638 dim->state = DIM_START_MEASURE; in mtk_dim_rx()
3645 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_dim_tx()
3649 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, in mtk_dim_tx()
3650 dim->profile_ix); in mtk_dim_tx()
3651 spin_lock_bh(ð->dim_lock); in mtk_dim_tx()
3653 val = mtk_r32(eth, reg_map->pdma.delay_irq); in mtk_dim_tx()
3663 mtk_w32(eth, val, reg_map->pdma.delay_irq); in mtk_dim_tx()
3664 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_dim_tx()
3665 mtk_w32(eth, val, reg_map->qdma.delay_irq); in mtk_dim_tx()
3667 spin_unlock_bh(ð->dim_lock); in mtk_dim_tx()
3669 dim->state = DIM_START_MEASURE; in mtk_dim_tx()
3674 struct mtk_eth *eth = mac->hw; in mtk_set_mcr_max_rx()
3677 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_set_mcr_max_rx()
3680 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); in mtk_set_mcr_max_rx()
3693 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); in mtk_set_mcr_max_rx()
3701 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3706 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_hw_reset()
3709 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) in mtk_hw_reset()
3716 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_hw_reset()
3725 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
3728 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
3736 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); in mtk_hw_reset_read()
3744 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, in mtk_hw_warm_reset()
3748 dev_err(eth->dev, "warm reset failed\n"); in mtk_hw_warm_reset()
3755 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_hw_warm_reset()
3757 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) in mtk_hw_warm_reset()
3763 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_hw_warm_reset()
3769 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); in mtk_hw_warm_reset()
3774 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", in mtk_hw_warm_reset()
3778 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); in mtk_hw_warm_reset()
3783 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", in mtk_hw_warm_reset()
3789 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_hw_check_dma_hang()
3797 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_hw_check_dma_hang()
3801 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); in mtk_hw_check_dma_hang()
3803 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); in mtk_hw_check_dma_hang()
3806 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); in mtk_hw_check_dma_hang()
3809 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && in mtk_hw_check_dma_hang()
3810 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && in mtk_hw_check_dma_hang()
3811 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); in mtk_hw_check_dma_hang()
3813 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { in mtk_hw_check_dma_hang()
3814 if (++eth->reset.wdma_hang_count > 2) { in mtk_hw_check_dma_hang()
3815 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
3822 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); in mtk_hw_check_dma_hang()
3823 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); in mtk_hw_check_dma_hang()
3829 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); in mtk_hw_check_dma_hang()
3830 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); in mtk_hw_check_dma_hang()
3835 if (++eth->reset.qdma_hang_count > 2) { in mtk_hw_check_dma_hang()
3836 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
3843 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); in mtk_hw_check_dma_hang()
3845 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && in mtk_hw_check_dma_hang()
3846 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); in mtk_hw_check_dma_hang()
3849 if (++eth->reset.adma_hang_count > 2) { in mtk_hw_check_dma_hang()
3850 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
3856 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
3857 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
3858 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
3860 eth->reset.wdidx = wdidx; in mtk_hw_check_dma_hang()
3871 if (test_bit(MTK_RESETTING, ð->state)) in mtk_hw_reset_monitor_work()
3876 schedule_work(ð->pending_work); in mtk_hw_reset_monitor_work()
3879 schedule_delayed_work(ð->reset.monitor_work, in mtk_hw_reset_monitor_work()
3887 const struct mtk_reg_map *reg_map = eth->soc->reg_map; in mtk_hw_init()
3890 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) in mtk_hw_init()
3894 pm_runtime_enable(eth->dev); in mtk_hw_init()
3895 pm_runtime_get_sync(eth->dev); in mtk_hw_init()
3902 if (eth->ethsys) in mtk_hw_init()
3903 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, in mtk_hw_init()
3904 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); in mtk_hw_init()
3906 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_hw_init()
3907 ret = device_reset(eth->dev); in mtk_hw_init()
3909 dev_err(eth->dev, "MAC reset failed!\n"); in mtk_hw_init()
3914 mtk_dim_rx(ð->rx_dim.work); in mtk_hw_init()
3915 mtk_dim_tx(ð->tx_dim.work); in mtk_hw_init()
3937 if (eth->pctl) { in mtk_hw_init()
3939 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); in mtk_hw_init()
3942 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); in mtk_hw_init()
3945 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); in mtk_hw_init()
3953 struct net_device *dev = eth->netdev[i]; in mtk_hw_init()
3960 dev->mtu + MTK_RX_ETH_HLEN); in mtk_hw_init()
3976 mtk_dim_rx(ð->rx_dim.work); in mtk_hw_init()
3977 mtk_dim_tx(ð->tx_dim.work); in mtk_hw_init()
3984 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); in mtk_hw_init()
3985 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4); in mtk_hw_init()
3986 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); in mtk_hw_init()
3987 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4); in mtk_hw_init()
4006 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); in mtk_hw_init()
4050 pm_runtime_put_sync(eth->dev); in mtk_hw_init()
4051 pm_runtime_disable(eth->dev); in mtk_hw_init()
4059 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) in mtk_hw_deinit()
4064 pm_runtime_put_sync(eth->dev); in mtk_hw_deinit()
4065 pm_runtime_disable(eth->dev); in mtk_hw_deinit()
4073 struct mtk_eth *eth = mac->hw; in mtk_uninit()
4075 phylink_disconnect_phy(mac->phylink); in mtk_uninit()
4084 struct mtk_eth *eth = mac->hw; in mtk_change_mtu()
4086 if (rcu_access_pointer(eth->prog) && in mtk_change_mtu()
4089 return -EINVAL; in mtk_change_mtu()
4093 WRITE_ONCE(dev->mtu, new_mtu); in mtk_change_mtu()
4106 return phylink_mii_ioctl(mac->phylink, ifr, cmd); in mtk_do_ioctl()
4111 return -EOPNOTSUPP; in mtk_do_ioctl()
4124 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_prepare_for_reset()
4126 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) in mtk_prepare_for_reset()
4132 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_prepare_for_reset()
4133 mtk_ppe_prepare_reset(eth->ppe[i]); in mtk_prepare_for_reset()
4153 set_bit(MTK_RESETTING, ð->state); in mtk_pending_work()
4164 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) in mtk_pending_work()
4167 mtk_stop(eth->netdev[i]); in mtk_pending_work()
4173 if (eth->dev->pins) in mtk_pending_work()
4174 pinctrl_select_state(eth->dev->pins->p, in mtk_pending_work()
4175 eth->dev->pins->default_state); in mtk_pending_work()
4180 if (!eth->netdev[i] || !test_bit(i, &restart)) in mtk_pending_work()
4183 if (mtk_open(eth->netdev[i])) { in mtk_pending_work()
4184 netif_alert(eth, ifup, eth->netdev[i], in mtk_pending_work()
4186 dev_close(eth->netdev[i]); in mtk_pending_work()
4195 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) in mtk_pending_work()
4197 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2)) in mtk_pending_work()
4203 clear_bit(MTK_RESETTING, ð->state); in mtk_pending_work()
4215 if (!eth->netdev[i]) in mtk_free_dev()
4217 free_netdev(eth->netdev[i]); in mtk_free_dev()
4220 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_free_dev()
4221 if (!eth->dsa_meta[i]) in mtk_free_dev()
4223 metadata_dst_free(eth->dsa_meta[i]); in mtk_free_dev()
4235 if (!eth->netdev[i]) in mtk_unreg_dev()
4237 mac = netdev_priv(eth->netdev[i]); in mtk_unreg_dev()
4238 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_unreg_dev()
4239 unregister_netdevice_notifier(&mac->device_notifier); in mtk_unreg_dev()
4240 unregister_netdev(eth->netdev[i]); in mtk_unreg_dev()
4251 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); in mtk_sgmii_destroy()
4259 cancel_work_sync(ð->pending_work); in mtk_cleanup()
4260 cancel_delayed_work_sync(ð->reset.monitor_work); in mtk_cleanup()
4270 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_get_link_ksettings()
4271 return -EBUSY; in mtk_get_link_ksettings()
4273 return phylink_ethtool_ksettings_get(mac->phylink, cmd); in mtk_get_link_ksettings()
4281 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_set_link_ksettings()
4282 return -EBUSY; in mtk_set_link_ksettings()
4284 return phylink_ethtool_ksettings_set(mac->phylink, cmd); in mtk_set_link_ksettings()
4292 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); in mtk_get_drvinfo()
4293 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); in mtk_get_drvinfo()
4294 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); in mtk_get_drvinfo()
4301 return mac->hw->msg_enable; in mtk_get_msglevel()
4308 mac->hw->msg_enable = value; in mtk_set_msglevel()
4315 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_nway_reset()
4316 return -EBUSY; in mtk_nway_reset()
4318 if (!mac->phylink) in mtk_nway_reset()
4319 return -ENOTSUPP; in mtk_nway_reset()
4321 return phylink_ethtool_nway_reset(mac->phylink); in mtk_nway_reset()
4334 if (mtk_page_pool_enabled(mac->hw)) in mtk_get_strings()
4350 if (mtk_page_pool_enabled(mac->hw)) in mtk_get_sset_count()
4355 return -EOPNOTSUPP; in mtk_get_sset_count()
4364 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { in mtk_ethtool_pp_stats()
4365 struct mtk_rx_ring *ring = ð->rx_ring[i]; in mtk_ethtool_pp_stats()
4367 if (!ring->page_pool) in mtk_ethtool_pp_stats()
4370 page_pool_get_stats(ring->page_pool, &stats); in mtk_ethtool_pp_stats()
4379 struct mtk_hw_stats *hwstats = mac->hw_stats; in mtk_get_ethtool_stats()
4384 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) in mtk_get_ethtool_stats()
4388 if (spin_trylock_bh(&hwstats->stats_lock)) { in mtk_get_ethtool_stats()
4390 spin_unlock_bh(&hwstats->stats_lock); in mtk_get_ethtool_stats()
4398 start = u64_stats_fetch_begin(&hwstats->syncp); in mtk_get_ethtool_stats()
4402 if (mtk_page_pool_enabled(mac->hw)) in mtk_get_ethtool_stats()
4403 mtk_ethtool_pp_stats(mac->hw, data_dst); in mtk_get_ethtool_stats()
4404 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); in mtk_get_ethtool_stats()
4410 int ret = -EOPNOTSUPP; in mtk_get_rxnfc()
4412 switch (cmd->cmd) { in mtk_get_rxnfc()
4414 if (dev->hw_features & NETIF_F_LRO) { in mtk_get_rxnfc()
4415 cmd->data = MTK_MAX_RX_RING_NUM; in mtk_get_rxnfc()
4420 if (dev->hw_features & NETIF_F_LRO) { in mtk_get_rxnfc()
4423 cmd->rule_cnt = mac->hwlro_ip_cnt; in mtk_get_rxnfc()
4428 if (dev->hw_features & NETIF_F_LRO) in mtk_get_rxnfc()
4432 if (dev->hw_features & NETIF_F_LRO) in mtk_get_rxnfc()
4445 int ret = -EOPNOTSUPP; in mtk_set_rxnfc()
4447 switch (cmd->cmd) { in mtk_set_rxnfc()
4449 if (dev->hw_features & NETIF_F_LRO) in mtk_set_rxnfc()
4453 if (dev->hw_features & NETIF_F_LRO) in mtk_set_rxnfc()
4467 phylink_ethtool_get_pauseparam(mac->phylink, pause); in mtk_get_pauseparam()
4474 return phylink_ethtool_set_pauseparam(mac->phylink, pause); in mtk_set_pauseparam()
4486 queue = mac->id; in mtk_select_queue()
4488 if (queue >= dev->num_tx_queues) in mtk_select_queue()
4544 dev_err(eth->dev, "missing mac id\n"); in mtk_add_mac()
4545 return -EINVAL; in mtk_add_mac()
4550 dev_err(eth->dev, "%d is not a valid mac id\n", id); in mtk_add_mac()
4551 return -EINVAL; in mtk_add_mac()
4554 if (eth->netdev[id]) { in mtk_add_mac()
4555 dev_err(eth->dev, "duplicate mac id found: %d\n", id); in mtk_add_mac()
4556 return -EINVAL; in mtk_add_mac()
4559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) in mtk_add_mac()
4562 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); in mtk_add_mac()
4563 if (!eth->netdev[id]) { in mtk_add_mac()
4564 dev_err(eth->dev, "alloc_etherdev failed\n"); in mtk_add_mac()
4565 return -ENOMEM; in mtk_add_mac()
4567 mac = netdev_priv(eth->netdev[id]); in mtk_add_mac()
4568 eth->mac[id] = mac; in mtk_add_mac()
4569 mac->id = id; in mtk_add_mac()
4570 mac->hw = eth; in mtk_add_mac()
4571 mac->of_node = np; in mtk_add_mac()
4573 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]); in mtk_add_mac()
4574 if (err == -EPROBE_DEFER) in mtk_add_mac()
4579 eth_hw_addr_random(eth->netdev[id]); in mtk_add_mac()
4580 dev_err(eth->dev, "generated random MAC address %pM\n", in mtk_add_mac()
4581 eth->netdev[id]->dev_addr); in mtk_add_mac()
4584 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); in mtk_add_mac()
4585 mac->hwlro_ip_cnt = 0; in mtk_add_mac()
4587 mac->hw_stats = devm_kzalloc(eth->dev, in mtk_add_mac()
4588 sizeof(*mac->hw_stats), in mtk_add_mac()
4590 if (!mac->hw_stats) { in mtk_add_mac()
4591 dev_err(eth->dev, "failed to allocate counter memory\n"); in mtk_add_mac()
4592 err = -ENOMEM; in mtk_add_mac()
4595 spin_lock_init(&mac->hw_stats->stats_lock); in mtk_add_mac()
4596 u64_stats_init(&mac->hw_stats->syncp); in mtk_add_mac()
4599 mac->hw_stats->reg_offset = id * 0x80; in mtk_add_mac()
4601 mac->hw_stats->reg_offset = id * 0x40; in mtk_add_mac()
4606 dev_err(eth->dev, "incorrect phy-mode\n"); in mtk_add_mac()
4611 mac->interface = PHY_INTERFACE_MODE_NA; in mtk_add_mac()
4612 mac->speed = SPEED_UNKNOWN; in mtk_add_mac()
4614 mac->phylink_config.dev = ð->netdev[id]->dev; in mtk_add_mac()
4615 mac->phylink_config.type = PHYLINK_NETDEV; in mtk_add_mac()
4616 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in mtk_add_mac()
4619 /* MT7623 gmac0 is now missing its speed-specific PLL configuration in mtk_add_mac()
4620 * in its .mac_config method (since state->speed is not valid there. in mtk_add_mac()
4623 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { in mtk_add_mac()
4625 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4627 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4629 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) in mtk_add_mac()
4630 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); in mtk_add_mac()
4633 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) in mtk_add_mac()
4635 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4638 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && in mtk_add_mac()
4639 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { in mtk_add_mac()
4640 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); in mtk_add_mac()
4643 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4646 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { in mtk_add_mac()
4648 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4650 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4652 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4655 if (mtk_is_netsys_v3_or_greater(mac->hw) && in mtk_add_mac()
4656 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && in mtk_add_mac()
4658 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | in mtk_add_mac()
4661 phy_interface_zero(mac->phylink_config.supported_interfaces); in mtk_add_mac()
4663 mac->phylink_config.supported_interfaces); in mtk_add_mac()
4666 phylink = phylink_create(&mac->phylink_config, in mtk_add_mac()
4667 of_fwnode_handle(mac->of_node), in mtk_add_mac()
4674 mac->phylink = phylink; in mtk_add_mac()
4676 SET_NETDEV_DEV(eth->netdev[id], eth->dev); in mtk_add_mac()
4677 eth->netdev[id]->watchdog_timeo = 5 * HZ; in mtk_add_mac()
4678 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; in mtk_add_mac()
4679 eth->netdev[id]->base_addr = (unsigned long)eth->base; in mtk_add_mac()
4681 eth->netdev[id]->hw_features = eth->soc->hw_features; in mtk_add_mac()
4682 if (eth->hwlro) in mtk_add_mac()
4683 eth->netdev[id]->hw_features |= NETIF_F_LRO; in mtk_add_mac()
4685 eth->netdev[id]->vlan_features = eth->soc->hw_features & in mtk_add_mac()
4687 eth->netdev[id]->features |= eth->soc->hw_features; in mtk_add_mac()
4688 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; in mtk_add_mac()
4690 eth->netdev[id]->irq = eth->irq[0]; in mtk_add_mac()
4691 eth->netdev[id]->dev.of_node = np; in mtk_add_mac()
4693 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_add_mac()
4694 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; in mtk_add_mac()
4696 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; in mtk_add_mac()
4698 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { in mtk_add_mac()
4699 mac->device_notifier.notifier_call = mtk_device_event; in mtk_add_mac()
4700 register_netdevice_notifier(&mac->device_notifier); in mtk_add_mac()
4704 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | in mtk_add_mac()
4712 free_netdev(eth->netdev[id]); in mtk_add_mac()
4725 dev = eth->netdev[i]; in mtk_eth_set_dma_device()
4727 if (!dev || !(dev->flags & IFF_UP)) in mtk_eth_set_dma_device()
4730 list_add_tail(&dev->close_list, &dev_list); in mtk_eth_set_dma_device()
4735 eth->dma_dev = dma_dev; in mtk_eth_set_dma_device()
4738 list_del_init(&dev->close_list); in mtk_eth_set_dma_device()
4753 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); in mtk_sgmii_init()
4767 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, in mtk_sgmii_init()
4768 eth->soc->ana_rgc3, in mtk_sgmii_init()
4782 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); in mtk_probe()
4784 return -ENOMEM; in mtk_probe()
4786 eth->soc = of_device_get_match_data(&pdev->dev); in mtk_probe()
4788 eth->dev = &pdev->dev; in mtk_probe()
4789 eth->dma_dev = &pdev->dev; in mtk_probe()
4790 eth->base = devm_platform_ioremap_resource(pdev, 0); in mtk_probe()
4791 if (IS_ERR(eth->base)) in mtk_probe()
4792 return PTR_ERR(eth->base); in mtk_probe()
4794 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) in mtk_probe()
4795 eth->ip_align = NET_IP_ALIGN; in mtk_probe()
4797 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { in mtk_probe()
4803 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1); in mtk_probe()
4804 if (IS_ERR(eth->sram_base)) in mtk_probe()
4805 return PTR_ERR(eth->sram_base); in mtk_probe()
4807 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET; in mtk_probe()
4811 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) { in mtk_probe()
4812 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); in mtk_probe()
4814 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); in mtk_probe()
4817 dev_err(&pdev->dev, "Wrong DMA config\n"); in mtk_probe()
4818 return -EINVAL; in mtk_probe()
4822 spin_lock_init(ð->page_lock); in mtk_probe()
4823 spin_lock_init(ð->tx_irq_lock); in mtk_probe()
4824 spin_lock_init(ð->rx_irq_lock); in mtk_probe()
4825 spin_lock_init(ð->dim_lock); in mtk_probe()
4827 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; in mtk_probe()
4828 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); in mtk_probe()
4829 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); in mtk_probe()
4831 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; in mtk_probe()
4832 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); in mtk_probe()
4834 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_probe()
4835 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mtk_probe()
4837 if (IS_ERR(eth->ethsys)) { in mtk_probe()
4838 dev_err(&pdev->dev, "no ethsys regmap found\n"); in mtk_probe()
4839 return PTR_ERR(eth->ethsys); in mtk_probe()
4843 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { in mtk_probe()
4844 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mtk_probe()
4846 if (IS_ERR(eth->infra)) { in mtk_probe()
4847 dev_err(&pdev->dev, "no infracfg regmap found\n"); in mtk_probe()
4848 return PTR_ERR(eth->infra); in mtk_probe()
4852 if (of_dma_is_coherent(pdev->dev.of_node)) { in mtk_probe()
4855 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mtk_probe()
4856 "cci-control-port"); in mtk_probe()
4862 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { in mtk_probe()
4869 if (eth->soc->required_pctl) { in mtk_probe()
4870 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mtk_probe()
4872 if (IS_ERR(eth->pctl)) { in mtk_probe()
4873 dev_err(&pdev->dev, "no pctl regmap found\n"); in mtk_probe()
4874 err = PTR_ERR(eth->pctl); in mtk_probe()
4882 err = -EINVAL; in mtk_probe()
4885 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) { in mtk_probe()
4889 err = -EINVAL; in mtk_probe()
4892 eth->phy_scratch_ring = res_sram->start; in mtk_probe()
4894 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; in mtk_probe()
4899 if (eth->soc->offload_version) { in mtk_probe()
4905 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) in mtk_probe()
4908 np = of_parse_phandle(pdev->dev.of_node, in mtk_probe()
4913 wdma_base = eth->soc->reg_map->wdma_base[i]; in mtk_probe()
4914 wdma_phy = res ? res->start + wdma_base : 0; in mtk_probe()
4915 mtk_wed_add_hw(np, eth, eth->base + wdma_base, in mtk_probe()
4921 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) in mtk_probe()
4922 eth->irq[i] = eth->irq[0]; in mtk_probe()
4924 eth->irq[i] = platform_get_irq(pdev, i); in mtk_probe()
4925 if (eth->irq[i] < 0) { in mtk_probe()
4926 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); in mtk_probe()
4927 err = -ENXIO; in mtk_probe()
4931 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { in mtk_probe()
4932 eth->clks[i] = devm_clk_get(eth->dev, in mtk_probe()
4934 if (IS_ERR(eth->clks[i])) { in mtk_probe()
4935 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { in mtk_probe()
4936 err = -EPROBE_DEFER; in mtk_probe()
4939 if (eth->soc->required_clks & BIT(i)) { in mtk_probe()
4940 dev_err(&pdev->dev, "clock %s not found\n", in mtk_probe()
4942 err = -EINVAL; in mtk_probe()
4945 eth->clks[i] = NULL; in mtk_probe()
4949 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); in mtk_probe()
4950 INIT_WORK(ð->pending_work, mtk_pending_work); in mtk_probe()
4956 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); in mtk_probe()
4958 for_each_child_of_node(pdev->dev.of_node, mac_np) { in mtk_probe()
4960 "mediatek,eth-mac")) in mtk_probe()
4973 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { in mtk_probe()
4974 err = devm_request_irq(eth->dev, eth->irq[0], in mtk_probe()
4976 dev_name(eth->dev), eth); in mtk_probe()
4978 err = devm_request_irq(eth->dev, eth->irq[1], in mtk_probe()
4980 dev_name(eth->dev), eth); in mtk_probe()
4984 err = devm_request_irq(eth->dev, eth->irq[2], in mtk_probe()
4986 dev_name(eth->dev), eth); in mtk_probe()
4992 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { in mtk_probe()
4998 if (eth->soc->offload_version) { in mtk_probe()
4999 u8 ppe_num = eth->soc->ppe_num; in mtk_probe()
5001 ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num); in mtk_probe()
5003 u32 ppe_addr = eth->soc->reg_map->ppe_base; in mtk_probe()
5006 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); in mtk_probe()
5008 if (!eth->ppe[i]) { in mtk_probe()
5009 err = -ENOMEM; in mtk_probe()
5020 if (!eth->netdev[i]) in mtk_probe()
5023 err = register_netdev(eth->netdev[i]); in mtk_probe()
5025 dev_err(eth->dev, "error bringing up device\n"); in mtk_probe()
5028 netif_info(eth, probe, eth->netdev[i], in mtk_probe()
5030 eth->netdev[i]->base_addr, eth->irq[0]); in mtk_probe()
5036 eth->dummy_dev = alloc_netdev_dummy(0); in mtk_probe()
5037 if (!eth->dummy_dev) { in mtk_probe()
5038 err = -ENOMEM; in mtk_probe()
5039 dev_err(eth->dev, "failed to allocated dummy device\n"); in mtk_probe()
5042 netif_napi_add(eth->dummy_dev, ð->tx_napi, mtk_napi_tx); in mtk_probe()
5043 netif_napi_add(eth->dummy_dev, ð->rx_napi, mtk_napi_rx); in mtk_probe()
5046 schedule_delayed_work(ð->reset.monitor_work, in mtk_probe()
5076 if (!eth->netdev[i]) in mtk_remove()
5078 mtk_stop(eth->netdev[i]); in mtk_remove()
5079 mac = netdev_priv(eth->netdev[i]); in mtk_remove()
5080 phylink_disconnect_phy(mac->phylink); in mtk_remove()
5086 netif_napi_del(ð->tx_napi); in mtk_remove()
5087 netif_napi_del(ð->rx_napi); in mtk_remove()
5089 free_netdev(eth->dummy_dev); in mtk_remove()
5344 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
5345 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
5346 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
5347 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
5348 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
5349 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
5350 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
5351 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
5352 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },