Lines Matching +full:disable +full:- +full:report +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
62 P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
63 P_CLK_COR_REGS_D0_DIS = 1<<17,/* Disable Clock Core Regs D0 */
64 P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
65 P_CLK_PCI_REGS_D0_DIS = 1<<16,/* Disable Clock PCI Regs D0 */
66 P_CLK_COR_YTB_ARB_DIS = 1<<15,/* Disable Clock YTB Arbiter */
67 P_CLK_MAC_LNK1_D3_DIS = 1<<14,/* Disable Clock MAC Link1 D3 */
68 P_CLK_COR_LNK1_D0_DIS = 1<<13,/* Disable Clock Core Link1 D0 */
69 P_CLK_MAC_LNK1_D0_DIS = 1<<12,/* Disable Clock MAC Link1 D0 */
70 P_CLK_COR_LNK1_D3_DIS = 1<<11,/* Disable Clock Core Link1 D3 */
71 P_CLK_PCI_MST_ARB_DIS = 1<<10,/* Disable Clock PCI Master Arb. */
72 P_CLK_COR_REGS_D3_DIS = 1<<9, /* Disable Clock Core Regs D3 */
73 P_CLK_PCI_REGS_D3_DIS = 1<<8, /* Disable Clock PCI Regs D3 */
74 P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */
75 P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */
76 P_CLK_PCI_COMMON_DIS = 1<<5, /* Disable Clock PCI Common */
77 P_CLK_COR_COMMON_DIS = 1<<4, /* Disable Clock Core Common */
78 P_CLK_PCI_LNK1_BMU_DIS = 1<<3, /* Disable Clock PCI Link1 BMU */
79 P_CLK_COR_LNK1_BMU_DIS = 1<<2, /* Disable Clock Core Link1 BMU */
80 P_CLK_PCI_LNK1_BIU_DIS = 1<<1, /* Disable Clock PCI Link1 BIU */
81 P_CLK_COR_LNK1_BIU_DIS = 1<<0, /* Disable Clock Core Link1 BIU */
91 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
94 P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
98 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
114 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
118 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
119 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
120 P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
122 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
134 /* Bit 10.. 0: Mask for Gate Clock */
141 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
157 /* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
163 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
166 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
167 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
168 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
169 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
188 /* Yukon-Optima */
205 PSM_CONFIG_REG1_DIS_PSM_TIMER = 1<<19, /* Disable PSM Timer */
208 /* Yukon-Supreme */
214 PSM_CONFIG_REG1_UART_CLK_DISABLE= 1<<27, /* Disable UART clock */
229 PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK = 1<<12, /* Disable CLK_GATE control snd_task */
230 PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */
232 PSM_CONFIG_REG1_DIS_LOADER = 1<<9, /* Disable Loader SM after PSM Goes back to IDLE */
234 PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */
235 PSM_CONFIG_REG1_DIS_PERST = 1<<6, /* Disable Internal PCIe Reset after PSM Goes back to IDLE */
237 PSM_CONFIG_REG1_EN_PSM_LOAD = 1<<4, /* Disable EEPROM Loader after PSM Goes back to IDLE */
265 /* Special ISR registers (Yukon-2 only) */
308 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
310 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
363 Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */
368 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
369 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
370 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
371 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
372 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
373 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
374 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
375 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
376 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
377 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
392 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
394 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
401 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
423 Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */
424 Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */
425 Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */
443 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
463 /* Hardware error interrupt mask for Yukon 2 */
469 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
470 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
510 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
518 GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
520 GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
531 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
537 CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */
538 CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
539 CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */
540 CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */
541 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
542 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
543 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
544 CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
545 CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */
546 CHIP_ID_YUKON_PRM = 0xbd, /* YUKON-2 Optima Prime */
547 CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */
558 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
559 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
560 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
590 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
593 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
594 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
595 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
597 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
598 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
599 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
602 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
604 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
612 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
621 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
641 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
678 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
680 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
684 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
688 * Bank 4 - 5
739 /* Yukon-2 */
760 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
765 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
795 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
829 /* Receive GMAC FIFO (YUKON and Yukon-2) */
834 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
837 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
838 RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
839 RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
840 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
862 /* Rx BMU Control / Status Registers (Yukon-2) */
869 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
871 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
894 /* Tx BMU Control / Status Registers (Yukon-2) */
898 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
904 TBMU_TEST_BMU_TX_CHK_AUTO_OFF = 1<<31, /* BMU Tx Checksum Auto Calculation Disable */
907 TBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 1<<28, /* Home Address Paddiing FIX1 Disable */
909 TBMU_TEST_ROUTING_ADD_FIX_DIS = 1<<26, /* Routing Address Fix Disable */
911 TBMU_TEST_HOME_ADD_FIX_DIS = 1<<24, /* Home address checksum fix disable */
938 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
966 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
968 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
988 /* Threshold values for Yukon-EC Ultra and Extreme */
1010 /* Polling Unit Registers (Yukon-2 only) */
1037 /* ASF Subsystem Registers (Yukon-2 only) */
1051 /* Status BMU Registers (Yukon-2 only)*/
1058 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
1059 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
1060 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
1061 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
1065 /* FIFO Control/Status Registers (Yukon-2 only)*/
1074 /* Level and ISR Timer Registers (Yukon-2 only)*/
1103 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
1106 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
1135 * Marvel-PHY Registers, indirect addressed over GMAC
1142 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1144 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1147 /* Marvel-specific registers */
1148 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1149 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1153 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1179 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1182 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1198 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1200 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1222 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1223 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1224 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1225 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1226 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1238 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1239 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1240 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1241 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1249 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1250 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1262 /** Marvell-Specific */
1270 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1271 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1272 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1273 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1274 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1275 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1282 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1283 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1294 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1299 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1306 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1307 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1310 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1312 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1313 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1317 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1333 /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1335 PHY_M_PC_COP_TX_DIS = 1<<3, /* Copper Transmitter Disable */
1343 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1345 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1347 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1348 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1351 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1356 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1364 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1383 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1387 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1411 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1419 /* !!! Errata in spec. (1 = disable) */
1422 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1425 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */
1427 PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */
1438 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1440 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1444 /* !!! Errata in spec. (1 = disable) */
1456 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1457 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1459 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1462 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1467 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1480 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1481 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1482 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1483 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1484 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1485 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1550 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1562 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1563 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1564 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1592 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1594 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1597 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1602 PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */
1605 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1608 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1610 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1612 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1618 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1619 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1620 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1621 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1636 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1658 /* Interrupt Mask Registers */
1659 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1660 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1661 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1674 * MIB Counters base address definitions (low word) -
1691 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1692 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1693 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1694 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1695 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1696 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1708 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1709 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1710 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1711 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1712 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1713 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1728 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1738 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1745 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1754 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1756 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1757 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1758 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1765 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1766 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1767 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1778 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1787 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1808 GM_NEW_FLOW_CTRL = 1<<6, /* Enable New Flow-Control */
1810 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1847 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1848 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1871 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1873 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1881 GMF_RX_OVER_OFF = 1<<18, /* disable flushing on receive overrun */
1883 GMF_ASF_RX_OVER_OFF = 1<<16, /* disable flushing of ASF when overrun */
1907 /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */
1910 RX_IPV6_SA_MOB_DIS = 1<<8, /* IPv6 SA Mobility Support Disable */
1912 RX_IPV6_DA_MOB_DIS = 1<<6, /* IPv6 DA Mobility Support Disable */
1914 RX_PTR_SYNCDLY_DIS = 1<<4, /* Pointers Delay Synch Disable */
1916 RX_ASF_NEWFLAG_DIS = 1<<2, /* RX ASF Flag New Logic Disable */
1917 RX_FLSH_MISSPKT_ENA = 1<<1, /* RX Flush Miss-Packet Enable */
1918 RX_FLSH_MISSPKT_DIS = 1<<0, /* RX Flush Miss-Packet Disable */
1923 TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
1928 TX_STFW_DIS = 1<<31,/* Disable Store & Forward */
1932 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
2004 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2063 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2139 /* YUKON-2 STATUS opcodes defines */
2311 return !(hw->flags & SKY2_HW_FIBRE_PHY); in sky2_is_copper()
2317 return readl(hw->regs + reg); in sky2_read32()
2322 return readw(hw->regs + reg); in sky2_read16()
2327 return readb(hw->regs + reg); in sky2_read8()
2332 writel(val, hw->regs + reg); in sky2_write32()
2337 writew(val, hw->regs + reg); in sky2_write16()
2342 writeb(val, hw->regs + reg); in sky2_write8()
2347 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))