Lines Matching +full:11 +full:w
52 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
70 P_CLK_COR_LNK1_D3_DIS = 1<<11,/* Disable Clock Core Link1 D3 */
230 PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */
310 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
374 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
418 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
449 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
474 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
521 GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
522 GLB_GPIO_TEST_SEL_BASE = 1<<11,
872 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
873 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
899 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
1138 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1142 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1145 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1148 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1151 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1153 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1155 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1156 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1157 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1159 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1160 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1161 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1162 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1164 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1165 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1168 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1169 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1170 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1172 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1180 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1235 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1256 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1268 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1294 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1298 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1304 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1308 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1330 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1345 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1362 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1387 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1406 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1412 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1416 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1430 /* 00=1x; 01=2x; 10=3x; 11=4x */
1432 /* 00=dis; 01=1x; 10=2x; 11=3x */
1442 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1454 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1458 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1478 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1481 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1516 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1519 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1533 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1542 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1548 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1559 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1562 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1590 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1598 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1606 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1616 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1619 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1633 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1634 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1635 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1636 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1637 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1638 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1640 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1641 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1642 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1643 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1644 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1645 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1648 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1649 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1650 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1651 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1659 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1660 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1661 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1664 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1665 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1666 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1730 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1742 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1747 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1763 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1774 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1782 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1801 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1803 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1813 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1820 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1822 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1829 #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
1832 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1843 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
2019 GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
2053 GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */
2088 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,