Lines Matching +full:ignore +full:- +full:power +full:- +full:on +full:- +full:sel
1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
150 LED_STAT_ON = 1<<1, /* Status LED on */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
158 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
160 PC_VCC_ON = 1<<1, /* Switch VCC On */
173 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
240 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
241 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
242 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
243 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
244 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
245 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
269 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
284 TIM_T_ON = 1<<2, /* Test mode on */
346 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
351 BSC_T_ON = 1<<2, /* Test mode on */
373 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
430 * Bank 4 - 5
489 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
520 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
607 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
615 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
619 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
642 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
649 LED_T_ON = 1<<2, /* LED Counter Test mode On */
656 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
660 LED_REG_ON = 1<<1, /* switch LED on */
680 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
683 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
807 #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
808 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
856 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
858 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
908 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
927 ,* XMAC-PHY Registers, indirect addressed over the XMAC
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
936 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
944 * Broadcom-PHY Registers, indirect addressed over XMAC
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
953 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
956 /* Broadcom-specific registers */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
958 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
973 * Marvel-PHY Registers, indirect addressed over GMAC
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
982 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
985 /* Marvel-specific registers */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
987 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1017 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1018 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1020 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1036 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1038 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1062 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1063 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1064 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1076 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1077 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1078 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1079 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1127 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1130 /* Broadcom-Specific */
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1141 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1142 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1156 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1157 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1158 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1159 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1164 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1169 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1175 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1227 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1246 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1247 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1285 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1286 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1289 /** Marvell-Specific */
1297 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1298 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1299 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1300 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1301 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1309 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1326 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1335 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1341 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1402 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1406 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1415 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1441 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1530 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1540 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1599 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1661 * MIB Counters base address definitions (low word) -
1678 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1679 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1680 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1681 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1682 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1683 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1696 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1697 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1698 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1699 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1700 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1701 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1716 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1726 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1733 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1742 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1744 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1745 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1746 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1754 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1767 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1793 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1830 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1831 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1852 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1856 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1859 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1863 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1874 GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
1892 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1894 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1896 GMC_PAUSE_ON = 1<<3, /* Pause On */
1904 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1940 /* auto-negotiation with limited advertised speeds */
2071 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2072 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2073 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2074 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2075 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2101 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2102 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2103 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2104 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2105 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2112 XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
2166 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2184 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2246 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2249 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2255 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2257 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2296 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2297 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2298 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2299 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2300 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2318 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2319 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2333 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2334 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2335 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2336 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2337 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2350 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2427 FLOW_MODE_NONE = 1, /* No Flow-Control */
2478 return readl(hw->regs + reg); in skge_read32()
2483 return readw(hw->regs + reg); in skge_read16()
2488 return readb(hw->regs + reg); in skge_read8()
2493 writel(val, hw->regs + reg); in skge_write32()
2498 writew(val, hw->regs + reg); in skge_write16()
2503 writeb(val, hw->regs + reg); in skge_write8()
2509 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2553 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))