Lines Matching +full:hw +full:- +full:timeout +full:- +full:ms
1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
167 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
169 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
170 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
171 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
172 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
269 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
371 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
380 /* Timeout values */
381 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
382 #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
384 #define SK_RI_TO_53 36 /* RAM interface timeout */
389 PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
390 PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
391 PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
392 PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
393 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
394 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
395 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
396 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
397 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
398 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
399 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
400 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
430 * Bank 4 - 5
489 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
543 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
544 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
798 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
799 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
801 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
803 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
804 /* 215 ms at 78.12 MHz */
856 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
858 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
908 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
927 ,* XMAC-PHY Registers, indirect addressed over the XMAC
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
936 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
944 * Broadcom-PHY Registers, indirect addressed over XMAC
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
953 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
956 /* Broadcom-specific registers */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
958 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
973 * Marvel-PHY Registers, indirect addressed over GMAC
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
982 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
985 /* Marvel-specific registers */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
987 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1017 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1020 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1036 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1038 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1062 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1063 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1064 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1076 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1077 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1078 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1079 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1127 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1130 /* Broadcom-Specific */
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1141 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1142 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1156 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1157 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1158 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1159 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1164 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1169 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1246 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1247 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1285 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1286 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1289 /** Marvell-Specific */
1297 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1298 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1299 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1300 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1301 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1309 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1326 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1402 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1406 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1441 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1484 PULS_21MS = 1, /* 21 ms to 42 ms */
1485 PULS_42MS = 2, /* 42 ms to 84 ms */
1486 PULS_84MS = 3, /* 84 ms to 170 ms */
1487 PULS_170MS = 4, /* 170 ms to 340 ms */
1488 PULS_340MS = 5, /* 340 ms to 670 ms */
1489 PULS_670MS = 6, /* 670 ms to 1.3 s */
1495 BLINK_42MS = 0, /* 42 ms */
1496 BLINK_84MS = 1, /* 84 ms */
1497 BLINK_170MS = 2, /* 170 ms */
1498 BLINK_340MS = 3, /* 340 ms */
1499 BLINK_670MS = 4, /* 670 ms */
1599 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1661 * MIB Counters base address definitions (low word) -
1678 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1679 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1680 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1681 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1682 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1683 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1696 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1697 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1698 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1699 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1700 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1701 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1716 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1726 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1733 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1742 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1744 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1745 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1746 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1754 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1767 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1793 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1830 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1831 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1904 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1940 /* auto-negotiation with limited advertised speeds */
2071 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2072 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2073 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2074 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2075 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2101 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2102 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2103 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2104 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2105 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2166 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2184 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2296 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2297 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2298 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2299 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2300 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2318 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2319 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2333 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2334 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2335 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2336 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2337 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2350 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2427 FLOW_MODE_NONE = 1, /* No Flow-Control */
2445 struct skge_hw *hw; member
2476 static inline u32 skge_read32(const struct skge_hw *hw, int reg) in skge_read32() argument
2478 return readl(hw->regs + reg); in skge_read32()
2481 static inline u16 skge_read16(const struct skge_hw *hw, int reg) in skge_read16() argument
2483 return readw(hw->regs + reg); in skge_read16()
2486 static inline u8 skge_read8(const struct skge_hw *hw, int reg) in skge_read8() argument
2488 return readb(hw->regs + reg); in skge_read8()
2491 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val) in skge_write32() argument
2493 writel(val, hw->regs + reg); in skge_write32()
2496 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val) in skge_write16() argument
2498 writew(val, hw->regs + reg); in skge_write16()
2501 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val) in skge_write8() argument
2503 writeb(val, hw->regs + reg); in skge_write8()
2509 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2511 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg) in xm_read32() argument
2514 v = skge_read16(hw, SK_XMAC_REG(port, reg)); in xm_read32()
2515 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16; in xm_read32()
2519 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg) in xm_read16() argument
2521 return skge_read16(hw, SK_XMAC_REG(port,reg)); in xm_read16()
2524 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v) in xm_write32() argument
2526 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff); in xm_write32()
2527 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16); in xm_write32()
2530 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v) in xm_write16() argument
2532 skge_write16(hw, SK_XMAC_REG(port,r), v); in xm_write16()
2535 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg, in xm_outhash() argument
2538 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8)); in xm_outhash()
2539 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8)); in xm_outhash()
2540 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8)); in xm_outhash()
2541 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8)); in xm_outhash()
2544 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg, in xm_outaddr() argument
2547 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8)); in xm_outaddr()
2548 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8)); in xm_outaddr()
2549 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8)); in xm_outaddr()
2553 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2555 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg) in gma_read16() argument
2557 return skge_read16(hw, SK_GMAC_REG(port,reg)); in gma_read16()
2560 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg) in gma_read32() argument
2562 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg)) in gma_read32()
2563 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16); in gma_read32()
2566 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v) in gma_write16() argument
2568 skge_write16(hw, SK_GMAC_REG(port,r), v); in gma_write16()
2571 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg, in gma_set_addr() argument
2574 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); in gma_set_addr()
2575 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); in gma_set_addr()
2576 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); in gma_set_addr()