Lines Matching +full:dma +full:- +full:poll +full:- +full:cnt
1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
179 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
181 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
269 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
282 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
415 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
430 * Bank 4 - 5
489 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
540 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
549 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
550 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
551 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
552 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
554 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
555 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
556 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
557 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
636 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
637 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
638 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
645 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
646 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
647 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
782 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
791 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
792 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
793 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
794 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
825 /* Descriptor Poll Timer Registers */
826 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
827 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
828 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
830 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
856 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
858 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
908 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
927 ,* XMAC-PHY Registers, indirect addressed over the XMAC
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
936 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
944 * Broadcom-PHY Registers, indirect addressed over XMAC
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
953 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
956 /* Broadcom-specific registers */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
958 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
963 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
964 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
973 * Marvel-PHY Registers, indirect addressed over GMAC
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
982 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
985 /* Marvel-specific registers */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
987 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1017 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1020 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1036 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1038 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1062 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1063 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1064 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1076 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1077 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1078 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1079 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1127 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1130 /* Broadcom-Specific */
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1141 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1142 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1156 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1157 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1158 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1159 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1164 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1169 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1215 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1216 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1246 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1247 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1285 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1286 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1289 /** Marvell-Specific */
1297 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1298 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1299 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1300 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1301 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1309 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1326 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1402 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1406 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1441 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1599 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1661 * MIB Counters base address definitions (low word) -
1678 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1679 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1680 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1681 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1682 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1683 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1696 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1697 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1698 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1699 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1700 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1701 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1716 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1726 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1733 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1742 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1744 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1745 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1746 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1754 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1767 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1793 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1830 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1831 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1904 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1940 /* auto-negotiation with limited advertised speeds */
2052 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2053 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2059 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2067 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2068 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2071 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2072 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2073 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2074 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2075 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2077 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2082 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2084 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2087 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2089 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2090 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2091 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2094 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2096 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2097 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2098 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2101 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2102 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2103 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2104 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2105 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2166 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2184 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2296 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2297 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2298 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2299 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2300 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2301 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2302 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2303 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2304 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2305 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2306 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2307 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2308 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2309 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2310 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2311 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2312 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2313 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2314 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2315 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2318 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2319 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2321 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2322 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2324 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2333 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2334 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2335 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2336 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2337 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2338 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2339 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2340 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2341 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2342 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2343 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2344 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2345 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2347 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2348 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2350 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2351 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2352 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2353 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2354 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2355 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2357 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2427 FLOW_MODE_NONE = 1, /* No Flow-Control */
2467 dma_addr_t dma; member
2478 return readl(hw->regs + reg); in skge_read32()
2483 return readw(hw->regs + reg); in skge_read16()
2488 return readb(hw->regs + reg); in skge_read8()
2493 writel(val, hw->regs + reg); in skge_write32()
2498 writew(val, hw->regs + reg); in skge_write16()
2503 writeb(val, hw->regs + reg); in skge_write8()
2509 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2553 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))