Lines Matching +full:11 +full:w
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
191 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
219 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
391 PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
528 /* GPHY address (bits 15..11 of SMI control reg) */
566 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
718 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
903 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
930 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
931 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
937 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
947 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
954 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
960 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
962 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
963 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
964 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
966 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
969 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
976 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
983 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
989 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
991 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
993 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
994 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
995 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
997 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
998 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
999 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1000 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1002 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1003 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1006 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1007 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1008 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1010 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1018 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1073 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1107 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1135 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1148 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1162 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1168 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1186 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1205 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1210 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1214 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1218 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1222 /* Bit 11: reserved */
1238 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1252 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1257 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1276 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1277 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1278 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1279 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1295 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1325 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1331 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1335 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1355 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1364 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1381 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1406 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1425 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1431 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1435 PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
1446 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1447 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1458 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1462 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1502 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1505 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1519 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1528 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1534 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1555 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1564 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1567 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1595 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1603 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1606 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1620 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1621 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1622 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1624 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1625 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1627 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1628 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1629 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1630 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1631 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1632 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1635 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1636 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1637 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1638 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1646 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1647 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1648 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1651 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1652 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1653 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1718 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1730 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1735 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1752 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1763 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1771 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1787 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1789 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1796 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1802 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1804 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
1811 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1814 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1826 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1921 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1976 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
2004 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2005 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2006 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2007 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2008 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2009 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2010 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2011 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2012 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2013 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2014 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2015 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2016 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2017 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2019 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2020 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2021 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2022 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2023 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2024 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2025 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2026 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2027 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2030 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2035 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2036 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2037 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2038 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2039 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2040 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2042 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2046 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2049 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2050 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2108 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2111 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
2125 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2136 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2140 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2144 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2148 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2164 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2174 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2180 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2196 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2204 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2205 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2208 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2209 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2210 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2219 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2233 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2234 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2235 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2243 /* XM_MODE 32 bit r/w Mode Register */
2264 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2282 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2294 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2314 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2331 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2347 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */