Lines Matching full:hw
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
113 static inline bool is_genesis(const struct skge_hw *hw) in is_genesis() argument
116 return hw->chip_id == CHIP_ID_GENESIS; in is_genesis()
136 const void __iomem *io = skge->hw->regs; in skge_get_regs()
149 static u32 wol_supported(const struct skge_hw *hw) in wol_supported() argument
151 if (is_genesis(hw)) in wol_supported()
154 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in wol_supported()
162 struct skge_hw *hw = skge->hw; in skge_wol_init() local
166 skge_write16(hw, B0_CTST, CS_RST_CLR); in skge_wol_init()
167 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); in skge_wol_init()
170 skge_write8(hw, B0_POWER_CTRL, in skge_wol_init()
174 if (hw->chip_id == CHIP_ID_YUKON_LITE && in skge_wol_init()
175 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in skge_wol_init()
176 u32 reg = skge_read32(hw, B2_GP_IO); in skge_wol_init()
179 skge_write32(hw, B2_GP_IO, reg); in skge_wol_init()
182 skge_write32(hw, SK_REG(port, GPHY_CTRL), in skge_wol_init()
187 skge_write32(hw, SK_REG(port, GPHY_CTRL), in skge_wol_init()
192 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in skge_wol_init()
195 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, in skge_wol_init()
199 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); in skge_wol_init()
200 gm_phy_write(hw, port, PHY_MARV_CTRL, in skge_wol_init()
206 gma_write16(hw, port, GM_GP_CTRL, in skge_wol_init()
211 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), in skge_wol_init()
215 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); in skge_wol_init()
228 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); in skge_wol_init()
231 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); in skge_wol_init()
238 wol->supported = wol_supported(skge->hw); in skge_get_wol()
245 struct skge_hw *hw = skge->hw; in skge_set_wol() local
247 if ((wol->wolopts & ~wol_supported(hw)) || in skge_set_wol()
248 !device_can_wakeup(&hw->pdev->dev)) in skge_set_wol()
253 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); in skge_set_wol()
261 static u32 skge_supported_modes(const struct skge_hw *hw) in skge_supported_modes() argument
265 if (hw->copper) { in skge_supported_modes()
275 if (is_genesis(hw)) in skge_supported_modes()
281 else if (hw->chip_id == CHIP_ID_YUKON) in skge_supported_modes()
296 struct skge_hw *hw = skge->hw; in skge_get_link_ksettings() local
299 supported = skge_supported_modes(hw); in skge_get_link_ksettings()
301 if (hw->copper) { in skge_get_link_ksettings()
303 cmd->base.phy_address = hw->phy_addr; in skge_get_link_ksettings()
324 const struct skge_hw *hw = skge->hw; in skge_set_link_ksettings() local
325 u32 supported = skge_supported_modes(hw); in skge_set_link_ksettings()
399 strscpy(info->bus_info, pci_name(skge->hw->pdev), in skge_get_drvinfo()
449 if (is_genesis(skge->hw)) in skge_get_ethtool_stats()
464 if (is_genesis(skge->hw)) in skge_get_stats()
602 static inline u32 hwkhz(const struct skge_hw *hw) in hwkhz() argument
604 return is_genesis(hw) ? 53125 : 78125; in hwkhz()
608 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) in skge_clk2usec() argument
610 return (ticks * 1000) / hwkhz(hw); in skge_clk2usec()
614 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) in skge_usecs2clk() argument
616 return hwkhz(hw) * usec / 1000; in skge_usecs2clk()
625 struct skge_hw *hw = skge->hw; in skge_get_coalesce() local
631 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { in skge_get_coalesce()
632 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); in skge_get_coalesce()
633 u32 msk = skge_read32(hw, B2_IRQM_MSK); in skge_get_coalesce()
651 struct skge_hw *hw = skge->hw; in skge_set_coalesce() local
653 u32 msk = skge_read32(hw, B2_IRQM_MSK); in skge_set_coalesce()
676 skge_write32(hw, B2_IRQM_MSK, msk); in skge_set_coalesce()
678 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); in skge_set_coalesce()
680 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); in skge_set_coalesce()
681 skge_write32(hw, B2_IRQM_CTRL, TIM_START); in skge_set_coalesce()
689 struct skge_hw *hw = skge->hw; in skge_led() local
692 spin_lock_bh(&hw->phy_lock); in skge_led()
693 if (is_genesis(hw)) { in skge_led()
696 if (hw->phy_type == SK_PHY_BCOM) in skge_led()
697 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); in skge_led()
699 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); in skge_led()
700 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); in skge_led()
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); in skge_led()
703 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); in skge_led()
704 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); in skge_led()
708 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); in skge_led()
709 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); in skge_led()
711 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); in skge_led()
712 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); in skge_led()
717 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); in skge_led()
718 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); in skge_led()
719 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); in skge_led()
721 if (hw->phy_type == SK_PHY_BCOM) in skge_led()
722 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); in skge_led()
724 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); in skge_led()
725 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); in skge_led()
726 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); in skge_led()
733 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
734 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
742 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, in skge_led()
748 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
754 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
755 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
763 spin_unlock_bh(&hw->phy_lock); in skge_led()
797 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2); in skge_get_eeprom_len()
830 struct pci_dev *pdev = skge->hw->pdev; in skge_get_eeprom()
856 struct pci_dev *pdev = skge->hw->pdev; in skge_set_eeprom()
948 map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize, in skge_rx_setup()
951 if (dma_mapping_error(&skge->hw->pdev->dev, map)) in skge_rx_setup()
990 struct skge_hw *hw = skge->hw; in skge_rx_clean() local
999 dma_unmap_single(&hw->pdev->dev, in skge_rx_clean()
1058 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), in skge_link_up()
1073 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); in skge_link_down()
1080 static void xm_link_down(struct skge_hw *hw, int port) in xm_link_down() argument
1082 struct net_device *dev = hw->dev[port]; in xm_link_down()
1085 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); in xm_link_down()
1091 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) in __xm_phy_read() argument
1095 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); in __xm_phy_read()
1096 *val = xm_read16(hw, port, XM_PHY_DATA); in __xm_phy_read()
1098 if (hw->phy_type == SK_PHY_XMAC) in __xm_phy_read()
1102 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) in __xm_phy_read()
1109 *val = xm_read16(hw, port, XM_PHY_DATA); in __xm_phy_read()
1114 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) in xm_phy_read() argument
1117 if (__xm_phy_read(hw, port, reg, &v)) in xm_phy_read()
1118 pr_warn("%s: phy read timed out\n", hw->dev[port]->name); in xm_phy_read()
1122 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) in xm_phy_write() argument
1126 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); in xm_phy_write()
1128 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) in xm_phy_write()
1135 xm_write16(hw, port, XM_PHY_DATA, val); in xm_phy_write()
1137 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) in xm_phy_write()
1144 static void genesis_init(struct skge_hw *hw) in genesis_init() argument
1147 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); in genesis_init()
1148 skge_write8(hw, B2_BSC_CTRL, BSC_START); in genesis_init()
1151 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); in genesis_init()
1154 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); in genesis_init()
1155 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); in genesis_init()
1156 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); in genesis_init()
1157 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); in genesis_init()
1159 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_init()
1160 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_init()
1161 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_init()
1162 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_init()
1165 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); in genesis_init()
1166 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); in genesis_init()
1167 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); in genesis_init()
1168 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); in genesis_init()
1169 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); in genesis_init()
1172 static void genesis_reset(struct skge_hw *hw, int port) in genesis_reset() argument
1177 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in genesis_reset()
1180 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); in genesis_reset()
1181 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); in genesis_reset()
1182 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ in genesis_reset()
1183 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ in genesis_reset()
1184 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ in genesis_reset()
1187 if (hw->phy_type == SK_PHY_BCOM) in genesis_reset()
1188 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); in genesis_reset()
1190 xm_outhash(hw, port, XM_HSM, zero); in genesis_reset()
1193 reg = xm_read32(hw, port, XM_MODE); in genesis_reset()
1194 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); in genesis_reset()
1195 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); in genesis_reset()
1216 static void bcom_check_link(struct skge_hw *hw, int port) in bcom_check_link() argument
1218 struct net_device *dev = hw->dev[port]; in bcom_check_link()
1223 xm_phy_read(hw, port, PHY_BCOM_STAT); in bcom_check_link()
1224 status = xm_phy_read(hw, port, PHY_BCOM_STAT); in bcom_check_link()
1227 xm_link_down(hw, port); in bcom_check_link()
1237 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); in bcom_check_link()
1243 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); in bcom_check_link()
1284 struct skge_hw *hw = skge->hw; in bcom_phy_init() local
1304 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); in bcom_phy_init()
1307 r = xm_read16(hw, port, XM_MMU_CMD); in bcom_phy_init()
1309 xm_write16(hw, port, XM_MMU_CMD, r); in bcom_phy_init()
1318 xm_phy_write(hw, port, in bcom_phy_init()
1328 xm_phy_write(hw, port, in bcom_phy_init()
1337 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); in bcom_phy_init()
1339 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); in bcom_phy_init()
1342 xm_read16(hw, port, XM_ISRC); in bcom_phy_init()
1358 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); in bcom_phy_init()
1365 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); in bcom_phy_init()
1369 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, in bcom_phy_init()
1373 if (hw->dev[port]->mtu > ETH_DATA_LEN) { in bcom_phy_init()
1374 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, in bcom_phy_init()
1381 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); in bcom_phy_init()
1382 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); in bcom_phy_init()
1385 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); in bcom_phy_init()
1390 struct skge_hw *hw = skge->hw; in xm_phy_init() local
1402 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); in xm_phy_init()
1416 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); in xm_phy_init()
1425 struct skge_hw *hw = skge->hw; in xm_check_link() local
1430 xm_phy_read(hw, port, PHY_XMAC_STAT); in xm_check_link()
1431 status = xm_phy_read(hw, port, PHY_XMAC_STAT); in xm_check_link()
1434 xm_link_down(hw, port); in xm_check_link()
1444 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); in xm_check_link()
1450 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); in xm_check_link()
1499 struct skge_hw *hw = skge->hw; in xm_link_timer() local
1507 spin_lock_irqsave(&hw->phy_lock, flags); in xm_link_timer()
1514 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) in xm_link_timer()
1520 u16 msk = xm_read16(hw, port, XM_IMSK); in xm_link_timer()
1522 xm_write16(hw, port, XM_IMSK, msk); in xm_link_timer()
1523 xm_read16(hw, port, XM_ISRC); in xm_link_timer()
1529 spin_unlock_irqrestore(&hw->phy_lock, flags); in xm_link_timer()
1532 static void genesis_mac_init(struct skge_hw *hw, int port) in genesis_mac_init() argument
1534 struct net_device *dev = hw->dev[port]; in genesis_mac_init()
1536 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; in genesis_mac_init()
1542 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), in genesis_mac_init()
1544 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) in genesis_mac_init()
1553 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); in genesis_mac_init()
1560 if (hw->phy_type != SK_PHY_XMAC) { in genesis_mac_init()
1562 r = skge_read32(hw, B2_GP_IO); in genesis_mac_init()
1568 skge_write32(hw, B2_GP_IO, r); in genesis_mac_init()
1571 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); in genesis_mac_init()
1575 switch (hw->phy_type) { in genesis_mac_init()
1581 bcom_check_link(hw, port); in genesis_mac_init()
1585 xm_outaddr(hw, port, XM_SA, dev->dev_addr); in genesis_mac_init()
1589 xm_outaddr(hw, port, XM_EXM(i), zero); in genesis_mac_init()
1592 xm_write16(hw, port, XM_STAT_CMD, in genesis_mac_init()
1595 xm_write16(hw, port, XM_STAT_CMD, in genesis_mac_init()
1599 xm_write16(hw, port, XM_RX_HI_WM, 1450); in genesis_mac_init()
1614 xm_write16(hw, port, XM_RX_CMD, r); in genesis_mac_init()
1617 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); in genesis_mac_init()
1620 if (hw->ports > 1 && jumbo) in genesis_mac_init()
1621 xm_write16(hw, port, XM_TX_THR, 1020); in genesis_mac_init()
1623 xm_write16(hw, port, XM_TX_THR, 512); in genesis_mac_init()
1639 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); in genesis_mac_init()
1647 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); in genesis_mac_init()
1654 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); in genesis_mac_init()
1657 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); in genesis_mac_init()
1660 skge_write8(hw, B3_MA_TOINI_RX1, 72); in genesis_mac_init()
1661 skge_write8(hw, B3_MA_TOINI_RX2, 72); in genesis_mac_init()
1662 skge_write8(hw, B3_MA_TOINI_TX1, 72); in genesis_mac_init()
1663 skge_write8(hw, B3_MA_TOINI_TX2, 72); in genesis_mac_init()
1665 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_mac_init()
1666 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_mac_init()
1667 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_mac_init()
1668 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_mac_init()
1671 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); in genesis_mac_init()
1672 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); in genesis_mac_init()
1673 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); in genesis_mac_init()
1676 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); in genesis_mac_init()
1677 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); in genesis_mac_init()
1678 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); in genesis_mac_init()
1682 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH); in genesis_mac_init()
1685 skge_write16(hw, B3_PA_CTRL, in genesis_mac_init()
1692 struct skge_hw *hw = skge->hw; in genesis_stop() local
1698 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_stop()
1700 xm_write16(hw, port, XM_MMU_CMD, cmd); in genesis_stop()
1702 genesis_reset(hw, port); in genesis_stop()
1705 skge_write16(hw, B3_PA_CTRL, in genesis_stop()
1709 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); in genesis_stop()
1711 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); in genesis_stop()
1712 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) in genesis_stop()
1717 if (hw->phy_type != SK_PHY_XMAC) { in genesis_stop()
1718 u32 reg = skge_read32(hw, B2_GP_IO); in genesis_stop()
1726 skge_write32(hw, B2_GP_IO, reg); in genesis_stop()
1727 skge_read32(hw, B2_GP_IO); in genesis_stop()
1730 xm_write16(hw, port, XM_MMU_CMD, in genesis_stop()
1731 xm_read16(hw, port, XM_MMU_CMD) in genesis_stop()
1734 xm_read16(hw, port, XM_MMU_CMD); in genesis_stop()
1740 struct skge_hw *hw = skge->hw; in genesis_get_stats() local
1745 xm_write16(hw, port, in genesis_get_stats()
1749 while (xm_read16(hw, port, XM_STAT_CMD) in genesis_get_stats()
1757 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 in genesis_get_stats()
1758 | xm_read32(hw, port, XM_TXO_OK_LO); in genesis_get_stats()
1759 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 in genesis_get_stats()
1760 | xm_read32(hw, port, XM_RXO_OK_LO); in genesis_get_stats()
1763 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); in genesis_get_stats()
1766 static void genesis_mac_intr(struct skge_hw *hw, int port) in genesis_mac_intr() argument
1768 struct net_device *dev = hw->dev[port]; in genesis_mac_intr()
1770 u16 status = xm_read16(hw, port, XM_ISRC); in genesis_mac_intr()
1775 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) { in genesis_mac_intr()
1776 xm_link_down(hw, port); in genesis_mac_intr()
1781 xm_write32(hw, port, XM_MODE, XM_MD_FTF); in genesis_mac_intr()
1788 struct skge_hw *hw = skge->hw; in genesis_link_up() local
1793 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_link_up()
1807 xm_write16(hw, port, XM_MMU_CMD, cmd); in genesis_link_up()
1809 mode = xm_read32(hw, port, XM_MODE); in genesis_link_up()
1823 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); in genesis_link_up()
1826 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); in genesis_link_up()
1835 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); in genesis_link_up()
1838 xm_write32(hw, port, XM_MODE, mode); in genesis_link_up()
1841 msk = xm_read16(hw, port, XM_IMSK); in genesis_link_up()
1843 xm_write16(hw, port, XM_IMSK, msk); in genesis_link_up()
1845 xm_read16(hw, port, XM_ISRC); in genesis_link_up()
1848 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_link_up()
1849 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) in genesis_link_up()
1856 if (hw->phy_type == SK_PHY_BCOM) { in genesis_link_up()
1857 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, in genesis_link_up()
1858 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) in genesis_link_up()
1860 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); in genesis_link_up()
1864 xm_write16(hw, port, XM_MMU_CMD, in genesis_link_up()
1872 struct skge_hw *hw = skge->hw; in bcom_phy_intr() local
1876 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); in bcom_phy_intr()
1882 hw->dev[port]->name); in bcom_phy_intr()
1888 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); in bcom_phy_intr()
1889 xm_phy_write(hw, port, PHY_BCOM_CTRL, in bcom_phy_intr()
1891 xm_phy_write(hw, port, PHY_BCOM_CTRL, in bcom_phy_intr()
1896 bcom_check_link(hw, port); in bcom_phy_intr()
1900 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) in gm_phy_write() argument
1904 gma_write16(hw, port, GM_SMI_DATA, val); in gm_phy_write()
1905 gma_write16(hw, port, GM_SMI_CTRL, in gm_phy_write()
1906 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); in gm_phy_write()
1910 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) in gm_phy_write()
1914 pr_warn("%s: phy write timeout\n", hw->dev[port]->name); in gm_phy_write()
1918 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) in __gm_phy_read() argument
1922 gma_write16(hw, port, GM_SMI_CTRL, in __gm_phy_read()
1923 GM_SMI_CT_PHY_AD(hw->phy_addr) in __gm_phy_read()
1928 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) in __gm_phy_read()
1934 *val = gma_read16(hw, port, GM_SMI_DATA); in __gm_phy_read()
1938 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) in gm_phy_read() argument
1941 if (__gm_phy_read(hw, port, reg, &v)) in gm_phy_read()
1942 pr_warn("%s: phy read timeout\n", hw->dev[port]->name); in gm_phy_read()
1947 static void yukon_init(struct skge_hw *hw, int port) in yukon_init() argument
1949 struct skge_port *skge = netdev_priv(hw->dev[port]); in yukon_init()
1953 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); in yukon_init()
1961 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); in yukon_init()
1964 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_init()
1969 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_init()
1976 if (hw->copper) { in yukon_init()
2022 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); in yukon_init()
2024 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); in yukon_init()
2025 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_init()
2029 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); in yukon_init()
2031 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); in yukon_init()
2034 static void yukon_reset(struct skge_hw *hw, int port) in yukon_reset() argument
2036 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ in yukon_reset()
2037 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ in yukon_reset()
2038 gma_write16(hw, port, GM_MC_ADDR_H2, 0); in yukon_reset()
2039 gma_write16(hw, port, GM_MC_ADDR_H3, 0); in yukon_reset()
2040 gma_write16(hw, port, GM_MC_ADDR_H4, 0); in yukon_reset()
2042 gma_write16(hw, port, GM_RX_CTRL, in yukon_reset()
2043 gma_read16(hw, port, GM_RX_CTRL) in yukon_reset()
2048 static int is_yukon_lite_a0(struct skge_hw *hw) in is_yukon_lite_a0() argument
2053 if (hw->chip_id != CHIP_ID_YUKON) in is_yukon_lite_a0()
2056 reg = skge_read32(hw, B2_FAR); in is_yukon_lite_a0()
2057 skge_write8(hw, B2_FAR + 3, 0xff); in is_yukon_lite_a0()
2058 ret = (skge_read8(hw, B2_FAR + 3) != 0); in is_yukon_lite_a0()
2059 skge_write32(hw, B2_FAR, reg); in is_yukon_lite_a0()
2063 static void yukon_mac_init(struct skge_hw *hw, int port) in yukon_mac_init() argument
2065 struct skge_port *skge = netdev_priv(hw->dev[port]); in yukon_mac_init()
2068 const u8 *addr = hw->dev[port]->dev_addr; in yukon_mac_init()
2071 if (hw->chip_id == CHIP_ID_YUKON_LITE && in yukon_mac_init()
2072 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in yukon_mac_init()
2073 reg = skge_read32(hw, B2_GP_IO); in yukon_mac_init()
2075 skge_write32(hw, B2_GP_IO, reg); in yukon_mac_init()
2079 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in yukon_mac_init()
2080 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_mac_init()
2083 if (hw->chip_id == CHIP_ID_YUKON_LITE && in yukon_mac_init()
2084 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in yukon_mac_init()
2085 reg = skge_read32(hw, B2_GP_IO); in yukon_mac_init()
2088 skge_write32(hw, B2_GP_IO, reg); in yukon_mac_init()
2094 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; in yukon_mac_init()
2097 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); in yukon_mac_init()
2098 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); in yukon_mac_init()
2099 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); in yukon_mac_init()
2103 gma_write16(hw, port, GM_GP_CTRL, in yukon_mac_init()
2104 gma_read16(hw, port, GM_GP_CTRL) | reg); in yukon_mac_init()
2127 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_mac_init()
2140 gma_write16(hw, port, GM_GP_CTRL, reg); in yukon_mac_init()
2141 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); in yukon_mac_init()
2143 yukon_init(hw, port); in yukon_mac_init()
2146 reg = gma_read16(hw, port, GM_PHY_ADDR); in yukon_mac_init()
2147 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); in yukon_mac_init()
2150 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); in yukon_mac_init()
2151 gma_write16(hw, port, GM_PHY_ADDR, reg); in yukon_mac_init()
2154 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); in yukon_mac_init()
2157 gma_write16(hw, port, GM_RX_CTRL, in yukon_mac_init()
2161 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); in yukon_mac_init()
2164 gma_write16(hw, port, GM_TX_PARAM, in yukon_mac_init()
2174 if (hw->dev[port]->mtu > ETH_DATA_LEN) in yukon_mac_init()
2177 gma_write16(hw, port, GM_SERIAL_MODE, reg); in yukon_mac_init()
2180 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); in yukon_mac_init()
2182 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); in yukon_mac_init()
2185 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); in yukon_mac_init()
2186 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); in yukon_mac_init()
2187 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); in yukon_mac_init()
2192 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); in yukon_mac_init()
2196 if (is_yukon_lite_a0(hw)) in yukon_mac_init()
2199 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); in yukon_mac_init()
2200 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); in yukon_mac_init()
2206 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); in yukon_mac_init()
2209 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); in yukon_mac_init()
2210 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); in yukon_mac_init()
2214 static void yukon_suspend(struct skge_hw *hw, int port) in yukon_suspend() argument
2218 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); in yukon_suspend()
2220 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); in yukon_suspend()
2222 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_suspend()
2224 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_suspend()
2227 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_suspend()
2229 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_suspend()
2234 struct skge_hw *hw = skge->hw; in yukon_stop() local
2237 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in yukon_stop()
2238 yukon_reset(hw, port); in yukon_stop()
2240 gma_write16(hw, port, GM_GP_CTRL, in yukon_stop()
2241 gma_read16(hw, port, GM_GP_CTRL) in yukon_stop()
2243 gma_read16(hw, port, GM_GP_CTRL); in yukon_stop()
2245 yukon_suspend(hw, port); in yukon_stop()
2248 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in yukon_stop()
2249 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_stop()
2254 struct skge_hw *hw = skge->hw; in yukon_get_stats() local
2258 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 in yukon_get_stats()
2259 | gma_read32(hw, port, GM_TXO_OK_LO); in yukon_get_stats()
2260 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 in yukon_get_stats()
2261 | gma_read32(hw, port, GM_RXO_OK_LO); in yukon_get_stats()
2264 data[i] = gma_read32(hw, port, in yukon_get_stats()
2268 static void yukon_mac_intr(struct skge_hw *hw, int port) in yukon_mac_intr() argument
2270 struct net_device *dev = hw->dev[port]; in yukon_mac_intr()
2272 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); in yukon_mac_intr()
2279 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); in yukon_mac_intr()
2284 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); in yukon_mac_intr()
2289 static u16 yukon_speed(const struct skge_hw *hw, u16 aux) in yukon_speed() argument
2303 struct skge_hw *hw = skge->hw; in yukon_link_up() local
2308 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); in yukon_link_up()
2310 reg = gma_read16(hw, port, GM_GP_CTRL); in yukon_link_up()
2316 gma_write16(hw, port, GM_GP_CTRL, reg); in yukon_link_up()
2318 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); in yukon_link_up()
2324 struct skge_hw *hw = skge->hw; in yukon_link_down() local
2328 ctrl = gma_read16(hw, port, GM_GP_CTRL); in yukon_link_down()
2330 gma_write16(hw, port, GM_GP_CTRL, ctrl); in yukon_link_down()
2333 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); in yukon_link_down()
2336 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); in yukon_link_down()
2341 yukon_init(hw, port); in yukon_link_down()
2346 struct skge_hw *hw = skge->hw; in yukon_phy_intr() local
2351 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); in yukon_phy_intr()
2352 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); in yukon_phy_intr()
2358 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) in yukon_phy_intr()
2364 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { in yukon_phy_intr()
2376 skge->speed = yukon_speed(hw, phystat); in yukon_phy_intr()
2395 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_phy_intr()
2397 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in yukon_phy_intr()
2403 skge->speed = yukon_speed(hw, phystat); in yukon_phy_intr()
2422 struct skge_hw *hw = skge->hw; in skge_phy_reset() local
2424 struct net_device *dev = hw->dev[port]; in skge_phy_reset()
2429 spin_lock_bh(&hw->phy_lock); in skge_phy_reset()
2430 if (is_genesis(hw)) { in skge_phy_reset()
2431 genesis_reset(hw, port); in skge_phy_reset()
2432 genesis_mac_init(hw, port); in skge_phy_reset()
2434 yukon_reset(hw, port); in skge_phy_reset()
2435 yukon_init(hw, port); in skge_phy_reset()
2437 spin_unlock_bh(&hw->phy_lock); in skge_phy_reset()
2447 struct skge_hw *hw = skge->hw; in skge_ioctl() local
2455 data->phy_id = hw->phy_addr; in skge_ioctl()
2460 spin_lock_bh(&hw->phy_lock); in skge_ioctl()
2462 if (is_genesis(hw)) in skge_ioctl()
2463 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2465 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2466 spin_unlock_bh(&hw->phy_lock); in skge_ioctl()
2472 spin_lock_bh(&hw->phy_lock); in skge_ioctl()
2473 if (is_genesis(hw)) in skge_ioctl()
2474 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2477 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2479 spin_unlock_bh(&hw->phy_lock); in skge_ioctl()
2485 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) in skge_ramset() argument
2493 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in skge_ramset()
2494 skge_write32(hw, RB_ADDR(q, RB_START), start); in skge_ramset()
2495 skge_write32(hw, RB_ADDR(q, RB_WP), start); in skge_ramset()
2496 skge_write32(hw, RB_ADDR(q, RB_RP), start); in skge_ramset()
2497 skge_write32(hw, RB_ADDR(q, RB_END), end); in skge_ramset()
2501 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), in skge_ramset()
2503 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), in skge_ramset()
2509 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in skge_ramset()
2512 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in skge_ramset()
2519 struct skge_hw *hw = skge->hw; in skge_qset() local
2524 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) in skge_qset()
2527 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset()
2528 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset()
2529 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset()
2530 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset()
2536 struct skge_hw *hw = skge->hw; in skge_up() local
2556 skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size, in skge_up()
2564 dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n"); in skge_up()
2582 if (hw->ports == 1) { in skge_up()
2583 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED, in skge_up()
2584 dev->name, hw); in skge_up()
2587 hw->pdev->irq, err); in skge_up()
2594 spin_lock_bh(&hw->phy_lock); in skge_up()
2595 if (is_genesis(hw)) in skge_up()
2596 genesis_mac_init(hw, port); in skge_up()
2598 yukon_mac_init(hw, port); in skge_up()
2599 spin_unlock_bh(&hw->phy_lock); in skge_up()
2602 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); in skge_up()
2603 ram_addr = hw->ram_offset + 2 * chunk * port; in skge_up()
2605 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); in skge_up()
2609 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); in skge_up()
2614 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); in skge_up()
2617 spin_lock_irq(&hw->hw_lock); in skge_up()
2618 hw->intr_mask |= portmask[port]; in skge_up()
2619 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_up()
2620 skge_read32(hw, B0_IMSK); in skge_up()
2621 spin_unlock_irq(&hw->hw_lock); in skge_up()
2635 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem, in skge_up()
2643 static void skge_rx_stop(struct skge_hw *hw, int port) in skge_rx_stop() argument
2645 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop()
2646 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), in skge_rx_stop()
2648 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop()
2654 struct skge_hw *hw = skge->hw; in skge_down() local
2664 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC) in skge_down()
2670 spin_lock_irq(&hw->hw_lock); in skge_down()
2671 hw->intr_mask &= ~portmask[port]; in skge_down()
2672 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask); in skge_down()
2673 skge_read32(hw, B0_IMSK); in skge_down()
2674 spin_unlock_irq(&hw->hw_lock); in skge_down()
2676 if (hw->ports == 1) in skge_down()
2677 free_irq(hw->pdev->irq, hw); in skge_down()
2679 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); in skge_down()
2680 if (is_genesis(hw)) in skge_down()
2686 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down()
2687 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in skge_down()
2692 skge_write8(hw, SK_REG(port, TXA_CTRL), in skge_down()
2696 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); in skge_down()
2697 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); in skge_down()
2700 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down()
2701 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in skge_down()
2704 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); in skge_down()
2706 skge_rx_stop(hw, port); in skge_down()
2708 if (is_genesis(hw)) { in skge_down()
2709 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); in skge_down()
2710 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); in skge_down()
2712 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); in skge_down()
2713 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); in skge_down()
2726 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem, in skge_down()
2743 struct skge_hw *hw = skge->hw; in skge_xmit_frame() local
2761 map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE); in skge_xmit_frame()
2762 if (dma_mapping_error(&hw->pdev->dev, map)) in skge_xmit_frame()
2778 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) in skge_xmit_frame()
2798 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0, in skge_xmit_frame()
2800 if (dma_mapping_error(&hw->pdev->dev, map)) in skge_xmit_frame()
2824 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame()
2842 dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr), in skge_xmit_frame()
2846 dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr), in skge_xmit_frame()
2852 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); in skge_xmit_frame()
2880 skge_tx_unmap(skge->hw->pdev, e, td->control); in skge_tx_clean()
2897 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); in skge_tx_timeout()
2936 struct skge_hw *hw = skge->hw; in genesis_set_multicast() local
2942 mode = xm_read32(hw, port, XM_MODE); in genesis_set_multicast()
2962 xm_write32(hw, port, XM_MODE, mode); in genesis_set_multicast()
2963 xm_outhash(hw, port, XM_HSM, filter); in genesis_set_multicast()
2976 struct skge_hw *hw = skge->hw; in yukon_set_multicast() local
2986 reg = gma_read16(hw, port, GM_RX_CTRL); in yukon_set_multicast()
3006 gma_write16(hw, port, GM_MC_ADDR_H1, in yukon_set_multicast()
3008 gma_write16(hw, port, GM_MC_ADDR_H2, in yukon_set_multicast()
3010 gma_write16(hw, port, GM_MC_ADDR_H3, in yukon_set_multicast()
3012 gma_write16(hw, port, GM_MC_ADDR_H4, in yukon_set_multicast()
3015 gma_write16(hw, port, GM_RX_CTRL, reg); in yukon_set_multicast()
3018 static inline u16 phy_length(const struct skge_hw *hw, u32 status) in phy_length() argument
3020 if (is_genesis(hw)) in phy_length()
3026 static inline int bad_phy_status(const struct skge_hw *hw, u32 status) in bad_phy_status() argument
3028 if (is_genesis(hw)) in bad_phy_status()
3039 if (is_genesis(skge->hw)) in skge_set_multicast()
3068 if (bad_phy_status(skge->hw, status)) in skge_rx_get()
3071 if (phy_length(skge->hw, status) != len) in skge_rx_get()
3079 dma_sync_single_for_cpu(&skge->hw->pdev->dev, in skge_rx_get()
3084 dma_sync_single_for_device(&skge->hw->pdev->dev, in skge_rx_get()
3107 dma_unmap_single(&skge->hw->pdev->dev, in skge_rx_get()
3128 if (is_genesis(skge->hw)) { in skge_rx_get()
3157 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_tx_done()
3165 skge_tx_unmap(skge->hw->pdev, e, control); in skge_tx_done()
3200 struct skge_hw *hw = skge->hw; in skge_poll() local
3207 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll()
3229 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); in skge_poll()
3234 spin_lock_irqsave(&hw->hw_lock, flags); in skge_poll()
3235 hw->intr_mask |= napimask[skge->port]; in skge_poll()
3236 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_poll()
3237 skge_read32(hw, B0_IMSK); in skge_poll()
3238 spin_unlock_irqrestore(&hw->hw_lock, flags); in skge_poll()
3247 static void skge_mac_parity(struct skge_hw *hw, int port) in skge_mac_parity() argument
3249 struct net_device *dev = hw->dev[port]; in skge_mac_parity()
3253 if (is_genesis(hw)) in skge_mac_parity()
3254 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), in skge_mac_parity()
3257 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ in skge_mac_parity()
3258 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), in skge_mac_parity()
3259 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in skge_mac_parity()
3263 static void skge_mac_intr(struct skge_hw *hw, int port) in skge_mac_intr() argument
3265 if (is_genesis(hw)) in skge_mac_intr()
3266 genesis_mac_intr(hw, port); in skge_mac_intr()
3268 yukon_mac_intr(hw, port); in skge_mac_intr()
3272 static void skge_error_irq(struct skge_hw *hw) in skge_error_irq() argument
3274 struct pci_dev *pdev = hw->pdev; in skge_error_irq()
3275 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); in skge_error_irq()
3277 if (is_genesis(hw)) { in skge_error_irq()
3280 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); in skge_error_irq()
3282 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); in skge_error_irq()
3286 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); in skge_error_irq()
3291 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); in skge_error_irq()
3296 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); in skge_error_irq()
3300 skge_mac_parity(hw, 0); in skge_error_irq()
3303 skge_mac_parity(hw, 1); in skge_error_irq()
3307 hw->dev[0]->name); in skge_error_irq()
3308 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); in skge_error_irq()
3313 hw->dev[1]->name); in skge_error_irq()
3314 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); in skge_error_irq()
3328 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_error_irq()
3332 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_error_irq()
3335 hwstatus = skge_read32(hw, B0_HWE_ISRC); in skge_error_irq()
3337 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); in skge_error_irq()
3338 hw->intr_mask &= ~IS_HW_ERR; in skge_error_irq()
3350 struct skge_hw *hw = from_tasklet(hw, t, phy_task); in skge_extirq() local
3353 for (port = 0; port < hw->ports; port++) { in skge_extirq()
3354 struct net_device *dev = hw->dev[port]; in skge_extirq()
3359 spin_lock(&hw->phy_lock); in skge_extirq()
3360 if (!is_genesis(hw)) in skge_extirq()
3362 else if (hw->phy_type == SK_PHY_BCOM) in skge_extirq()
3364 spin_unlock(&hw->phy_lock); in skge_extirq()
3368 spin_lock_irq(&hw->hw_lock); in skge_extirq()
3369 hw->intr_mask |= IS_EXT_REG; in skge_extirq()
3370 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_extirq()
3371 skge_read32(hw, B0_IMSK); in skge_extirq()
3372 spin_unlock_irq(&hw->hw_lock); in skge_extirq()
3377 struct skge_hw *hw = dev_id; in skge_intr() local
3381 spin_lock(&hw->hw_lock); in skge_intr()
3383 status = skge_read32(hw, B0_SP_ISRC); in skge_intr()
3388 status &= hw->intr_mask; in skge_intr()
3390 hw->intr_mask &= ~IS_EXT_REG; in skge_intr()
3391 tasklet_schedule(&hw->phy_task); in skge_intr()
3395 struct skge_port *skge = netdev_priv(hw->dev[0]); in skge_intr()
3396 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); in skge_intr()
3401 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); in skge_intr()
3404 ++hw->dev[0]->stats.rx_over_errors; in skge_intr()
3405 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); in skge_intr()
3410 skge_mac_intr(hw, 0); in skge_intr()
3412 if (hw->dev[1]) { in skge_intr()
3413 struct skge_port *skge = netdev_priv(hw->dev[1]); in skge_intr()
3416 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); in skge_intr()
3421 ++hw->dev[1]->stats.rx_over_errors; in skge_intr()
3422 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); in skge_intr()
3426 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); in skge_intr()
3429 skge_mac_intr(hw, 1); in skge_intr()
3433 skge_error_irq(hw); in skge_intr()
3435 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_intr()
3436 skge_read32(hw, B0_IMSK); in skge_intr()
3437 spin_unlock(&hw->hw_lock); in skge_intr()
3448 skge_intr(dev->irq, skge->hw); in skge_netpoll()
3456 struct skge_hw *hw = skge->hw; in skge_set_mac_address() local
3467 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3468 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3471 spin_lock_bh(&hw->phy_lock); in skge_set_mac_address()
3472 ctrl = gma_read16(hw, port, GM_GP_CTRL); in skge_set_mac_address()
3473 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); in skge_set_mac_address()
3475 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3476 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3478 if (is_genesis(hw)) in skge_set_mac_address()
3479 xm_outaddr(hw, port, XM_SA, dev->dev_addr); in skge_set_mac_address()
3481 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); in skge_set_mac_address()
3482 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); in skge_set_mac_address()
3485 gma_write16(hw, port, GM_GP_CTRL, ctrl); in skge_set_mac_address()
3486 spin_unlock_bh(&hw->phy_lock); in skge_set_mac_address()
3502 static const char *skge_board_name(const struct skge_hw *hw) in skge_board_name() argument
3508 if (skge_chips[i].id == hw->chip_id) in skge_board_name()
3511 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id); in skge_board_name()
3520 static int skge_reset(struct skge_hw *hw) in skge_reset() argument
3527 ctst = skge_read16(hw, B0_CTST); in skge_reset()
3530 skge_write8(hw, B0_CTST, CS_RST_SET); in skge_reset()
3531 skge_write8(hw, B0_CTST, CS_RST_CLR); in skge_reset()
3534 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3535 skge_write8(hw, B2_TST_CTRL2, 0); in skge_reset()
3537 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); in skge_reset()
3538 pci_write_config_word(hw->pdev, PCI_STATUS, in skge_reset()
3540 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_reset()
3541 skge_write8(hw, B0_CTST, CS_MRST_CLR); in skge_reset()
3544 skge_write16(hw, B0_CTST, in skge_reset()
3547 hw->chip_id = skge_read8(hw, B2_CHIP_ID); in skge_reset()
3548 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; in skge_reset()
3549 pmd_type = skge_read8(hw, B2_PMD_TYP); in skge_reset()
3550 hw->copper = (pmd_type == 'T' || pmd_type == '1'); in skge_reset()
3552 switch (hw->chip_id) { in skge_reset()
3555 switch (hw->phy_type) { in skge_reset()
3557 hw->phy_addr = PHY_ADDR_XMAC; in skge_reset()
3560 hw->phy_addr = PHY_ADDR_BCOM; in skge_reset()
3563 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", in skge_reset()
3564 hw->phy_type); in skge_reset()
3569 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n"); in skge_reset()
3576 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') in skge_reset()
3577 hw->copper = 1; in skge_reset()
3579 hw->phy_addr = PHY_ADDR_MARV; in skge_reset()
3583 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", in skge_reset()
3584 hw->chip_id); in skge_reset()
3588 mac_cfg = skge_read8(hw, B2_MAC_CFG); in skge_reset()
3589 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; in skge_reset()
3590 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; in skge_reset()
3593 t8 = skge_read8(hw, B2_E_0); in skge_reset()
3594 if (is_genesis(hw)) { in skge_reset()
3597 hw->ram_size = 0x100000; in skge_reset()
3598 hw->ram_offset = 0x80000; in skge_reset()
3600 hw->ram_size = t8 * 512; in skge_reset()
3602 hw->ram_size = 0x20000; in skge_reset()
3604 hw->ram_size = t8 * 4096; in skge_reset()
3606 hw->intr_mask = IS_HW_ERR; in skge_reset()
3609 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)) in skge_reset()
3610 hw->intr_mask |= IS_EXT_REG; in skge_reset()
3612 if (is_genesis(hw)) in skge_reset()
3613 genesis_init(hw); in skge_reset()
3616 skge_write8(hw, B0_POWER_CTRL, in skge_reset()
3620 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && in skge_reset()
3621 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { in skge_reset()
3622 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); in skge_reset()
3623 hw->intr_mask &= ~IS_HW_ERR; in skge_reset()
3627 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3628 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); in skge_reset()
3630 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); in skge_reset()
3631 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_reset()
3634 for (i = 0; i < hw->ports; i++) { in skge_reset()
3635 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); in skge_reset()
3636 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); in skge_reset()
3641 skge_write8(hw, B2_TI_CTRL, TIM_STOP); in skge_reset()
3642 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); in skge_reset()
3643 skge_write8(hw, B0_LED, LED_STAT_ON); in skge_reset()
3646 for (i = 0; i < hw->ports; i++) in skge_reset()
3647 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); in skge_reset()
3650 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); in skge_reset()
3652 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); in skge_reset()
3653 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); in skge_reset()
3654 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); in skge_reset()
3655 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); in skge_reset()
3656 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); in skge_reset()
3657 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); in skge_reset()
3658 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); in skge_reset()
3659 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); in skge_reset()
3660 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); in skge_reset()
3661 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); in skge_reset()
3662 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); in skge_reset()
3663 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); in skge_reset()
3665 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); in skge_reset()
3670 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); in skge_reset()
3671 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); in skge_reset()
3672 skge_write32(hw, B2_IRQM_CTRL, TIM_START); in skge_reset()
3675 skge_write32(hw, B0_IMSK, 0); in skge_reset()
3677 for (i = 0; i < hw->ports; i++) { in skge_reset()
3678 if (is_genesis(hw)) in skge_reset()
3679 genesis_reset(hw, i); in skge_reset()
3681 yukon_reset(hw, i); in skge_reset()
3696 const struct skge_hw *hw = skge->hw; in skge_debug_show() local
3702 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC), in skge_debug_show()
3703 skge_read32(hw, B0_IMSK)); in skge_debug_show()
3807 static struct net_device *skge_devinit(struct skge_hw *hw, int port, in skge_devinit() argument
3817 SET_NETDEV_DEV(dev, &hw->pdev->dev); in skge_devinit()
3821 dev->irq = hw->pdev->irq; in skge_devinit()
3833 skge->hw = hw; in skge_devinit()
3844 skge->advertising = skge_supported_modes(hw); in skge_devinit()
3846 if (device_can_wakeup(&hw->pdev->dev)) { in skge_devinit()
3847 skge->wol = wol_supported(hw) & WAKE_MAGIC; in skge_devinit()
3848 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); in skge_devinit()
3851 hw->dev[port] = dev; in skge_devinit()
3856 if (is_genesis(hw)) in skge_devinit()
3865 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); in skge_devinit()
3883 struct skge_hw *hw; in skge_probe() local
3926 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") in skge_probe()
3928 if (!hw) in skge_probe()
3931 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); in skge_probe()
3933 hw->pdev = pdev; in skge_probe()
3934 spin_lock_init(&hw->hw_lock); in skge_probe()
3935 spin_lock_init(&hw->phy_lock); in skge_probe()
3936 tasklet_setup(&hw->phy_task, skge_extirq); in skge_probe()
3938 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000); in skge_probe()
3939 if (!hw->regs) { in skge_probe()
3944 err = skge_reset(hw); in skge_probe()
3951 skge_board_name(hw), hw->chip_rev); in skge_probe()
3953 dev = skge_devinit(hw, 0, using_dac); in skge_probe()
3971 if (hw->ports > 1) { in skge_probe()
3972 dev1 = skge_devinit(hw, 1, using_dac); in skge_probe()
3985 hw->irq_name, hw); in skge_probe()
3994 pci_set_drvdata(pdev, hw); in skge_probe()
4007 skge_write16(hw, B0_LED, LED_STAT_OFF); in skge_probe()
4009 iounmap(hw->regs); in skge_probe()
4011 kfree(hw); in skge_probe()
4022 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_remove() local
4025 if (!hw) in skge_remove()
4028 dev1 = hw->dev[1]; in skge_remove()
4031 dev0 = hw->dev[0]; in skge_remove()
4034 tasklet_kill(&hw->phy_task); in skge_remove()
4036 spin_lock_irq(&hw->hw_lock); in skge_remove()
4037 hw->intr_mask = 0; in skge_remove()
4039 if (hw->ports > 1) { in skge_remove()
4040 skge_write32(hw, B0_IMSK, 0); in skge_remove()
4041 skge_read32(hw, B0_IMSK); in skge_remove()
4043 spin_unlock_irq(&hw->hw_lock); in skge_remove()
4045 skge_write16(hw, B0_LED, LED_STAT_OFF); in skge_remove()
4046 skge_write8(hw, B0_CTST, CS_RST_SET); in skge_remove()
4048 if (hw->ports > 1) in skge_remove()
4049 free_irq(pdev->irq, hw); in skge_remove()
4056 iounmap(hw->regs); in skge_remove()
4057 kfree(hw); in skge_remove()
4063 struct skge_hw *hw = dev_get_drvdata(dev); in skge_suspend() local
4066 if (!hw) in skge_suspend()
4069 for (i = 0; i < hw->ports; i++) { in skge_suspend()
4070 struct net_device *dev = hw->dev[i]; in skge_suspend()
4080 skge_write32(hw, B0_IMSK, 0); in skge_suspend()
4087 struct skge_hw *hw = dev_get_drvdata(dev); in skge_resume() local
4090 if (!hw) in skge_resume()
4093 err = skge_reset(hw); in skge_resume()
4097 for (i = 0; i < hw->ports; i++) { in skge_resume()
4098 struct net_device *dev = hw->dev[i]; in skge_resume()
4124 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_shutdown() local
4127 if (!hw) in skge_shutdown()
4130 for (i = 0; i < hw->ports; i++) { in skge_shutdown()
4131 struct net_device *dev = hw->dev[i]; in skge_shutdown()