Lines Matching defs:a
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3) argument
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) argument
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) argument
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) argument
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) argument
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) argument
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3) argument
24 #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3) argument
25 #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3) argument
26 #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) argument
27 #define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3) argument
28 #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3) argument
29 #define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3) argument
30 #define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3) argument
31 #define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3) argument
32 #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3) argument
33 #define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3) argument
36 #define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3) argument
41 #define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) argument
42 #define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) argument
43 #define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3) argument
47 #define RVU_MBOX_PF_VFX_PFVF_TRIGX(a) (0x2000 | (a) << 3) argument
48 #define RVU_MBOX_PF_VFPF_INTX(a) (0x1000 | (a) << 3) argument
49 #define RVU_MBOX_PF_VFPF_INT_W1SX(a) (0x1020 | (a) << 3) argument
50 #define RVU_MBOX_PF_VFPF_INT_ENA_W1SX(a) (0x1040 | (a) << 3) argument
51 #define RVU_MBOX_PF_VFPF_INT_ENA_W1CX(a) (0x1060 | (a) << 3) argument
53 #define RVU_MBOX_PF_VFPF1_INTX(a) (0x1080 | (a) << 3) argument
54 #define RVU_MBOX_PF_VFPF1_INT_W1SX(a) (0x10a0 | (a) << 3) argument
55 #define RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(a) (0x10c0 | (a) << 3) argument
56 #define RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(a) (0x10e0 | (a) << 3) argument
61 #define RVU_VF_VFPF_MBOXX(a) (0x00 | (a) << 3) argument
66 #define RVU_VF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) argument
67 #define RVU_VF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) argument
68 #define RVU_VF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) argument
69 #define RVU_VF_MSIX_PBAX(a) (0xF0000 | (a) << 3) argument
73 #define RVU_MBOX_AF_PFX_ADDR(a) (0x5000 | (a) << 4) argument
82 #define NPA_LF_AURA_OP_ALLOCX(a) (NPA_LFBASE | 0x10 | (a) << 3) argument
105 #define NPA_LF_QINTX_CNT(a) (NPA_LFBASE | 0x300 | (a) << 12) argument
106 #define NPA_LF_QINTX_INT(a) (NPA_LFBASE | 0x310 | (a) << 12) argument
107 #define NPA_LF_QINTX_INT_W1S(a) (NPA_LFBASE | 0x318 | (a) << 12) argument
108 #define NPA_LF_QINTX_ENA_W1S(a) (NPA_LFBASE | 0x320 | (a) << 12) argument
109 #define NPA_LF_QINTX_ENA_W1C(a) (NPA_LFBASE | 0x330 | (a) << 12) argument
114 #define NIX_LF_RX_SECRETX(a) (NIX_LFBASE | 0x0 | (a) << 3) argument
131 #define NIX_LF_TX_STATX(a) (NIX_LFBASE | 0x300 | (a) << 3) argument
132 #define NIX_LF_RX_STATX(a) (NIX_LFBASE | 0x400 | (a) << 3) argument
133 #define NIX_LF_OP_SENDX(a) (NIX_LFBASE | 0x800 | (a) << 3) argument
145 #define NIX_LF_QINTX_CNT(a) (NIX_LFBASE | 0xC00 | (a) << 12) argument
146 #define NIX_LF_QINTX_INT(a) (NIX_LFBASE | 0xC10 | (a) << 12) argument
147 #define NIX_LF_QINTX_INT_W1S(a) (NIX_LFBASE | 0xC18 | (a) << 12) argument
148 #define NIX_LF_QINTX_ENA_W1S(a) (NIX_LFBASE | 0xC20 | (a) << 12) argument
149 #define NIX_LF_QINTX_ENA_W1C(a) (NIX_LFBASE | 0xC30 | (a) << 12) argument
150 #define NIX_LF_CINTX_CNT(a) (NIX_LFBASE | 0xD00 | (a) << 12) argument
151 #define NIX_LF_CINTX_WAIT(a) (NIX_LFBASE | 0xD10 | (a) << 12) argument
152 #define NIX_LF_CINTX_INT(a) (NIX_LFBASE | 0xD20 | (a) << 12) argument
153 #define NIX_LF_CINTX_INT_W1S(a) (NIX_LFBASE | 0xD30 | (a) << 12) argument
154 #define NIX_LF_CINTX_ENA_W1S(a) (NIX_LFBASE | 0xD40 | (a) << 12) argument
155 #define NIX_LF_CINTX_ENA_W1C(a) (NIX_LFBASE | 0xD50 | (a) << 12) argument
159 #define LMT_LF_LMTLINEX(a) (LMT_LFBASE | 0x000 | (a) << 12) argument