Lines Matching +full:num +full:- +full:vectors
1 // SPDX-License-Identifier: GPL-2.0
34 int type, int num,
63 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_capabilities()
65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; in rvu_setup_hw_capabilities()
66 hw->cap.nix_fixed_txschq_mapping = false; in rvu_setup_hw_capabilities()
67 hw->cap.nix_shaping = true; in rvu_setup_hw_capabilities()
68 hw->cap.nix_tx_link_bp = true; in rvu_setup_hw_capabilities()
69 hw->cap.nix_rx_multicast = true; in rvu_setup_hw_capabilities()
70 hw->cap.nix_shaper_toggle_wait = false; in rvu_setup_hw_capabilities()
71 hw->cap.npc_hash_extract = false; in rvu_setup_hw_capabilities()
72 hw->cap.npc_exact_match_enabled = false; in rvu_setup_hw_capabilities()
73 hw->rvu = rvu; in rvu_setup_hw_capabilities()
76 hw->cap.nix_fixed_txschq_mapping = true; in rvu_setup_hw_capabilities()
77 hw->cap.nix_txsch_per_cgx_lmac = 4; in rvu_setup_hw_capabilities()
78 hw->cap.nix_txsch_per_lbk_lmac = 132; in rvu_setup_hw_capabilities()
79 hw->cap.nix_txsch_per_sdp_lmac = 76; in rvu_setup_hw_capabilities()
80 hw->cap.nix_shaping = false; in rvu_setup_hw_capabilities()
81 hw->cap.nix_tx_link_bp = false; in rvu_setup_hw_capabilities()
83 hw->cap.nix_rx_multicast = false; in rvu_setup_hw_capabilities()
86 hw->cap.nix_shaper_toggle_wait = true; in rvu_setup_hw_capabilities()
89 hw->cap.per_pf_mbox_regs = true; in rvu_setup_hw_capabilities()
92 hw->cap.npc_hash_extract = true; in rvu_setup_hw_capabilities()
105 reg = rvu->afreg_base + ((block << 28) | offset); in rvu_poll_reg()
125 return -EBUSY; in rvu_poll_reg()
132 if (!rsrc->bmap) in rvu_alloc_rsrc()
133 return -EINVAL; in rvu_alloc_rsrc()
135 id = find_first_zero_bit(rsrc->bmap, rsrc->max); in rvu_alloc_rsrc()
136 if (id >= rsrc->max) in rvu_alloc_rsrc()
137 return -ENOSPC; in rvu_alloc_rsrc()
139 __set_bit(id, rsrc->bmap); in rvu_alloc_rsrc()
148 if (!rsrc->bmap) in rvu_alloc_rsrc_contig()
149 return -EINVAL; in rvu_alloc_rsrc_contig()
151 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); in rvu_alloc_rsrc_contig()
152 if (start >= rsrc->max) in rvu_alloc_rsrc_contig()
153 return -ENOSPC; in rvu_alloc_rsrc_contig()
155 bitmap_set(rsrc->bmap, start, nrsrc); in rvu_alloc_rsrc_contig()
161 if (!rsrc->bmap) in rvu_free_rsrc_contig()
163 if (start >= rsrc->max) in rvu_free_rsrc_contig()
166 bitmap_clear(rsrc->bmap, start, nrsrc); in rvu_free_rsrc_contig()
173 if (!rsrc->bmap) in rvu_rsrc_check_contig()
176 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); in rvu_rsrc_check_contig()
177 if (start >= rsrc->max) in rvu_rsrc_check_contig()
185 if (!rsrc->bmap) in rvu_free_rsrc()
188 __clear_bit(id, rsrc->bmap); in rvu_free_rsrc()
195 if (!rsrc->bmap) in rvu_rsrc_free_count()
198 used = bitmap_weight(rsrc->bmap, rsrc->max); in rvu_rsrc_free_count()
199 return (rsrc->max - used); in rvu_rsrc_free_count()
204 if (!rsrc->bmap) in is_rsrc_free()
207 return !test_bit(id, rsrc->bmap); in is_rsrc_free()
212 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), in rvu_alloc_bitmap()
214 if (!rsrc->bmap) in rvu_alloc_bitmap()
215 return -ENOMEM; in rvu_alloc_bitmap()
221 kfree(rsrc->bmap); in rvu_free_bitmap()
230 mutex_lock(&rvu->rsrc_lock); in rvu_get_lf()
231 for (lf = 0; lf < block->lf.max; lf++) { in rvu_get_lf()
232 if (block->fn_map[lf] == pcifunc) { in rvu_get_lf()
234 mutex_unlock(&rvu->rsrc_lock); in rvu_get_lf()
240 mutex_unlock(&rvu->rsrc_lock); in rvu_get_lf()
241 return -ENODEV; in rvu_get_lf()
255 int devnum, blkaddr = -ENODEV; in rvu_get_blkaddr()
336 if (is_block_implemented(rvu->hw, blkaddr)) in rvu_get_blkaddr()
338 return -ENODEV; in rvu_get_blkaddr()
349 if (lf >= block->lf.max) { in rvu_update_rsrc_map()
350 dev_err(&rvu->pdev->dev, in rvu_update_rsrc_map()
352 __func__, lf, block->name, block->lf.max); in rvu_update_rsrc_map()
365 block->fn_map[lf] = attach ? pcifunc : 0; in rvu_update_rsrc_map()
367 switch (block->addr) { in rvu_update_rsrc_map()
369 pfvf->npalf = attach ? true : false; in rvu_update_rsrc_map()
370 num_lfs = pfvf->npalf; in rvu_update_rsrc_map()
374 pfvf->nixlf = attach ? true : false; in rvu_update_rsrc_map()
375 num_lfs = pfvf->nixlf; in rvu_update_rsrc_map()
378 attach ? pfvf->sso++ : pfvf->sso--; in rvu_update_rsrc_map()
379 num_lfs = pfvf->sso; in rvu_update_rsrc_map()
382 attach ? pfvf->ssow++ : pfvf->ssow--; in rvu_update_rsrc_map()
383 num_lfs = pfvf->ssow; in rvu_update_rsrc_map()
386 attach ? pfvf->timlfs++ : pfvf->timlfs--; in rvu_update_rsrc_map()
387 num_lfs = pfvf->timlfs; in rvu_update_rsrc_map()
390 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; in rvu_update_rsrc_map()
391 num_lfs = pfvf->cptlfs; in rvu_update_rsrc_map()
394 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; in rvu_update_rsrc_map()
395 num_lfs = pfvf->cpt1_lfs; in rvu_update_rsrc_map()
399 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; in rvu_update_rsrc_map()
431 return ((cfg & 0xFFF) + func - 1); in rvu_get_hwvf()
438 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; in rvu_get_pfvf()
440 return &rvu->pf[rvu_get_pf(pcifunc)]; in rvu_get_pfvf()
449 if (pf >= rvu->hw->total_pfs) in is_pf_func_valid()
456 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; in is_pf_func_valid()
472 block = &hw->block[blkaddr]; in is_block_implemented()
473 return block->implemented; in is_block_implemented()
478 struct rvu_hwinfo *hw = rvu->hw; in rvu_check_block_implemented()
485 block = &hw->block[blkid]; in rvu_check_block_implemented()
488 block->implemented = true; in rvu_check_block_implemented()
509 if (!block->implemented) in rvu_lf_reset()
512 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); in rvu_lf_reset()
513 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), in rvu_lf_reset()
520 struct rvu_block *block = &rvu->hw->block[blkaddr]; in rvu_block_reset()
523 if (!block->implemented) in rvu_block_reset()
529 dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr); in rvu_block_reset()
530 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY) in rvu_block_reset()
559 for (lf = 0; lf < block->lf.max; lf++) { in rvu_scan_block()
560 cfg = rvu_read64(rvu, block->addr, in rvu_scan_block()
561 block->lfcfg_reg | (lf << block->lfshift)); in rvu_scan_block()
566 __set_bit(lf, block->lf.bmap); in rvu_scan_block()
586 dev_warn(rvu->dev, in rvu_check_min_msix_vec()
587 "PF%d:VF%d is configured with zero msix vectors, %d\n", in rvu_check_min_msix_vec()
588 pf, vf - 1, nvecs); in rvu_check_min_msix_vec()
600 dev_warn(rvu->dev, in rvu_check_min_msix_vec()
601 "PF%d is configured with too few vectors, %d, min is %d\n", in rvu_check_min_msix_vec()
607 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_msix_resources()
614 for (pf = 0; pf < hw->total_pfs; pf++) { in rvu_setup_msix_resources()
622 pfvf = &rvu->pf[pf]; in rvu_setup_msix_resources()
623 /* Get num of MSIX vectors attached to this PF */ in rvu_setup_msix_resources()
625 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; in rvu_setup_msix_resources()
626 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); in rvu_setup_msix_resources()
629 err = rvu_alloc_bitmap(&pfvf->msix); in rvu_setup_msix_resources()
634 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, in rvu_setup_msix_resources()
636 if (!pfvf->msix_lfmap) in rvu_setup_msix_resources()
637 return -ENOMEM; in rvu_setup_msix_resources()
640 * AF, block AF and PF0_INT vectors, so jump to VFs. in rvu_setup_msix_resources()
645 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. in rvu_setup_msix_resources()
652 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); in rvu_setup_msix_resources()
658 pfvf = &rvu->hwvf[hwvf + vf]; in rvu_setup_msix_resources()
659 /* Get num of MSIX vectors attached to this VF */ in rvu_setup_msix_resources()
662 pfvf->msix.max = (cfg & 0xFFF) + 1; in rvu_setup_msix_resources()
663 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); in rvu_setup_msix_resources()
666 err = rvu_alloc_bitmap(&pfvf->msix); in rvu_setup_msix_resources()
670 pfvf->msix_lfmap = in rvu_setup_msix_resources()
671 devm_kcalloc(rvu->dev, pfvf->msix.max, in rvu_setup_msix_resources()
673 if (!pfvf->msix_lfmap) in rvu_setup_msix_resources()
674 return -ENOMEM; in rvu_setup_msix_resources()
676 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. in rvu_setup_msix_resources()
684 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); in rvu_setup_msix_resources()
697 if (rvu->fwdata && rvu->fwdata->msixtr_base) in rvu_setup_msix_resources()
698 phy_addr = rvu->fwdata->msixtr_base; in rvu_setup_msix_resources()
702 iova = dma_map_resource(rvu->dev, phy_addr, in rvu_setup_msix_resources()
706 if (dma_mapping_error(rvu->dev, iova)) in rvu_setup_msix_resources()
707 return -ENOMEM; in rvu_setup_msix_resources()
710 rvu->msix_base_iova = iova; in rvu_setup_msix_resources()
711 rvu->msixtr_base_phy = phy_addr; in rvu_setup_msix_resources()
720 rvu->msixtr_base_phy); in rvu_reset_msix()
725 struct rvu_hwinfo *hw = rvu->hw; in rvu_free_hw_resources()
737 block = &hw->block[id]; in rvu_free_hw_resources()
738 kfree(block->lf.bmap); in rvu_free_hw_resources()
742 for (id = 0; id < hw->total_pfs; id++) { in rvu_free_hw_resources()
743 pfvf = &rvu->pf[id]; in rvu_free_hw_resources()
744 kfree(pfvf->msix.bmap); in rvu_free_hw_resources()
747 for (id = 0; id < hw->total_vfs; id++) { in rvu_free_hw_resources()
748 pfvf = &rvu->hwvf[id]; in rvu_free_hw_resources()
749 kfree(pfvf->msix.bmap); in rvu_free_hw_resources()
753 if (!rvu->msix_base_iova) in rvu_free_hw_resources()
757 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, in rvu_free_hw_resources()
762 mutex_destroy(&rvu->rsrc_lock); in rvu_free_hw_resources()
767 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_pfvf_macaddress()
772 for (pf = 0; pf < hw->total_pfs; pf++) { in rvu_setup_pfvf_macaddress()
780 pfvf = &rvu->pf[pf]; in rvu_setup_pfvf_macaddress()
781 if (rvu->fwdata && pf < PF_MACNUM_MAX) { in rvu_setup_pfvf_macaddress()
782 mac = &rvu->fwdata->pf_macs[pf]; in rvu_setup_pfvf_macaddress()
784 u64_to_ether_addr(*mac, pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
786 eth_random_addr(pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
788 eth_random_addr(pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
790 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
796 pfvf = &rvu->hwvf[hwvf]; in rvu_setup_pfvf_macaddress()
797 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { in rvu_setup_pfvf_macaddress()
798 mac = &rvu->fwdata->vf_macs[hwvf]; in rvu_setup_pfvf_macaddress()
800 u64_to_ether_addr(*mac, pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
802 eth_random_addr(pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
804 eth_random_addr(pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
806 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
822 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); in rvu_fwdata_init()
823 if (!rvu->fwdata) in rvu_fwdata_init()
826 dev_err(rvu->dev, in rvu_fwdata_init()
828 iounmap(rvu->fwdata); in rvu_fwdata_init()
829 rvu->fwdata = NULL; in rvu_fwdata_init()
830 return -EINVAL; in rvu_fwdata_init()
834 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); in rvu_fwdata_init()
835 return -EIO; in rvu_fwdata_init()
840 if (rvu->fwdata) in rvu_fwdata_exit()
841 iounmap(rvu->fwdata); in rvu_fwdata_exit()
846 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_nix_hw_resource()
852 block = &hw->block[blkaddr]; in rvu_setup_nix_hw_resource()
853 if (!block->implemented) in rvu_setup_nix_hw_resource()
857 block->lf.max = cfg & 0xFFF; in rvu_setup_nix_hw_resource()
858 block->addr = blkaddr; in rvu_setup_nix_hw_resource()
859 block->type = BLKTYPE_NIX; in rvu_setup_nix_hw_resource()
860 block->lfshift = 8; in rvu_setup_nix_hw_resource()
861 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; in rvu_setup_nix_hw_resource()
862 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); in rvu_setup_nix_hw_resource()
863 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); in rvu_setup_nix_hw_resource()
864 block->lfcfg_reg = NIX_PRIV_LFX_CFG; in rvu_setup_nix_hw_resource()
865 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; in rvu_setup_nix_hw_resource()
866 block->lfreset_reg = NIX_AF_LF_RST; in rvu_setup_nix_hw_resource()
867 block->rvu = rvu; in rvu_setup_nix_hw_resource()
868 sprintf(block->name, "NIX%d", blkid); in rvu_setup_nix_hw_resource()
869 rvu->nix_blkaddr[blkid] = blkaddr; in rvu_setup_nix_hw_resource()
870 return rvu_alloc_bitmap(&block->lf); in rvu_setup_nix_hw_resource()
875 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_cpt_hw_resource()
881 block = &hw->block[blkaddr]; in rvu_setup_cpt_hw_resource()
882 if (!block->implemented) in rvu_setup_cpt_hw_resource()
886 block->lf.max = cfg & 0xFF; in rvu_setup_cpt_hw_resource()
887 block->addr = blkaddr; in rvu_setup_cpt_hw_resource()
888 block->type = BLKTYPE_CPT; in rvu_setup_cpt_hw_resource()
889 block->multislot = true; in rvu_setup_cpt_hw_resource()
890 block->lfshift = 3; in rvu_setup_cpt_hw_resource()
891 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; in rvu_setup_cpt_hw_resource()
892 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); in rvu_setup_cpt_hw_resource()
893 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); in rvu_setup_cpt_hw_resource()
894 block->lfcfg_reg = CPT_PRIV_LFX_CFG; in rvu_setup_cpt_hw_resource()
895 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; in rvu_setup_cpt_hw_resource()
896 block->lfreset_reg = CPT_AF_LF_RST; in rvu_setup_cpt_hw_resource()
897 block->rvu = rvu; in rvu_setup_cpt_hw_resource()
898 sprintf(block->name, "CPT%d", blkid); in rvu_setup_cpt_hw_resource()
899 return rvu_alloc_bitmap(&block->lf); in rvu_setup_cpt_hw_resource()
920 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); in rvu_get_lbk_bufsize()
929 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_resources()
936 hw->total_pfs = (cfg >> 32) & 0xFF; in rvu_setup_hw_resources()
937 hw->total_vfs = (cfg >> 20) & 0xFFF; in rvu_setup_hw_resources()
938 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; in rvu_setup_hw_resources()
944 block = &hw->block[BLKADDR_NPA]; in rvu_setup_hw_resources()
945 if (!block->implemented) in rvu_setup_hw_resources()
948 block->lf.max = (cfg >> 16) & 0xFFF; in rvu_setup_hw_resources()
949 block->addr = BLKADDR_NPA; in rvu_setup_hw_resources()
950 block->type = BLKTYPE_NPA; in rvu_setup_hw_resources()
951 block->lfshift = 8; in rvu_setup_hw_resources()
952 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; in rvu_setup_hw_resources()
953 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; in rvu_setup_hw_resources()
954 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; in rvu_setup_hw_resources()
955 block->lfcfg_reg = NPA_PRIV_LFX_CFG; in rvu_setup_hw_resources()
956 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; in rvu_setup_hw_resources()
957 block->lfreset_reg = NPA_AF_LF_RST; in rvu_setup_hw_resources()
958 block->rvu = rvu; in rvu_setup_hw_resources()
959 sprintf(block->name, "NPA"); in rvu_setup_hw_resources()
960 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
962 dev_err(rvu->dev, in rvu_setup_hw_resources()
970 dev_err(rvu->dev, in rvu_setup_hw_resources()
977 dev_err(rvu->dev, in rvu_setup_hw_resources()
983 block = &hw->block[BLKADDR_SSO]; in rvu_setup_hw_resources()
984 if (!block->implemented) in rvu_setup_hw_resources()
987 block->lf.max = cfg & 0xFFFF; in rvu_setup_hw_resources()
988 block->addr = BLKADDR_SSO; in rvu_setup_hw_resources()
989 block->type = BLKTYPE_SSO; in rvu_setup_hw_resources()
990 block->multislot = true; in rvu_setup_hw_resources()
991 block->lfshift = 3; in rvu_setup_hw_resources()
992 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; in rvu_setup_hw_resources()
993 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; in rvu_setup_hw_resources()
994 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; in rvu_setup_hw_resources()
995 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; in rvu_setup_hw_resources()
996 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; in rvu_setup_hw_resources()
997 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; in rvu_setup_hw_resources()
998 block->rvu = rvu; in rvu_setup_hw_resources()
999 sprintf(block->name, "SSO GROUP"); in rvu_setup_hw_resources()
1000 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
1002 dev_err(rvu->dev, in rvu_setup_hw_resources()
1009 block = &hw->block[BLKADDR_SSOW]; in rvu_setup_hw_resources()
1010 if (!block->implemented) in rvu_setup_hw_resources()
1012 block->lf.max = (cfg >> 56) & 0xFF; in rvu_setup_hw_resources()
1013 block->addr = BLKADDR_SSOW; in rvu_setup_hw_resources()
1014 block->type = BLKTYPE_SSOW; in rvu_setup_hw_resources()
1015 block->multislot = true; in rvu_setup_hw_resources()
1016 block->lfshift = 3; in rvu_setup_hw_resources()
1017 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; in rvu_setup_hw_resources()
1018 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; in rvu_setup_hw_resources()
1019 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; in rvu_setup_hw_resources()
1020 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; in rvu_setup_hw_resources()
1021 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; in rvu_setup_hw_resources()
1022 block->lfreset_reg = SSOW_AF_LF_HWS_RST; in rvu_setup_hw_resources()
1023 block->rvu = rvu; in rvu_setup_hw_resources()
1024 sprintf(block->name, "SSOWS"); in rvu_setup_hw_resources()
1025 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
1027 dev_err(rvu->dev, in rvu_setup_hw_resources()
1034 block = &hw->block[BLKADDR_TIM]; in rvu_setup_hw_resources()
1035 if (!block->implemented) in rvu_setup_hw_resources()
1038 block->lf.max = cfg & 0xFFFF; in rvu_setup_hw_resources()
1039 block->addr = BLKADDR_TIM; in rvu_setup_hw_resources()
1040 block->type = BLKTYPE_TIM; in rvu_setup_hw_resources()
1041 block->multislot = true; in rvu_setup_hw_resources()
1042 block->lfshift = 3; in rvu_setup_hw_resources()
1043 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; in rvu_setup_hw_resources()
1044 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; in rvu_setup_hw_resources()
1045 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; in rvu_setup_hw_resources()
1046 block->lfcfg_reg = TIM_PRIV_LFX_CFG; in rvu_setup_hw_resources()
1047 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; in rvu_setup_hw_resources()
1048 block->lfreset_reg = TIM_AF_LF_RST; in rvu_setup_hw_resources()
1049 block->rvu = rvu; in rvu_setup_hw_resources()
1050 sprintf(block->name, "TIM"); in rvu_setup_hw_resources()
1051 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
1053 dev_err(rvu->dev, in rvu_setup_hw_resources()
1061 dev_err(rvu->dev, in rvu_setup_hw_resources()
1067 dev_err(rvu->dev, in rvu_setup_hw_resources()
1073 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, in rvu_setup_hw_resources()
1075 if (!rvu->pf) { in rvu_setup_hw_resources()
1076 dev_err(rvu->dev, in rvu_setup_hw_resources()
1078 return -ENOMEM; in rvu_setup_hw_resources()
1081 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, in rvu_setup_hw_resources()
1083 if (!rvu->hwvf) { in rvu_setup_hw_resources()
1084 dev_err(rvu->dev, in rvu_setup_hw_resources()
1086 return -ENOMEM; in rvu_setup_hw_resources()
1089 mutex_init(&rvu->rsrc_lock); in rvu_setup_hw_resources()
1095 dev_err(rvu->dev, in rvu_setup_hw_resources()
1101 block = &hw->block[blkid]; in rvu_setup_hw_resources()
1102 if (!block->lf.bmap) in rvu_setup_hw_resources()
1106 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, in rvu_setup_hw_resources()
1108 if (!block->fn_map) { in rvu_setup_hw_resources()
1109 err = -ENOMEM; in rvu_setup_hw_resources()
1125 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); in rvu_setup_hw_resources()
1131 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); in rvu_setup_hw_resources()
1137 dev_err(rvu->dev, "failed to initialize exact match table\n"); in rvu_setup_hw_resources()
1146 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); in rvu_setup_hw_resources()
1154 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); in rvu_setup_hw_resources()
1160 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__); in rvu_setup_hw_resources()
1169 dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__); in rvu_setup_hw_resources()
1175 dev_err(rvu->dev, "%s: Failed to initialize cpt\n", __func__); in rvu_setup_hw_resources()
1203 qmem_free(rvu->dev, aq->inst); in rvu_aq_free()
1204 qmem_free(rvu->dev, aq->res); in rvu_aq_free()
1205 devm_kfree(rvu->dev, aq); in rvu_aq_free()
1214 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); in rvu_aq_alloc()
1216 return -ENOMEM; in rvu_aq_alloc()
1220 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); in rvu_aq_alloc()
1222 devm_kfree(rvu->dev, aq); in rvu_aq_alloc()
1227 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); in rvu_aq_alloc()
1233 spin_lock_init(&aq->lock); in rvu_aq_alloc()
1240 if (rvu->fwdata) { in rvu_mbox_handler_ready()
1241 rsp->rclk_freq = rvu->fwdata->rclk; in rvu_mbox_handler_ready()
1242 rsp->sclk_freq = rvu->fwdata->sclk; in rvu_mbox_handler_ready()
1254 return pfvf->npalf ? 1 : 0; in rvu_get_rsrc_mapcount()
1257 return pfvf->nixlf ? 1 : 0; in rvu_get_rsrc_mapcount()
1259 return pfvf->sso; in rvu_get_rsrc_mapcount()
1261 return pfvf->ssow; in rvu_get_rsrc_mapcount()
1263 return pfvf->timlfs; in rvu_get_rsrc_mapcount()
1265 return pfvf->cptlfs; in rvu_get_rsrc_mapcount()
1267 return pfvf->cpt1_lfs; in rvu_get_rsrc_mapcount()
1277 return pfvf->npalf ? 1 : 0; in is_blktype_attached()
1279 return pfvf->nixlf ? 1 : 0; in is_blktype_attached()
1281 return !!pfvf->sso; in is_blktype_attached()
1283 return !!pfvf->ssow; in is_blktype_attached()
1285 return !!pfvf->timlfs; in is_blktype_attached()
1287 return pfvf->cptlfs || pfvf->cpt1_lfs; in is_blktype_attached()
1315 rvu_write64(rvu, block->addr, block->lookup_reg, val); in rvu_lookup_rsrc()
1318 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) in rvu_lookup_rsrc()
1321 val = rvu_read64(rvu, block->addr, block->lookup_reg); in rvu_lookup_rsrc()
1325 return -1; in rvu_lookup_rsrc()
1341 return -ENODEV; in rvu_get_blkaddr_from_slot()
1347 block = &rvu->hw->block[blkaddr]; in rvu_get_blkaddr_from_slot()
1348 if (block->type != blktype) in rvu_get_blkaddr_from_slot()
1350 if (!is_block_implemented(rvu->hw, blkaddr)) in rvu_get_blkaddr_from_slot()
1362 return -ENODEV; in rvu_get_blkaddr_from_slot()
1369 blkaddr = -ENODEV; in rvu_get_blkaddr_from_slot()
1375 start_slot = total_lfs - numlfs; in rvu_get_blkaddr_from_slot()
1376 *slot_in_block = global_slot - start_slot; in rvu_get_blkaddr_from_slot()
1387 struct rvu_hwinfo *hw = rvu->hw; in rvu_detach_block()
1399 block = &hw->block[blkaddr]; in rvu_detach_block()
1401 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); in rvu_detach_block()
1411 rvu_write64(rvu, blkaddr, block->lfcfg_reg | in rvu_detach_block()
1412 (lf << block->lfshift), 0x00ULL); in rvu_detach_block()
1419 rvu_free_rsrc(&block->lf, lf); in rvu_detach_block()
1429 struct rvu_hwinfo *hw = rvu->hw; in rvu_detach_rsrcs()
1434 mutex_lock(&rvu->rsrc_lock); in rvu_detach_rsrcs()
1437 if (detach && detach->partial) in rvu_detach_rsrcs()
1444 block = &hw->block[blkid]; in rvu_detach_rsrcs()
1445 if (!block->lf.bmap) in rvu_detach_rsrcs()
1448 if (blkid == BLKADDR_NPA && !detach->npalf) in rvu_detach_rsrcs()
1450 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) in rvu_detach_rsrcs()
1452 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) in rvu_detach_rsrcs()
1454 else if ((blkid == BLKADDR_SSO) && !detach->sso) in rvu_detach_rsrcs()
1456 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) in rvu_detach_rsrcs()
1458 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) in rvu_detach_rsrcs()
1460 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) in rvu_detach_rsrcs()
1462 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) in rvu_detach_rsrcs()
1465 rvu_detach_block(rvu, pcifunc, block->type); in rvu_detach_rsrcs()
1468 mutex_unlock(&rvu->rsrc_lock); in rvu_detach_rsrcs()
1476 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); in rvu_mbox_handler_detach_resources()
1489 blkaddr = pf->nix_blkaddr; in rvu_get_nix_blkaddr()
1491 vf = pcifunc - 1; in rvu_get_nix_blkaddr()
1497 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) in rvu_get_nix_blkaddr()
1502 if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1) in rvu_get_nix_blkaddr()
1507 pfvf->nix_blkaddr = BLKADDR_NIX1; in rvu_get_nix_blkaddr()
1508 pfvf->nix_rx_intf = NIX_INTFX_RX(1); in rvu_get_nix_blkaddr()
1509 pfvf->nix_tx_intf = NIX_INTFX_TX(1); in rvu_get_nix_blkaddr()
1513 pfvf->nix_blkaddr = BLKADDR_NIX0; in rvu_get_nix_blkaddr()
1514 pfvf->nix_rx_intf = NIX_INTFX_RX(0); in rvu_get_nix_blkaddr()
1515 pfvf->nix_tx_intf = NIX_INTFX_TX(0); in rvu_get_nix_blkaddr()
1519 return pfvf->nix_blkaddr; in rvu_get_nix_blkaddr()
1532 if (attach->hdr.ver < RVU_MULTI_BLK_VER) in rvu_get_attach_blkaddr()
1534 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : in rvu_get_attach_blkaddr()
1537 return -ENODEV; in rvu_get_attach_blkaddr()
1543 if (is_block_implemented(rvu->hw, blkaddr)) in rvu_get_attach_blkaddr()
1546 return -ENODEV; in rvu_get_attach_blkaddr()
1553 struct rvu_hwinfo *hw = rvu->hw; in rvu_attach_block()
1566 block = &hw->block[blkaddr]; in rvu_attach_block()
1567 if (!block->lf.bmap) in rvu_attach_block()
1572 lf = rvu_alloc_rsrc(&block->lf); in rvu_attach_block()
1577 rvu_write64(rvu, blkaddr, block->lfcfg_reg | in rvu_attach_block()
1578 (lf << block->lfshift), cfg); in rvu_attach_block()
1592 struct rvu_hwinfo *hw = rvu->hw; in rvu_check_rsrc_availability()
1596 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { in rvu_check_rsrc_availability()
1597 block = &hw->block[BLKADDR_NPA]; in rvu_check_rsrc_availability()
1598 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1601 } else if (req->npalf) { in rvu_check_rsrc_availability()
1602 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1605 return -EINVAL; in rvu_check_rsrc_availability()
1609 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { in rvu_check_rsrc_availability()
1614 block = &hw->block[blkaddr]; in rvu_check_rsrc_availability()
1615 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1618 } else if (req->nixlf) { in rvu_check_rsrc_availability()
1619 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1622 return -EINVAL; in rvu_check_rsrc_availability()
1625 if (req->sso) { in rvu_check_rsrc_availability()
1626 block = &hw->block[BLKADDR_SSO]; in rvu_check_rsrc_availability()
1628 if (req->sso > block->lf.max) { in rvu_check_rsrc_availability()
1629 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1631 pcifunc, req->sso, block->lf.max); in rvu_check_rsrc_availability()
1632 return -EINVAL; in rvu_check_rsrc_availability()
1634 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); in rvu_check_rsrc_availability()
1635 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1637 if (req->sso > mappedlfs && in rvu_check_rsrc_availability()
1638 ((req->sso - mappedlfs) > free_lfs)) in rvu_check_rsrc_availability()
1642 if (req->ssow) { in rvu_check_rsrc_availability()
1643 block = &hw->block[BLKADDR_SSOW]; in rvu_check_rsrc_availability()
1644 if (req->ssow > block->lf.max) { in rvu_check_rsrc_availability()
1645 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1647 pcifunc, req->ssow, block->lf.max); in rvu_check_rsrc_availability()
1648 return -EINVAL; in rvu_check_rsrc_availability()
1650 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); in rvu_check_rsrc_availability()
1651 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1652 if (req->ssow > mappedlfs && in rvu_check_rsrc_availability()
1653 ((req->ssow - mappedlfs) > free_lfs)) in rvu_check_rsrc_availability()
1657 if (req->timlfs) { in rvu_check_rsrc_availability()
1658 block = &hw->block[BLKADDR_TIM]; in rvu_check_rsrc_availability()
1659 if (req->timlfs > block->lf.max) { in rvu_check_rsrc_availability()
1660 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1662 pcifunc, req->timlfs, block->lf.max); in rvu_check_rsrc_availability()
1663 return -EINVAL; in rvu_check_rsrc_availability()
1665 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); in rvu_check_rsrc_availability()
1666 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1667 if (req->timlfs > mappedlfs && in rvu_check_rsrc_availability()
1668 ((req->timlfs - mappedlfs) > free_lfs)) in rvu_check_rsrc_availability()
1672 if (req->cptlfs) { in rvu_check_rsrc_availability()
1677 block = &hw->block[blkaddr]; in rvu_check_rsrc_availability()
1678 if (req->cptlfs > block->lf.max) { in rvu_check_rsrc_availability()
1679 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1681 pcifunc, req->cptlfs, block->lf.max); in rvu_check_rsrc_availability()
1682 return -EINVAL; in rvu_check_rsrc_availability()
1684 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); in rvu_check_rsrc_availability()
1685 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1686 if (req->cptlfs > mappedlfs && in rvu_check_rsrc_availability()
1687 ((req->cptlfs - mappedlfs) > free_lfs)) in rvu_check_rsrc_availability()
1694 dev_info(rvu->dev, "Request for %s failed\n", block->name); in rvu_check_rsrc_availability()
1695 return -ENOSPC; in rvu_check_rsrc_availability()
1704 attach->hdr.pcifunc, attach); in rvu_attach_from_same_block()
1708 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), in rvu_attach_from_same_block()
1718 u16 pcifunc = attach->hdr.pcifunc; in rvu_mbox_handler_attach_resources()
1722 if (!attach->modify) in rvu_mbox_handler_attach_resources()
1725 mutex_lock(&rvu->rsrc_lock); in rvu_mbox_handler_attach_resources()
1733 if (attach->npalf) in rvu_mbox_handler_attach_resources()
1736 if (attach->nixlf) in rvu_mbox_handler_attach_resources()
1739 if (attach->sso) { in rvu_mbox_handler_attach_resources()
1745 if (attach->modify) in rvu_mbox_handler_attach_resources()
1748 attach->sso, attach); in rvu_mbox_handler_attach_resources()
1751 if (attach->ssow) { in rvu_mbox_handler_attach_resources()
1752 if (attach->modify) in rvu_mbox_handler_attach_resources()
1755 attach->ssow, attach); in rvu_mbox_handler_attach_resources()
1758 if (attach->timlfs) { in rvu_mbox_handler_attach_resources()
1759 if (attach->modify) in rvu_mbox_handler_attach_resources()
1762 attach->timlfs, attach); in rvu_mbox_handler_attach_resources()
1765 if (attach->cptlfs) { in rvu_mbox_handler_attach_resources()
1766 if (attach->modify && in rvu_mbox_handler_attach_resources()
1770 attach->cptlfs, attach); in rvu_mbox_handler_attach_resources()
1774 mutex_unlock(&rvu->rsrc_lock); in rvu_mbox_handler_attach_resources()
1786 for (vec = 0; vec < pfvf->msix.max; vec++) { in rvu_get_msix_offset()
1787 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) in rvu_get_msix_offset()
1799 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | in rvu_set_msix_offset()
1800 (lf << block->lfshift)); in rvu_set_msix_offset()
1803 /* Check and alloc MSIX vectors, must be contiguous */ in rvu_set_msix_offset()
1804 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) in rvu_set_msix_offset()
1807 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); in rvu_set_msix_offset()
1810 rvu_write64(rvu, block->addr, block->msixcfg_reg | in rvu_set_msix_offset()
1811 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); in rvu_set_msix_offset()
1815 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); in rvu_set_msix_offset()
1824 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | in rvu_clear_msix_offset()
1825 (lf << block->lfshift)); in rvu_clear_msix_offset()
1829 rvu_write64(rvu, block->addr, block->msixcfg_reg | in rvu_clear_msix_offset()
1830 (lf << block->lfshift), cfg & ~0x7FFULL); in rvu_clear_msix_offset()
1832 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); in rvu_clear_msix_offset()
1836 pfvf->msix_lfmap[offset + vec] = 0; in rvu_clear_msix_offset()
1839 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); in rvu_clear_msix_offset()
1845 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_msix_offset()
1846 u16 pcifunc = req->hdr.pcifunc; in rvu_mbox_handler_msix_offset()
1851 if (!pfvf->msix.bmap) in rvu_mbox_handler_msix_offset()
1855 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); in rvu_mbox_handler_msix_offset()
1856 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); in rvu_mbox_handler_msix_offset()
1861 rsp->nix_msixoff = MSIX_VECTOR_INVALID; in rvu_mbox_handler_msix_offset()
1863 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); in rvu_mbox_handler_msix_offset()
1864 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); in rvu_mbox_handler_msix_offset()
1867 rsp->sso = pfvf->sso; in rvu_mbox_handler_msix_offset()
1868 for (slot = 0; slot < rsp->sso; slot++) { in rvu_mbox_handler_msix_offset()
1869 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1870 rsp->sso_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1874 rsp->ssow = pfvf->ssow; in rvu_mbox_handler_msix_offset()
1875 for (slot = 0; slot < rsp->ssow; slot++) { in rvu_mbox_handler_msix_offset()
1876 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1877 rsp->ssow_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1881 rsp->timlfs = pfvf->timlfs; in rvu_mbox_handler_msix_offset()
1882 for (slot = 0; slot < rsp->timlfs; slot++) { in rvu_mbox_handler_msix_offset()
1883 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1884 rsp->timlf_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1888 rsp->cptlfs = pfvf->cptlfs; in rvu_mbox_handler_msix_offset()
1889 for (slot = 0; slot < rsp->cptlfs; slot++) { in rvu_mbox_handler_msix_offset()
1890 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1891 rsp->cptlf_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1895 rsp->cpt1_lfs = pfvf->cpt1_lfs; in rvu_mbox_handler_msix_offset()
1896 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { in rvu_mbox_handler_msix_offset()
1897 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1898 rsp->cpt1_lf_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1908 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_free_rsrc_cnt()
1913 mutex_lock(&rvu->rsrc_lock); in rvu_mbox_handler_free_rsrc_cnt()
1915 block = &hw->block[BLKADDR_NPA]; in rvu_mbox_handler_free_rsrc_cnt()
1916 rsp->npa = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
1918 block = &hw->block[BLKADDR_NIX0]; in rvu_mbox_handler_free_rsrc_cnt()
1919 rsp->nix = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
1921 block = &hw->block[BLKADDR_NIX1]; in rvu_mbox_handler_free_rsrc_cnt()
1922 rsp->nix1 = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
1924 block = &hw->block[BLKADDR_SSO]; in rvu_mbox_handler_free_rsrc_cnt()
1925 rsp->sso = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
1927 block = &hw->block[BLKADDR_SSOW]; in rvu_mbox_handler_free_rsrc_cnt()
1928 rsp->ssow = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
1930 block = &hw->block[BLKADDR_TIM]; in rvu_mbox_handler_free_rsrc_cnt()
1931 rsp->tim = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
1933 block = &hw->block[BLKADDR_CPT0]; in rvu_mbox_handler_free_rsrc_cnt()
1934 rsp->cpt = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
1936 block = &hw->block[BLKADDR_CPT1]; in rvu_mbox_handler_free_rsrc_cnt()
1937 rsp->cpt1 = rvu_rsrc_free_count(&block->lf); in rvu_mbox_handler_free_rsrc_cnt()
1939 if (rvu->hw->cap.nix_fixed_txschq_mapping) { in rvu_mbox_handler_free_rsrc_cnt()
1940 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1941 rsp->schq[NIX_TXSCH_LVL_TL4] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1942 rsp->schq[NIX_TXSCH_LVL_TL3] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1943 rsp->schq[NIX_TXSCH_LVL_TL2] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1945 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) in rvu_mbox_handler_free_rsrc_cnt()
1947 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1948 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1949 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1950 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1953 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; in rvu_mbox_handler_free_rsrc_cnt()
1954 rsp->schq[NIX_TXSCH_LVL_SMQ] = in rvu_mbox_handler_free_rsrc_cnt()
1955 rvu_rsrc_free_count(&txsch->schq); in rvu_mbox_handler_free_rsrc_cnt()
1957 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; in rvu_mbox_handler_free_rsrc_cnt()
1958 rsp->schq[NIX_TXSCH_LVL_TL4] = in rvu_mbox_handler_free_rsrc_cnt()
1959 rvu_rsrc_free_count(&txsch->schq); in rvu_mbox_handler_free_rsrc_cnt()
1961 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; in rvu_mbox_handler_free_rsrc_cnt()
1962 rsp->schq[NIX_TXSCH_LVL_TL3] = in rvu_mbox_handler_free_rsrc_cnt()
1963 rvu_rsrc_free_count(&txsch->schq); in rvu_mbox_handler_free_rsrc_cnt()
1965 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; in rvu_mbox_handler_free_rsrc_cnt()
1966 rsp->schq[NIX_TXSCH_LVL_TL2] = in rvu_mbox_handler_free_rsrc_cnt()
1967 rvu_rsrc_free_count(&txsch->schq); in rvu_mbox_handler_free_rsrc_cnt()
1969 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) in rvu_mbox_handler_free_rsrc_cnt()
1973 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; in rvu_mbox_handler_free_rsrc_cnt()
1974 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = in rvu_mbox_handler_free_rsrc_cnt()
1975 rvu_rsrc_free_count(&txsch->schq); in rvu_mbox_handler_free_rsrc_cnt()
1977 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; in rvu_mbox_handler_free_rsrc_cnt()
1978 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = in rvu_mbox_handler_free_rsrc_cnt()
1979 rvu_rsrc_free_count(&txsch->schq); in rvu_mbox_handler_free_rsrc_cnt()
1981 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; in rvu_mbox_handler_free_rsrc_cnt()
1982 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = in rvu_mbox_handler_free_rsrc_cnt()
1983 rvu_rsrc_free_count(&txsch->schq); in rvu_mbox_handler_free_rsrc_cnt()
1985 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; in rvu_mbox_handler_free_rsrc_cnt()
1986 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = in rvu_mbox_handler_free_rsrc_cnt()
1987 rvu_rsrc_free_count(&txsch->schq); in rvu_mbox_handler_free_rsrc_cnt()
1990 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1992 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; in rvu_mbox_handler_free_rsrc_cnt()
1993 mutex_unlock(&rvu->rsrc_lock); in rvu_mbox_handler_free_rsrc_cnt()
2001 u16 pcifunc = req->hdr.pcifunc; in rvu_mbox_handler_vf_flr()
2028 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_get_hw_cap()
2030 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; in rvu_mbox_handler_get_hw_cap()
2031 rsp->nix_shaping = hw->cap.nix_shaping; in rvu_mbox_handler_get_hw_cap()
2032 rsp->npc_hash_extract = hw->cap.npc_hash_extract; in rvu_mbox_handler_get_hw_cap()
2040 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_set_vf_perm()
2041 u16 pcifunc = req->hdr.pcifunc; in rvu_mbox_handler_set_vf_perm()
2048 return -EOPNOTSUPP; in rvu_mbox_handler_set_vf_perm()
2050 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); in rvu_mbox_handler_set_vf_perm()
2053 if (req->flags & RESET_VF_PERM) { in rvu_mbox_handler_set_vf_perm()
2054 pfvf->flags &= RVU_CLEAR_VF_PERM; in rvu_mbox_handler_set_vf_perm()
2055 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ in rvu_mbox_handler_set_vf_perm()
2056 (req->flags & VF_TRUSTED)) { in rvu_mbox_handler_set_vf_perm()
2057 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); in rvu_mbox_handler_set_vf_perm()
2059 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { in rvu_mbox_handler_set_vf_perm()
2063 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], in rvu_mbox_handler_set_vf_perm()
2083 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_ndc_sync_op()
2084 u16 pcifunc = req->hdr.pcifunc; in rvu_mbox_handler_ndc_sync_op()
2087 if (req->npa_lf_sync) { in rvu_mbox_handler_ndc_sync_op()
2093 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); in rvu_mbox_handler_ndc_sync_op()
2101 dev_err(rvu->dev, in rvu_mbox_handler_ndc_sync_op()
2102 "NDC-NPA sync failed for LF %u\n", lfidx); in rvu_mbox_handler_ndc_sync_op()
2105 if (!req->nix_lf_tx_sync && !req->nix_lf_rx_sync) in rvu_mbox_handler_ndc_sync_op()
2113 lfidx = rvu_get_lf(rvu, &hw->block[lfblkaddr], pcifunc, 0); in rvu_mbox_handler_ndc_sync_op()
2117 if (req->nix_lf_tx_sync) { in rvu_mbox_handler_ndc_sync_op()
2122 dev_err(rvu->dev, in rvu_mbox_handler_ndc_sync_op()
2123 "NDC-NIX-TX sync fail for LF %u\n", lfidx); in rvu_mbox_handler_ndc_sync_op()
2126 if (req->nix_lf_rx_sync) { in rvu_mbox_handler_ndc_sync_op()
2131 dev_err(rvu->dev, in rvu_mbox_handler_ndc_sync_op()
2132 "NDC-NIX-RX sync failed for LF %u\n", lfidx); in rvu_mbox_handler_ndc_sync_op()
2141 struct rvu *rvu = pci_get_drvdata(mbox->pdev); in rvu_process_mbox_msg()
2144 if (req->sig != OTX2_MBOX_REQ_SIG) in rvu_process_mbox_msg()
2147 switch (req->id) { in rvu_process_mbox_msg()
2162 return -ENOMEM; \ in rvu_process_mbox_msg()
2164 rsp->hdr.id = _id; \ in rvu_process_mbox_msg()
2165 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ in rvu_process_mbox_msg()
2166 rsp->hdr.pcifunc = req->pcifunc; \ in rvu_process_mbox_msg()
2167 rsp->hdr.rc = 0; \ in rvu_process_mbox_msg()
2174 rsp->hdr.rc = err; \ in rvu_process_mbox_msg()
2176 trace_otx2_msg_process(mbox->pdev, _id, err); \ in rvu_process_mbox_msg()
2177 return rsp ? err : -ENOMEM; \ in rvu_process_mbox_msg()
2184 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); in rvu_process_mbox_msg()
2185 return -ENODEV; in rvu_process_mbox_msg()
2191 struct rvu *rvu = mwork->rvu; in __rvu_mbox_handler()
2201 mw = &rvu->afpf_wq_info; in __rvu_mbox_handler()
2204 mw = &rvu->afvf_wq_info; in __rvu_mbox_handler()
2210 devid = mwork - mw->mbox_wrk; in __rvu_mbox_handler()
2211 mbox = &mw->mbox; in __rvu_mbox_handler()
2212 mdev = &mbox->dev[devid]; in __rvu_mbox_handler()
2215 req_hdr = mdev->mbase + mbox->rx_start; in __rvu_mbox_handler()
2216 if (mw->mbox_wrk[devid].num_msgs == 0) in __rvu_mbox_handler()
2219 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); in __rvu_mbox_handler()
2221 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { in __rvu_mbox_handler()
2222 msg = mdev->mbase + offset; in __rvu_mbox_handler()
2227 msg->pcifunc &= in __rvu_mbox_handler()
2229 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); in __rvu_mbox_handler()
2232 msg->pcifunc &= in __rvu_mbox_handler()
2234 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; in __rvu_mbox_handler()
2240 offset = mbox->rx_start + msg->next_msgoff; in __rvu_mbox_handler()
2244 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) in __rvu_mbox_handler()
2245 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", in __rvu_mbox_handler()
2246 err, otx2_mbox_id2name(msg->id), in __rvu_mbox_handler()
2247 msg->id, rvu_get_pf(msg->pcifunc), in __rvu_mbox_handler()
2248 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); in __rvu_mbox_handler()
2250 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", in __rvu_mbox_handler()
2251 err, otx2_mbox_id2name(msg->id), in __rvu_mbox_handler()
2252 msg->id, devid); in __rvu_mbox_handler()
2254 mw->mbox_wrk[devid].num_msgs = 0; in __rvu_mbox_handler()
2266 struct rvu *rvu = mwork->rvu; in rvu_afpf_mbox_handler()
2268 mutex_lock(&rvu->mbox_lock); in rvu_afpf_mbox_handler()
2270 mutex_unlock(&rvu->mbox_lock); in rvu_afpf_mbox_handler()
2282 struct rvu *rvu = mwork->rvu; in __rvu_mbox_up_handler()
2292 mw = &rvu->afpf_wq_info; in __rvu_mbox_up_handler()
2295 mw = &rvu->afvf_wq_info; in __rvu_mbox_up_handler()
2301 devid = mwork - mw->mbox_wrk_up; in __rvu_mbox_up_handler()
2302 mbox = &mw->mbox_up; in __rvu_mbox_up_handler()
2303 mdev = &mbox->dev[devid]; in __rvu_mbox_up_handler()
2305 rsp_hdr = mdev->mbase + mbox->rx_start; in __rvu_mbox_up_handler()
2306 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { in __rvu_mbox_up_handler()
2307 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); in __rvu_mbox_up_handler()
2311 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); in __rvu_mbox_up_handler()
2313 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { in __rvu_mbox_up_handler()
2314 msg = mdev->mbase + offset; in __rvu_mbox_up_handler()
2316 if (msg->id >= MBOX_MSG_MAX) { in __rvu_mbox_up_handler()
2317 dev_err(rvu->dev, in __rvu_mbox_up_handler()
2318 "Mbox msg with unknown ID 0x%x\n", msg->id); in __rvu_mbox_up_handler()
2322 if (msg->sig != OTX2_MBOX_RSP_SIG) { in __rvu_mbox_up_handler()
2323 dev_err(rvu->dev, in __rvu_mbox_up_handler()
2325 msg->sig, msg->id); in __rvu_mbox_up_handler()
2329 switch (msg->id) { in __rvu_mbox_up_handler()
2333 if (msg->rc) in __rvu_mbox_up_handler()
2334 dev_err(rvu->dev, in __rvu_mbox_up_handler()
2336 msg->rc, msg->id); in __rvu_mbox_up_handler()
2340 offset = mbox->rx_start + msg->next_msgoff; in __rvu_mbox_up_handler()
2341 mdev->msgs_acked++; in __rvu_mbox_up_handler()
2343 mw->mbox_wrk_up[devid].up_num_msgs = 0; in __rvu_mbox_up_handler()
2363 int num, int type, unsigned long *pf_bmap) in rvu_get_mbox_regions() argument
2365 struct rvu_hwinfo *hw = rvu->hw; in rvu_get_mbox_regions()
2370 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from in rvu_get_mbox_regions()
2374 for (region = 0; region < num; region++) { in rvu_get_mbox_regions()
2378 if (hw->cap.per_pf_mbox_regs) { in rvu_get_mbox_regions()
2394 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per in rvu_get_mbox_regions()
2398 for (region = 0; region < num; region++) { in rvu_get_mbox_regions()
2402 if (hw->cap.per_pf_mbox_regs) { in rvu_get_mbox_regions()
2417 while (region--) in rvu_get_mbox_regions()
2419 return -ENOMEM; in rvu_get_mbox_regions()
2423 int type, int num, in rvu_mbox_init() argument
2427 int err = -EINVAL, i, dir, dir_up; in rvu_mbox_init()
2435 pf_bmap = bitmap_zalloc(num, GFP_KERNEL); in rvu_mbox_init()
2437 return -ENOMEM; in rvu_mbox_init()
2441 bitmap_set(pf_bmap, 0, num); in rvu_mbox_init()
2445 for (i = 0; i < num; i++) { in rvu_mbox_init()
2452 mutex_init(&rvu->mbox_lock); in rvu_mbox_init()
2454 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); in rvu_mbox_init()
2456 err = -ENOMEM; in rvu_mbox_init()
2465 reg_base = rvu->afreg_base; in rvu_mbox_init()
2466 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF, pf_bmap); in rvu_mbox_init()
2474 reg_base = rvu->pfreg_base; in rvu_mbox_init()
2475 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF, pf_bmap); in rvu_mbox_init()
2483 mw->mbox_wq = alloc_workqueue("%s", in rvu_mbox_init()
2485 num, name); in rvu_mbox_init()
2486 if (!mw->mbox_wq) { in rvu_mbox_init()
2487 err = -ENOMEM; in rvu_mbox_init()
2491 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, in rvu_mbox_init()
2493 if (!mw->mbox_wrk) { in rvu_mbox_init()
2494 err = -ENOMEM; in rvu_mbox_init()
2498 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, in rvu_mbox_init()
2500 if (!mw->mbox_wrk_up) { in rvu_mbox_init()
2501 err = -ENOMEM; in rvu_mbox_init()
2505 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, in rvu_mbox_init()
2506 reg_base, dir, num, pf_bmap); in rvu_mbox_init()
2510 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, in rvu_mbox_init()
2511 reg_base, dir_up, num, pf_bmap); in rvu_mbox_init()
2515 for (i = 0; i < num; i++) { in rvu_mbox_init()
2519 mwork = &mw->mbox_wrk[i]; in rvu_mbox_init()
2520 mwork->rvu = rvu; in rvu_mbox_init()
2521 INIT_WORK(&mwork->work, mbox_handler); in rvu_mbox_init()
2523 mwork = &mw->mbox_wrk_up[i]; in rvu_mbox_init()
2524 mwork->rvu = rvu; in rvu_mbox_init()
2525 INIT_WORK(&mwork->work, mbox_up_handler); in rvu_mbox_init()
2530 destroy_workqueue(mw->mbox_wq); in rvu_mbox_init()
2532 while (num--) in rvu_mbox_init()
2533 iounmap((void __iomem *)mbox_regions[num]); in rvu_mbox_init()
2543 struct otx2_mbox *mbox = &mw->mbox; in rvu_mbox_destroy()
2547 if (mw->mbox_wq) { in rvu_mbox_destroy()
2548 destroy_workqueue(mw->mbox_wq); in rvu_mbox_destroy()
2549 mw->mbox_wq = NULL; in rvu_mbox_destroy()
2552 for (devid = 0; devid < mbox->ndevs; devid++) { in rvu_mbox_destroy()
2553 mdev = &mbox->dev[devid]; in rvu_mbox_destroy()
2554 if (mdev->hwbase) in rvu_mbox_destroy()
2555 iounmap((void __iomem *)mdev->hwbase); in rvu_mbox_destroy()
2558 otx2_mbox_destroy(&mw->mbox); in rvu_mbox_destroy()
2559 otx2_mbox_destroy(&mw->mbox_up); in rvu_mbox_destroy()
2572 if (!(intr & BIT_ULL(i - first))) in rvu_queue_work()
2575 mbox = &mw->mbox; in rvu_queue_work()
2576 mdev = &mbox->dev[i]; in rvu_queue_work()
2577 hdr = mdev->mbase + mbox->rx_start; in rvu_queue_work()
2579 /*The hdr->num_msgs is set to zero immediately in the interrupt in rvu_queue_work()
2582 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler in rvu_queue_work()
2587 if (hdr->num_msgs) { in rvu_queue_work()
2588 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; in rvu_queue_work()
2589 hdr->num_msgs = 0; in rvu_queue_work()
2590 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); in rvu_queue_work()
2592 mbox = &mw->mbox_up; in rvu_queue_work()
2593 mdev = &mbox->dev[i]; in rvu_queue_work()
2594 hdr = mdev->mbase + mbox->rx_start; in rvu_queue_work()
2595 if (hdr->num_msgs) { in rvu_queue_work()
2596 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; in rvu_queue_work()
2597 hdr->num_msgs = 0; in rvu_queue_work()
2598 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); in rvu_queue_work()
2612 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); in rvu_mbox_pf_intr_handler()
2617 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); in rvu_mbox_pf_intr_handler()
2625 int vfs = rvu->vfs; in rvu_mbox_intr_handler()
2636 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); in rvu_mbox_intr_handler()
2637 vfs -= 64; in rvu_mbox_intr_handler()
2643 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); in rvu_mbox_intr_handler()
2645 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); in rvu_mbox_intr_handler()
2652 struct rvu_hwinfo *hw = rvu->hw; in rvu_enable_mbox_intr()
2656 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); in rvu_enable_mbox_intr()
2660 INTR_MASK(hw->total_pfs) & ~1ULL); in rvu_enable_mbox_intr()
2669 block = &rvu->hw->block[blkaddr]; in rvu_blklf_teardown()
2671 block->addr); in rvu_blklf_teardown()
2680 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) in rvu_blklf_teardown()
2681 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); in rvu_blklf_teardown()
2682 else if (block->addr == BLKADDR_NPA) in rvu_blklf_teardown()
2684 else if ((block->addr == BLKADDR_CPT0) || in rvu_blklf_teardown()
2685 (block->addr == BLKADDR_CPT1)) in rvu_blklf_teardown()
2686 rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf, in rvu_blklf_teardown()
2691 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", in rvu_blklf_teardown()
2692 block->addr, lf); in rvu_blklf_teardown()
2702 mutex_lock(&rvu->flr_lock); in __rvu_flr_handler()
2703 /* Reset order should reflect inter-block dependencies: in __rvu_flr_handler()
2727 * Since LF is detached use LF number as -1. in __rvu_flr_handler()
2729 rvu_npc_free_mcam_entries(rvu, pcifunc, -1); in __rvu_flr_handler()
2732 if (rvu->mcs_blk_cnt) in __rvu_flr_handler()
2735 mutex_unlock(&rvu->flr_lock); in __rvu_flr_handler()
2747 vf = vf - 64; in rvu_afvf_flr_handler()
2758 struct rvu *rvu = flrwork->rvu; in rvu_flr_handler()
2763 pf = flrwork - rvu->flr_wrk; in rvu_flr_handler()
2764 if (pf >= rvu->hw->total_pfs) { in rvu_flr_handler()
2765 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); in rvu_flr_handler()
2804 dev = vf + start_vf + rvu->hw->total_pfs; in rvu_afvf_queue_flr_work()
2805 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); in rvu_afvf_queue_flr_work()
2819 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { in rvu_flr_intr_handler()
2828 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); in rvu_flr_intr_handler()
2834 if (rvu->vfs > 64) in rvu_flr_intr_handler()
2835 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); in rvu_flr_intr_handler()
2887 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { in rvu_me_pf_intr_handler()
2909 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
2913 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
2917 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
2919 for (irq = 0; irq < rvu->num_vec; irq++) { in rvu_unregister_interrupts()
2920 if (rvu->irq_allocated[irq]) { in rvu_unregister_interrupts()
2921 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); in rvu_unregister_interrupts()
2922 rvu->irq_allocated[irq] = false; in rvu_unregister_interrupts()
2926 pci_free_irq_vectors(rvu->pdev); in rvu_unregister_interrupts()
2927 rvu->num_vec = 0; in rvu_unregister_interrupts()
2932 struct rvu_pfvf *pfvf = &rvu->pf[0]; in rvu_afvf_msix_vectors_num_ok()
2935 pfvf = &rvu->pf[0]; in rvu_afvf_msix_vectors_num_ok()
2938 /* Make sure there are enough MSIX vectors configured so that in rvu_afvf_msix_vectors_num_ok()
2940 * that PF vectors are not configured and overlapping AF vectors. in rvu_afvf_msix_vectors_num_ok()
2942 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && in rvu_afvf_msix_vectors_num_ok()
2950 rvu->num_vec = pci_msix_vec_count(rvu->pdev); in rvu_register_interrupts()
2952 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, in rvu_register_interrupts()
2954 if (!rvu->irq_name) in rvu_register_interrupts()
2955 return -ENOMEM; in rvu_register_interrupts()
2957 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, in rvu_register_interrupts()
2959 if (!rvu->irq_allocated) in rvu_register_interrupts()
2960 return -ENOMEM; in rvu_register_interrupts()
2962 /* Enable MSI-X */ in rvu_register_interrupts()
2963 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, in rvu_register_interrupts()
2964 rvu->num_vec, PCI_IRQ_MSIX); in rvu_register_interrupts()
2966 dev_err(rvu->dev, in rvu_register_interrupts()
2967 "RVUAF: Request for %d msix vectors failed, ret %d\n", in rvu_register_interrupts()
2968 rvu->num_vec, ret); in rvu_register_interrupts()
2973 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); in rvu_register_interrupts()
2974 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), in rvu_register_interrupts()
2976 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); in rvu_register_interrupts()
2978 dev_err(rvu->dev, in rvu_register_interrupts()
2983 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; in rvu_register_interrupts()
2989 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], in rvu_register_interrupts()
2991 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), in rvu_register_interrupts()
2993 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], in rvu_register_interrupts()
2996 dev_err(rvu->dev, in rvu_register_interrupts()
3000 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; in rvu_register_interrupts()
3004 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); in rvu_register_interrupts()
3007 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_register_interrupts()
3010 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], in rvu_register_interrupts()
3012 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), in rvu_register_interrupts()
3014 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], in rvu_register_interrupts()
3017 dev_err(rvu->dev, in rvu_register_interrupts()
3020 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; in rvu_register_interrupts()
3024 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); in rvu_register_interrupts()
3027 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); in rvu_register_interrupts()
3030 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_register_interrupts()
3035 /* Get PF MSIX vectors offset. */ in rvu_register_interrupts()
3041 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); in rvu_register_interrupts()
3042 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
3044 &rvu->irq_name[offset * NAME_SIZE], in rvu_register_interrupts()
3047 dev_err(rvu->dev, in rvu_register_interrupts()
3050 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
3056 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); in rvu_register_interrupts()
3057 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
3059 &rvu->irq_name[offset * NAME_SIZE], in rvu_register_interrupts()
3062 dev_err(rvu->dev, in rvu_register_interrupts()
3065 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
3069 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); in rvu_register_interrupts()
3070 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
3072 &rvu->irq_name[offset * NAME_SIZE], rvu); in rvu_register_interrupts()
3074 dev_err(rvu->dev, in rvu_register_interrupts()
3078 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
3081 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); in rvu_register_interrupts()
3082 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
3084 &rvu->irq_name[offset * NAME_SIZE], rvu); in rvu_register_interrupts()
3086 dev_err(rvu->dev, in rvu_register_interrupts()
3090 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
3094 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); in rvu_register_interrupts()
3095 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
3097 &rvu->irq_name[offset * NAME_SIZE], rvu); in rvu_register_interrupts()
3099 dev_err(rvu->dev, in rvu_register_interrupts()
3103 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
3106 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); in rvu_register_interrupts()
3107 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
3109 &rvu->irq_name[offset * NAME_SIZE], rvu); in rvu_register_interrupts()
3111 dev_err(rvu->dev, in rvu_register_interrupts()
3115 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
3130 if (rvu->flr_wq) { in rvu_flr_wq_destroy()
3131 destroy_workqueue(rvu->flr_wq); in rvu_flr_wq_destroy()
3132 rvu->flr_wq = NULL; in rvu_flr_wq_destroy()
3143 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { in rvu_flr_init()
3149 rvu->flr_wq = alloc_ordered_workqueue("rvu_afpf_flr", in rvu_flr_init()
3151 if (!rvu->flr_wq) in rvu_flr_init()
3152 return -ENOMEM; in rvu_flr_init()
3154 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); in rvu_flr_init()
3155 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, in rvu_flr_init()
3157 if (!rvu->flr_wrk) { in rvu_flr_init()
3158 destroy_workqueue(rvu->flr_wq); in rvu_flr_init()
3159 return -ENOMEM; in rvu_flr_init()
3163 rvu->flr_wrk[dev].rvu = rvu; in rvu_flr_init()
3164 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); in rvu_flr_init()
3167 mutex_init(&rvu->flr_lock); in rvu_flr_init()
3174 int vfs = rvu->vfs; in rvu_disable_afvf_intr()
3183 INTR_MASK(vfs - 64)); in rvu_disable_afvf_intr()
3184 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); in rvu_disable_afvf_intr()
3185 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); in rvu_disable_afvf_intr()
3190 int vfs = rvu->vfs; in rvu_enable_afvf_intr()
3208 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
3210 INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
3212 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
3213 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
3214 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
3221 int ret = -EIO; in rvu_get_num_lbk_chans()
3243 struct pci_dev *pdev = rvu->pdev; in rvu_enable_sriov()
3248 dev_warn(&pdev->dev, in rvu_enable_sriov()
3257 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &rvu->vf_devid); in rvu_enable_sriov()
3282 rvu->vfs = vfs; in rvu_enable_sriov()
3284 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, in rvu_enable_sriov()
3296 rvu_mbox_destroy(&rvu->afvf_wq_info); in rvu_enable_sriov()
3306 rvu_mbox_destroy(&rvu->afvf_wq_info); in rvu_disable_sriov()
3307 pci_disable_sriov(rvu->pdev); in rvu_disable_sriov()
3314 strscpy(rvu->mkex_pfl_name, in rvu_update_module_params()
3316 strscpy(rvu->kpu_pfl_name, in rvu_update_module_params()
3322 struct device *dev = &pdev->dev; in rvu_probe()
3328 return -ENOMEM; in rvu_probe()
3330 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); in rvu_probe()
3331 if (!rvu->hw) { in rvu_probe()
3333 return -ENOMEM; in rvu_probe()
3337 rvu->pdev = pdev; in rvu_probe()
3338 rvu->dev = &pdev->dev; in rvu_probe()
3360 rvu->ptp = ptp_get(); in rvu_probe()
3361 if (IS_ERR(rvu->ptp)) { in rvu_probe()
3362 err = PTR_ERR(rvu->ptp); in rvu_probe()
3365 rvu->ptp = NULL; in rvu_probe()
3369 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); in rvu_probe()
3370 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); in rvu_probe()
3371 if (!rvu->afreg_base || !rvu->pfreg_base) { in rvu_probe()
3373 err = -ENOMEM; in rvu_probe()
3392 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, in rvu_probe()
3393 rvu->hw->total_pfs, rvu_afpf_mbox_handler, in rvu_probe()
3430 mutex_init(&rvu->rswitch.switch_lock); in rvu_probe()
3432 if (rvu->fwdata) in rvu_probe()
3433 ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, in rvu_probe()
3434 rvu->fwdata->ptp_ext_tstamp); in rvu_probe()
3444 rvu_mbox_destroy(&rvu->afpf_wq_info); in rvu_probe()
3453 ptp_put(rvu->ptp); in rvu_probe()
3460 devm_kfree(&pdev->dev, rvu->hw); in rvu_probe()
3476 rvu_mbox_destroy(&rvu->afpf_wq_info); in rvu_remove()
3481 ptp_put(rvu->ptp); in rvu_remove()
3486 devm_kfree(&pdev->dev, rvu->hw); in rvu_remove()
3487 devm_kfree(&pdev->dev, rvu); in rvu_remove()