Lines Matching +full:max +full:- +full:adj
1 // SPDX-License-Identifier: GPL-2.0
67 #define is_rev_A0(ptp) (((ptp)->pdev->revision & 0x0F) == 0x0)
68 #define is_rev_A1(ptp) (((ptp)->pdev->revision & 0x0F) == 0x1)
82 return ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A_PTP;
87 return ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_PTP;
101 struct ptp *ptp = rvu->ptp;
124 delta_ns = ktime_to_ns(ktime_sub(curr_ts, ptp->last_ts));
130 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI);
132 period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - ptp_clock_hi));
134 writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI);
135 period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - delta_ns));
139 ptp->last_ts = curr_ts;
148 period_ns = ktime_set(0, (NSEC_PER_SEC + 100 - start_ns));
149 hrtimer_start(&ptp->hrtimer, period_ns, HRTIMER_MODE_REL);
150 ptp->last_ts = ktime_get();
158 spin_lock_irqsave(&ptp->ptp_lock, flags);
159 sec = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL;
160 nsec = readq(ptp->reg_base + PTP_CLOCK_HI);
161 sec1 = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL;
164 nsec = readq(ptp->reg_base + PTP_CLOCK_HI);
167 spin_unlock_irqrestore(&ptp->ptp_lock, flags);
174 return readq(ptp->reg_base + PTP_CLOCK_HI);
179 u64 comp, adj = 0, cycles_per_sec, ns_drift = 0;
184 * Issue #1: At the time of 1 sec rollover of the nano-second counter,
185 * the nano-second counter is set to 0. However, it should be set to
186 * (existing counter_value - 10^9).
188 * Issue #2: The nano-second counter rolls over at 0x3B9A_C9FF.
200 cycle = cycles_per_sec - 1;
209 ns_drift = ptp_clock_nsec - NSEC_PER_SEC;
212 adj = comp * ns_drift;
213 adj = adj / 1000000000ULL;
216 comp += adj;
221 adj = comp * cycle_time;
222 adj = adj / 1000000000ULL;
223 adj = adj / CYCLE_MULT;
224 comp -= adj;
235 return ERR_PTR(-ENODEV);
238 ptp = ERR_PTR(-EPROBE_DEFER);
240 pci_dev_get(ptp->pdev);
250 pci_dev_put(ptp->pdev);
258 writeq(timestamp, ptp->reg_base + PTP_NANO_TIMESTAMP);
259 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);
261 ptp->reg_base + PTP_SEC_TIMESTAMP);
264 curr_rollover_set = nxt_rollover_set - NSEC_PER_SEC;
265 writeq(nxt_rollover_set, ptp->reg_base + PTP_NXT_ROLLOVER_SET);
266 writeq(curr_rollover_set, ptp->reg_base + PTP_CURR_ROLLOVER_SET);
269 regval = readq(ptp->reg_base + PTP_CLOCK_CFG);
272 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG);
281 delta = -delta;
290 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI);
293 ptp_clock_hi -= delta;
295 ptp_clock_hi = delta - ptp_clock_hi;
301 writeq(delta, ptp->reg_base + PTP_NANO_TIMESTAMP);
302 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);
305 regval = readq(ptp->reg_base + PTP_CLOCK_CFG);
308 writeq(regval, ptp->reg_base + PTP_CLOCK_CFG);
316 u64 comp, adj;
321 scaled_ppm = -scaled_ppm;
327 * convention compensation value is in 64 bit fixed-point
345 freq_adj = (ptp->clock_rate * ppb) / 1000000000ULL;
346 freq = neg_adj ? ptp->clock_rate + freq_adj : ptp->clock_rate - freq_adj;
349 comp = ((u64)1000000000ull << 32) / ptp->clock_rate;
350 adj = comp * ppb;
351 adj = div_u64(adj, 1000000000ull);
352 comp = neg_adj ? comp - adj : comp + adj;
354 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP);
362 *clk = ptp->read_ptp_tstmp(ptp);
369 struct ptp *ptp = rvu->ptp;
377 pdev = ptp->pdev;
380 dev_err(&pdev->dev, "PTP input clock cannot be zero\n");
385 ptp->clock_rate = sclk * 1000000;
389 writeq(0, ptp->reg_base + PTP_NANO_TIMESTAMP);
390 writeq(0, ptp->reg_base + PTP_FRNS_TIMESTAMP);
391 writeq(0, ptp->reg_base + PTP_SEC_TIMESTAMP);
392 writeq(0, ptp->reg_base + PTP_CURR_ROLLOVER_SET);
393 writeq(0x3b9aca00, ptp->reg_base + PTP_NXT_ROLLOVER_SET);
394 writeq(0x3b9aca00, ptp->reg_base + PTP_SEC_ROLLOVER);
398 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
401 ptp->clock_rate = ext_clk_freq;
415 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
416 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
419 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
422 clock_comp = ptp_calc_adjusted_comp(ptp->clock_rate);
424 clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate;
427 writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP);
435 timestamp = readq(ptp->reg_base + PTP_TIMESTAMP);
438 *clk = readq(ptp->reg_base + PTP_TIMESTAMP);
447 writeq(thresh, ptp->reg_base + PTP_PPS_THRESH_HI);
457 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI);
460 if (hrtimer_active(&ptp->hrtimer))
461 hrtimer_cancel(&ptp->hrtimer);
471 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
474 dev_err(&ptp->pdev->dev, "Supports max period value as 1 second\n");
475 return -EINVAL;
479 dev_err(&ptp->pdev->dev, "Supports max period as 8 seconds\n");
480 return -EINVAL;
484 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
486 writeq(0, ptp->reg_base + PTP_PPS_THRESH_HI);
487 writeq(0, ptp->reg_base + PTP_PPS_THRESH_LO);
491 writeq(((u64)period << 32), ptp->reg_base + PTP_PPS_HI_INCR);
492 writeq(((u64)period << 32), ptp->reg_base + PTP_PPS_LO_INCR);
495 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
506 ptp->clock_period = NSEC_PER_SEC / ptp->clock_rate;
507 writeq((0x1dcd6500ULL - ptp->clock_period) << 32,
508 ptp->reg_base + PTP_PPS_LO_INCR);
525 err = -ENOMEM;
529 ptp->pdev = pdev;
539 ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];
545 spin_lock_init(&ptp->ptp_lock);
547 ptp->read_ptp_tstmp = &read_ptp_tstmp_sec_nsec;
548 hrtimer_setup(&ptp->hrtimer, ptp_reset_thresh, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
550 ptp->read_ptp_tstmp = &read_ptp_tstmp_nsec;
562 * `dev->driver_data`.
579 if (cn10k_ptp_errata(ptp) && hrtimer_active(&ptp->hrtimer))
580 hrtimer_cancel(&ptp->hrtimer);
583 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
585 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
631 if (!rvu->ptp)
632 return -ENODEV;
634 switch (req->op) {
636 err = ptp_adjfine(rvu->ptp, req->scaled_ppm);
639 err = ptp_get_clock(rvu->ptp, &rsp->clk);
642 err = ptp_get_tstmp(rvu->ptp, &rsp->clk);
645 err = ptp_set_thresh(rvu->ptp, req->thresh);
648 err = ptp_pps_on(rvu->ptp, req->pps_on, req->period);
651 ptp_atomic_adjtime(rvu->ptp, req->delta);
654 ptp_atomic_update(rvu->ptp, (u64)req->clk);
657 err = -EINVAL;
667 if (!rvu->ptp)
668 return -ENODEV;
671 rsp->cap |= PTP_CAP_HW_ATOMIC_UPDATE;
673 rsp->cap &= ~BIT_ULL_MASK(0);