1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port)	(0x00 + 4 * (port))  argument
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port)	(0x20 + 4 * (port))  argument
38 #define MVPP22_TX_FIFO_THRESH_REG(port)		(0x8840 + 4 * (port))  argument
39 #define MVPP22_TX_FIFO_SIZE_REG(port)		(0x8860 + 4 * (port))  argument
42 #define MVPP2_RX_CTRL_REG(port)			(0x140 + 4 * (port))  argument
61 #define MVPP2_MH_REG(port)			(0x5040 + 4 * (port))  argument
70 #define     MVPP2_PRS_PORT_LU_MASK(port)	(0xff << ((port) * 4))  argument
71 #define     MVPP2_PRS_PORT_LU_VAL(port, val)	((val) << ((port) * 4))  argument
72 #define MVPP2_PRS_INIT_OFFS_REG(port)		(0x1004 + ((port) & 4))  argument
73 #define     MVPP2_PRS_INIT_OFF_MASK(port)	(0x3f << (((port) % 4) * 8))  argument
74 #define     MVPP2_PRS_INIT_OFF_VAL(port, val)	((val) << (((port) % 4) * 8))  argument
75 #define MVPP2_PRS_MAX_LOOP_REG(port)		(0x100c + ((port) & 4))  argument
76 #define     MVPP2_PRS_MAX_LOOP_MASK(port)	(0xff << (((port) % 4) * 8))  argument
77 #define     MVPP2_PRS_MAX_LOOP_VAL(port, val)	((val) << (((port) % 4) * 8))  argument
103 #define     MVPP2_CLS_PORT_WAY_MASK(port)	(1 << (port))  argument
117 #define     MVPP2_CLS_FLOW_TBL0_PORT_ID(port)	((port) << 4)  argument
131 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port)	(0x1980 + ((port) * 4))  argument
134 #define MVPP2_CLS_SWFWD_P2HQ_REG(port)		(0x19b0 + ((port) * 4))  argument
136 #define     MVPP2_CLS_SWFWD_PCTRL_MASK(port)	(1 << (port))  argument
146 #define     MVPP22_CLS_C2_PORT_ID(port)		((port) << 8)  argument
258 #define MVPP2_ISR_TX_THRESHOLD_REG(port)	(0x5140 + 4 * (port))  argument
263 #define MVPP21_ISR_RXQ_GROUP_REG(port)		(0x5400 + 4 * (port))  argument
278 #define MVPP2_ISR_ENABLE_REG(port)		(0x5420 + 4 * (port))  argument
281 #define MVPP2_ISR_RX_TX_CAUSE_REG(port)		(0x5480 + 4 * (port))  argument
292 #define MVPP2_ISR_RX_TX_MASK_REG(port)		(0x54a0 + 4 * (port))  argument
298 #define MVPP2_ISR_RX_ERR_CAUSE_REG(port)	(0x5520 + 4 * (port))  argument
355 /* Packet Processor per-port counters */
365 #define     MVPP22_CTRS_TX_CTR(port, txq)	((txq) | ((port) << 3) | BIT(7))  argument
410 #define     MVPP2_TX_PORT_FLUSH_MASK(port)	(1 << (port))  argument
420 /* Per-port registers */
485 /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
486  * relative to port->base.
522 /* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
526 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
590 #define MVPP22_GMAC_BASE(port)		(0x7000 + (port) * 0x1000 + 0xe00)  argument
596 	(((index) < (q)->last_desc) ? ((index) + 1) : 0)
599 #define MVPP22_MPCS_BASE(port)			(0x7000 + (port) * 0x1000)  argument
610 #define MVPP22_FCA_BASE(port)			(0x7600 + (port) * 0x1000)  argument
619 #define MVPP22_XPCS_BASE(port)			(0x7400 + (port) * 0x1000)  argument
626 #define MVPP22_PTP_BASE(port)			(0x7800 + (port * 0x1000))  argument
714 /* Maximum number of T-CONTs of PON port */
720 /* Loopback port index */
723 /* Maximum number of TXQs used by single port */
727  * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data),
733 /* Max number of RXQs per port */
754 #define MVPP2_TX_DESC_ALIGN		(MVPP2_DESC_ALIGNED_SIZE - 1)
771 		((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
779 #define MVPP2_RX_FC_REG(port)		(0x150 + 4 * (port))  argument
844 	((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE)
846 #define MVPP2_MAX_RX_BUF_SIZE	(PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM)
855 /* There are 7 supported high-level flows */
865 /* Port flags */
933 #define MVPP2_BM_POOL_SIZE_MAX		(16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
1037 	 * used per CPU.
1041 	/* On PPv2.2 and PPv2.3, some port control registers are located into
1054 	/* List of pointers to port structures */
1070 	/* Are we using page_pool with per-cpu pools? */
1087 	/* Maximum number of RXQs per port */
1129 /* Per-CPU port control */
1145 	struct mvpp2_port *port;  member
1166 	/* TCAM key and mask for C2-based steering. These fields should be
1188 	/* Index of the port from the "group of ports" complex point
1197 	/* Firmware node associated to the port */
1200 	/* Per-port registers' base address */
1214 	/* Per-CPU port control */
1233 	/* Per-port work and its lock to gather hardware statistics */
1249 	/* Index of first port's physical RXQ */
1258 	/* List of steering rules active on that port */
1262 	/* Each port has its own view of the rss contexts, so that it can number
1398 /* Per-CPU Tx queue control */
1443 	/* Per-CPU control of physical Tx queues */
1462 	/* RX queue number, in the range 0-31 for physical RXQs */
1483 	/* ID of port to which physical RXQ is mapped */
1484 	int port;  member
1486 	/* Port's logic RXQ number to which physical RXQ is mapped */
1495 	/* Pool number in the range 0-7 */
1520 	((addr) >= (txq_pcpu)->tso_headers_dma && \
1521 	 (addr) < (txq_pcpu)->tso_headers_dma + \
1522 	 (txq_pcpu)->size * TSO_HEADER_SIZE)
1535 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
1561 	return -1;  in mvpp22_tai_ptp_clock_index()
1565 static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)  in mvpp22_rx_hwtstamping()  argument
1567 	return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;  in mvpp22_rx_hwtstamping()