Lines Matching +full:8 +full:- +full:port
1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) argument
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) argument
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
61 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) argument
70 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
71 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
72 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) argument
73 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) argument
74 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
75 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) argument
76 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) argument
77 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) argument
92 #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8)
103 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) argument
117 #define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) ((port) << 4) argument
131 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) argument
134 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) argument
136 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) argument
146 #define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8) argument
147 #define MVPP22_CLS_C2_PORT_MASK (0xff << 8)
174 #define MVPP22_DESC_ADDR_OFFS 8
216 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
258 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) argument
263 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) argument
276 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
278 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) argument
281 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) argument
292 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) argument
298 #define MVPP2_ISR_RX_ERR_CAUSE_REG(port) (0x5520 + 4 * (port)) argument
319 #define MVPP2_BM_LOW_THRESH_OFFS 8
344 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8
353 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
355 /* Packet Processor per-port counters */
361 #define MVPP23_BM_8POOL_MODE BIT(8)
365 #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7)) argument
386 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
410 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) argument
420 /* Per-port registers */
485 #define MVPP2_GMAC_LPI_CTRL0_TS_MASK GENMASK(15, 8)
490 /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
491 * relative to port->base.
499 #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8)
527 /* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
531 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
595 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) argument
601 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
604 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) argument
615 #define MVPP22_FCA_BASE(port) (0x7600 + (port) * 0x1000) argument
624 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) argument
631 #define MVPP22_PTP_BASE(port) (0x7800 + (port * 0x1000)) argument
704 #define MVPP2_PPPOE_HDR_SIZE 8
706 #define MVPP2_VLAN_TAG_EDSA_LEN 8
719 /* Maximum number of T-CONTs of PON port */
725 /* Loopback port index */
728 /* Maximum number of TXQs used by single port */
729 #define MVPP2_MAX_TXQ 8
738 /* Max number of RXQs per port */
759 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
776 ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
784 #define MVPP2_RX_FC_REG(port) (0x150 + 4 * (port)) argument
822 #define MSS_RXQ_ASS_PER_OFFS 8
849 ((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE)
851 #define MVPP2_MAX_RX_BUF_SIZE (PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM)
853 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
860 /* There are 7 supported high-level flows */
864 #define MVPP22_N_RSS_TABLES 8
870 /* Port flags */
912 MVPP22_PTP_ACTION_ADDINGRESSTIME = 8,
938 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
940 #define MVPP2_BM_MAX_POOLS 8
943 #define MVPP2_BM_COOKIE_POOL_OFFS 8
1046 /* On PPv2.2 and PPv2.3, some port control registers are located into
1059 /* List of pointers to port structures */
1075 /* Are we using page_pool with per-cpu pools? */
1092 /* Maximum number of RXQs per port */
1137 /* Per-CPU port control */
1153 struct mvpp2_port *port; member
1174 /* TCAM key and mask for C2-based steering. These fields should be
1196 /* Index of the port from the "group of ports" complex point
1205 /* Firmware node associated to the port */
1208 /* Per-port registers' base address */
1222 /* Per-CPU port control */
1241 /* Per-port work and its lock to gather hardware statistics */
1257 /* Index of first port's physical RXQ */
1266 /* List of steering rules active on that port */
1270 /* Each port has its own view of the rss contexts, so that it can number
1290 #define MVPP2_TXD_IP_HLEN_SHIFT 8
1406 /* Per-CPU Tx queue control */
1451 /* Per-CPU control of physical Tx queues */
1470 /* RX queue number, in the range 0-31 for physical RXQs */
1491 /* ID of port to which physical RXQ is mapped */
1492 int port; member
1494 /* Port's logic RXQ number to which physical RXQ is mapped */
1503 /* Pool number in the range 0-7 */
1528 ((addr) >= (txq_pcpu)->tso_headers_dma && \
1529 (addr) < (txq_pcpu)->tso_headers_dma + \
1530 (txq_pcpu)->size * TSO_HEADER_SIZE)
1543 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
1569 return -1; in mvpp22_tai_ptp_clock_index()
1573 static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port) in mvpp22_rx_hwtstamping() argument
1575 return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp; in mvpp22_rx_hwtstamping()