Lines Matching +full:0 +full:x5400
28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
45 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
47 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
48 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
51 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
52 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
54 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
55 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
57 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
61 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
63 #define MVPP2_VER_ID_REG 0x50b0
64 #define MVPP2_VER_PP22 0x10
65 #define MVPP2_VER_PP23 0x11
68 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
69 #define MVPP2_PRS_PORT_LU_MAX 0xf
70 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
72 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
73 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
75 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
76 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
78 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
79 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
81 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
82 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
83 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
84 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
85 #define MVPP2_PRS_TCAM_HIT_IDX_REG 0x1240
86 #define MVPP2_PRS_TCAM_HIT_CNT_REG 0x1244
87 #define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0)
90 #define MVPP22_RSS_INDEX 0x1500
94 #define MVPP22_RXQ2RSS_TABLE 0x1504
96 #define MVPP22_RSS_TABLE_ENTRY 0x1508
97 #define MVPP22_RSS_WIDTH 0x150c
100 #define MVPP2_CLS_MODE_REG 0x1800
101 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
102 #define MVPP2_CLS_PORT_WAY_REG 0x1810
104 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
106 #define MVPP2_CLS_LKP_TBL_REG 0x1818
107 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
110 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
111 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
112 #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0)
113 #define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7
116 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff
119 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
120 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7
122 #define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) (((lu) & 0x3f) << 3)
123 #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f
125 #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7
127 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
128 #define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f
131 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
133 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
134 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
135 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
139 #define MVPP22_CLS_C2_TCAM_IDX 0x1b00
140 #define MVPP22_CLS_C2_TCAM_DATA0 0x1b10
141 #define MVPP22_CLS_C2_TCAM_DATA1 0x1b14
142 #define MVPP22_CLS_C2_TCAM_DATA2 0x1b18
143 #define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c
144 #define MVPP22_CLS_C2_TCAM_DATA4 0x1b20
145 #define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f)
147 #define MVPP22_CLS_C2_PORT_MASK (0xff << 8)
148 #define MVPP22_CLS_C2_TCAM_INV 0x1b24
150 #define MVPP22_CLS_C2_HIT_CTR 0x1b50
151 #define MVPP22_CLS_C2_ACT 0x1b60
152 #define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19)
153 #define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13)
154 #define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11)
155 #define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9)
156 #define MVPP22_CLS_C2_ACT_COLOR(act) ((act) & 0x7)
157 #define MVPP22_CLS_C2_ATTR0 0x1b64
158 #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24)
159 #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f
161 #define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21)
162 #define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7
164 #define MVPP22_CLS_C2_ATTR1 0x1b68
165 #define MVPP22_CLS_C2_ATTR2 0x1b6c
167 #define MVPP22_CLS_C2_ATTR3 0x1b70
168 #define MVPP22_CLS_C2_TCAM_CTRL 0x1b90
169 #define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0)
172 #define MVPP2_RXQ_NUM_REG 0x2040
173 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
175 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
176 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
177 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
178 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
180 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
181 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
183 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
184 #define MVPP2_RXQ_THRESH_REG 0x204c
185 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
186 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
187 #define MVPP2_RXQ_INDEX_REG 0x2050
188 #define MVPP2_TXQ_NUM_REG 0x2080
189 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
190 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
191 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
192 #define MVPP2_TXQ_THRESH_REG 0x2094
194 #define MVPP2_TXQ_THRESH_MASK 0x3fff
195 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
196 #define MVPP2_TXQ_INDEX_REG 0x2098
197 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
198 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
203 #define MVPP2_TXQ_PENDING_REG 0x20a0
204 #define MVPP2_TXQ_PENDING_MASK 0x3fff
205 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
206 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
208 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
209 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
211 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
212 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
213 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
215 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
217 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
218 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
219 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
220 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
221 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
224 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
225 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
226 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
227 #define MVPP2_BASE_ADDR_ENABLE 0x4060
230 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
231 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
232 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
233 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
234 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
235 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
236 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
237 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
238 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
239 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
240 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
241 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
244 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
247 #define MVPP22_AXI_CODE_CACHE_OFFS 0
250 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
251 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
252 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
258 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port))
259 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0
261 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
262 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
263 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port))
265 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
266 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
267 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
270 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
271 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
273 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
274 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
275 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
278 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
279 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
280 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
281 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
283 ((version) == MVPP21 ? 0xffff : 0xff)
284 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
292 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
293 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
294 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
295 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
297 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
298 #define MVPP2_ISR_RX_ERR_CAUSE_REG(port) (0x5520 + 4 * (port))
299 #define MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK 0x00ff
302 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
303 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
304 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
305 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
306 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
307 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
308 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
309 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
310 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
311 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
312 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
313 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8
315 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
316 #define MVPP2_BM_START_MASK BIT(0)
320 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
324 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
327 #define MVPP2_BM_BPPI_HIGH_THRESH 0x1E
328 #define MVPP2_BM_BPPI_LOW_THRESH 0x1C
329 #define MVPP23_BM_BPPI_HIGH_THRESH 0x34
330 #define MVPP23_BM_BPPI_LOW_THRESH 0x28
331 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
332 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
337 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
338 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
339 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
340 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
341 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444
342 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff
343 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00
345 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
346 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
349 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
350 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
351 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
352 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
356 #define MVPP2_OVERRUN_ETH_DROP 0x7000
357 #define MVPP2_CLS_ETH_DROP 0x7020
359 #define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG 0x6310
360 #define MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK 0xff
364 #define MVPP2_CTRS_IDX 0x7040
366 #define MVPP2_TX_DESC_ENQ_CTR 0x7100
367 #define MVPP2_TX_DESC_ENQ_TO_DDR_CTR 0x7104
368 #define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR 0x7108
369 #define MVPP2_TX_DESC_ENQ_HW_FWD_CTR 0x710c
370 #define MVPP2_RX_DESC_ENQ_CTR 0x7120
371 #define MVPP2_TX_PKTS_DEQ_CTR 0x7130
372 #define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR 0x7200
373 #define MVPP2_TX_PKTS_EARLY_DROP_CTR 0x7204
374 #define MVPP2_TX_PKTS_BM_DROP_CTR 0x7208
375 #define MVPP2_TX_PKTS_BM_MC_DROP_CTR 0x720c
376 #define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR 0x7220
377 #define MVPP2_RX_PKTS_EARLY_DROP_CTR 0x7224
378 #define MVPP2_RX_PKTS_BM_DROP_CTR 0x7228
379 #define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700
380 #define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704
383 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
384 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
385 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
387 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
388 #define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014
389 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
390 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
391 #define MVPP2_TXP_MTU_MAX 0x7FFFF
392 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
393 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
394 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
396 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
397 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
398 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
399 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
400 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
402 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
403 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
404 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
405 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
408 #define MVPP2_TX_SNOOP_REG 0x8800
409 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
413 #define MVPP2_SRC_ADDR_MIDDLE 0x24
414 #define MVPP2_SRC_ADDR_HIGH 0x28
415 #define MVPP2_PHY_AN_CFG0_REG 0x34
417 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
418 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
421 #define MVPP2_GMAC_CTRL_0_REG 0x0
422 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
425 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
427 #define MVPP2_GMAC_CTRL_1_REG 0x4
433 #define MVPP2_GMAC_CTRL_2_REG 0x8
434 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
440 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
441 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
454 #define MVPP2_GMAC_STATUS0 0x10
455 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)
462 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
464 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
467 #define MVPP22_GMAC_INT_STAT 0x20
469 #define MVPP22_GMAC_INT_MASK 0x24
471 #define MVPP22_GMAC_CTRL_4_REG 0x90
472 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
478 #define MVPP22_GMAC_INT_SUM_STAT 0xa0
481 #define MVPP22_GMAC_INT_SUM_MASK 0xa4
485 /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
488 #define MVPP22_XLG_CTRL0_REG 0x100
489 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
496 #define MVPP22_XLG_CTRL1_REG 0x104
497 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0
498 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff
499 #define MVPP22_XLG_STATUS 0x10c
500 #define MVPP22_XLG_STATUS_LINK_UP BIT(0)
501 #define MVPP22_XLG_INT_STAT 0x114
503 #define MVPP22_XLG_INT_MASK 0x118
505 #define MVPP22_XLG_CTRL3_REG 0x11c
507 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
509 #define MVPP22_XLG_EXT_INT_STAT 0x158
512 #define MVPP22_XLG_EXT_INT_MASK 0x15c
516 #define MVPP22_XLG_CTRL4_REG 0x184
523 #define MVPP22_SMI_MISC_CFG_REG 0x1204
527 #define MVPP22_TAI_INT_CAUSE 0x1400
528 #define MVPP22_TAI_INT_MASK 0x1404
529 #define MVPP22_TAI_CR0 0x1408
530 #define MVPP22_TAI_CR1 0x140c
531 #define MVPP22_TAI_TCFCR0 0x1410
532 #define MVPP22_TAI_TCFCR1 0x1414
533 #define MVPP22_TAI_TCFCR2 0x1418
534 #define MVPP22_TAI_FATWR 0x141c
535 #define MVPP22_TAI_TOD_STEP_NANO_CR 0x1420
536 #define MVPP22_TAI_TOD_STEP_FRAC_HIGH 0x1424
537 #define MVPP22_TAI_TOD_STEP_FRAC_LOW 0x1428
538 #define MVPP22_TAI_TAPDC_HIGH 0x142c
539 #define MVPP22_TAI_TAPDC_LOW 0x1430
540 #define MVPP22_TAI_TGTOD_SEC_HIGH 0x1434
541 #define MVPP22_TAI_TGTOD_SEC_MED 0x1438
542 #define MVPP22_TAI_TGTOD_SEC_LOW 0x143c
543 #define MVPP22_TAI_TGTOD_NANO_HIGH 0x1440
544 #define MVPP22_TAI_TGTOD_NANO_LOW 0x1444
545 #define MVPP22_TAI_TGTOD_FRAC_HIGH 0x1448
546 #define MVPP22_TAI_TGTOD_FRAC_LOW 0x144c
547 #define MVPP22_TAI_TLV_SEC_HIGH 0x1450
548 #define MVPP22_TAI_TLV_SEC_MED 0x1454
549 #define MVPP22_TAI_TLV_SEC_LOW 0x1458
550 #define MVPP22_TAI_TLV_NANO_HIGH 0x145c
551 #define MVPP22_TAI_TLV_NANO_LOW 0x1460
552 #define MVPP22_TAI_TLV_FRAC_HIGH 0x1464
553 #define MVPP22_TAI_TLV_FRAC_LOW 0x1468
554 #define MVPP22_TAI_TCV0_SEC_HIGH 0x146c
555 #define MVPP22_TAI_TCV0_SEC_MED 0x1470
556 #define MVPP22_TAI_TCV0_SEC_LOW 0x1474
557 #define MVPP22_TAI_TCV0_NANO_HIGH 0x1478
558 #define MVPP22_TAI_TCV0_NANO_LOW 0x147c
559 #define MVPP22_TAI_TCV0_FRAC_HIGH 0x1480
560 #define MVPP22_TAI_TCV0_FRAC_LOW 0x1484
561 #define MVPP22_TAI_TCV1_SEC_HIGH 0x1488
562 #define MVPP22_TAI_TCV1_SEC_MED 0x148c
563 #define MVPP22_TAI_TCV1_SEC_LOW 0x1490
564 #define MVPP22_TAI_TCV1_NANO_HIGH 0x1494
565 #define MVPP22_TAI_TCV1_NANO_LOW 0x1498
566 #define MVPP22_TAI_TCV1_FRAC_HIGH 0x149c
567 #define MVPP22_TAI_TCV1_FRAC_LOW 0x14a0
568 #define MVPP22_TAI_TCSR 0x14a4
569 #define MVPP22_TAI_TUC_LSB 0x14a8
570 #define MVPP22_TAI_GFM_SEC_HIGH 0x14ac
571 #define MVPP22_TAI_GFM_SEC_MED 0x14b0
572 #define MVPP22_TAI_GFM_SEC_LOW 0x14b4
573 #define MVPP22_TAI_GFM_NANO_HIGH 0x14b8
574 #define MVPP22_TAI_GFM_NANO_LOW 0x14bc
575 #define MVPP22_TAI_GFM_FRAC_HIGH 0x14c0
576 #define MVPP22_TAI_GFM_FRAC_LOW 0x14c4
577 #define MVPP22_TAI_PCLK_DA_HIGH 0x14c8
578 #define MVPP22_TAI_PCLK_DA_LOW 0x14cc
579 #define MVPP22_TAI_CTCR 0x14d0
580 #define MVPP22_TAI_PCLK_CCC_HIGH 0x14d4
581 #define MVPP22_TAI_PCLK_CCC_LOW 0x14d8
582 #define MVPP22_TAI_DTC_HIGH 0x14dc
583 #define MVPP22_TAI_DTC_LOW 0x14e0
584 #define MVPP22_TAI_CCC_HIGH 0x14e4
585 #define MVPP22_TAI_CCC_LOW 0x14e8
586 #define MVPP22_TAI_ICICE 0x14f4
587 #define MVPP22_TAI_ICICC_LOW 0x14f8
588 #define MVPP22_TAI_TUC_MSB 0x14fc
590 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)
592 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
596 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
599 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
600 #define MVPP22_MPCS_CTRL 0x14
602 #define MVPP22_MPCS_CLK_RESET 0x14c
603 #define MAC_CLK_RESET_SD_TX BIT(0)
610 #define MVPP22_FCA_BASE(port) (0x7600 + (port) * 0x1000)
612 #define MVPP22_FCA_REG_MASK 0xFFFF
613 #define MVPP22_FCA_CONTROL_REG 0x0
615 #define MVPP22_PERIODIC_COUNTER_LSB_REG (0x110)
616 #define MVPP22_PERIODIC_COUNTER_MSB_REG (0x114)
619 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
620 #define MVPP22_XPCS_CFG0 0x0
621 #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0)
626 #define MVPP22_PTP_BASE(port) (0x7800 + (port * 0x1000))
627 #define MVPP22_PTP_INT_CAUSE 0x00
630 #define MVPP22_PTP_INT_MASK 0x04
633 #define MVPP22_PTP_GCR 0x08
636 #define MVPP22_PTP_GCR_TSU_ENABLE BIT(0)
637 #define MVPP22_PTP_TX_Q0_R0 0x0c
638 #define MVPP22_PTP_TX_Q0_R1 0x10
639 #define MVPP22_PTP_TX_Q0_R2 0x14
640 #define MVPP22_PTP_TX_Q1_R0 0x18
641 #define MVPP22_PTP_TX_Q1_R1 0x1c
642 #define MVPP22_PTP_TX_Q1_R2 0x20
643 #define MVPP22_PTP_TPCR 0x24
644 #define MVPP22_PTP_V1PCR 0x28
645 #define MVPP22_PTP_V2PCR 0x2c
646 #define MVPP22_PTP_Y1731PCR 0x30
647 #define MVPP22_PTP_NTPTSPCR 0x34
648 #define MVPP22_PTP_NTPRXPCR 0x38
649 #define MVPP22_PTP_NTPTXPCR 0x3c
650 #define MVPP22_PTP_WAMPPCR 0x40
651 #define MVPP22_PTP_NAPCR 0x44
652 #define MVPP22_PTP_FAPCR 0x48
653 #define MVPP22_PTP_CAPCR 0x50
654 #define MVPP22_PTP_ATAPCR 0x54
655 #define MVPP22_PTP_ACTAPCR 0x58
656 #define MVPP22_PTP_CATAPCR 0x5c
657 #define MVPP22_PTP_CACTAPCR 0x60
658 #define MVPP22_PTP_AITAPCR 0x64
659 #define MVPP22_PTP_CAITAPCR 0x68
660 #define MVPP22_PTP_CITAPCR 0x6c
661 #define MVPP22_PTP_NTP_OFF_HIGH 0x70
662 #define MVPP22_PTP_NTP_OFF_LOW 0x74
663 #define MVPP22_PTP_TX_PIPE_STATUS_DELAY 0x78
666 #define GENCONF_SOFT_RESET1 0x1108
668 #define GENCONF_PORT_CTRL0 0x1110
672 #define GENCONF_PORT_CTRL1 0x1114
675 #define GENCONF_CTRL0 0x1120
676 #define GENCONF_CTRL0_PORT2_RGMII BIT(0)
704 #define MVPP2_IP_LBDT_TYPE 0xfffa
712 #define MVPP2_TX_MTU_MAX 0x7ffff
757 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB 0xb000
758 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000
759 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000
760 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000
762 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40
763 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
779 #define MVPP2_RX_FC_REG(port) (0x150 + 4 * (port))
782 #define MVPP2_RX_FC_TRSH_MASK (0xFF << MVPP2_RX_FC_TRSH_OFFS)
786 #define MSS_FC_COM_REG 0
787 #define FLOW_CONTROL_ENABLE_BIT BIT(0)
789 #define FC_QUANTA 0xFFFF
792 #define MSS_RXQ_TRESH_BASE 0x200
797 #define MSS_BUF_POOL_BASE 0x40
802 #define MSS_BUF_POOL_STOP_MASK 0xFFF
803 #define MSS_BUF_POOL_START_MASK (0xFFF << MSS_BUF_POOL_START_OFFS)
805 #define MSS_BUF_POOL_PORTS_MASK (0xF << MSS_BUF_POOL_PORTS_OFFS)
807 #define MSS_BUF_POOL_PORT_OFFS(id) (0x1 << \
810 #define MSS_RXQ_TRESH_START_MASK 0xFFFF
811 #define MSS_RXQ_TRESH_STOP_MASK (0xFFFF << MSS_RXQ_TRESH_STOP_OFFS)
814 #define MSS_RXQ_ASS_BASE 0x80
818 #define MSS_RXQ_ASS_PORTID_OFFS 0
819 #define MSS_RXQ_ASS_PORTID_MASK 0x3
821 #define MSS_RXQ_ASS_HOSTID_MASK 0x3F
866 #define MVPP2_F_LOOPBACK BIT(0)
871 MVPP2_TAG_TYPE_NONE = 0,
895 #define MVPP22_PTP_DESC_MASK_LOW 0xfff
899 MVPP22_PTP_ACTION_NONE = 0,
914 MVPP22_PTP_PKT_FMT_PTPV2 = 0,
923 #define MVPP22_PTP_ACTION(x) (((x) & 15) << 0)
952 #define MVPP21_ADDR_SPACE_SZ 0
959 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000
960 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400
961 #define MVPP22_MIB_COUNTERS_OFFSET 0x0
962 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100
964 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0
965 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8
966 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc
967 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10
968 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18
969 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c
970 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20
971 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24
972 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28
973 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c
974 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30
975 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
976 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38
977 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40
978 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48
979 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c
980 #define MVPP2_MIB_FC_SENT 0x54
981 #define MVPP2_MIB_FC_RCVD 0x58
982 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c
983 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60
984 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64
985 #define MVPP2_MIB_OVERSIZE_RCVD 0x68
986 #define MVPP2_MIB_JABBER_RCVD 0x6c
987 #define MVPP2_MIB_MAC_RCV_ERROR 0x70
988 #define MVPP2_MIB_BAD_CRC_EVENT 0x74
989 #define MVPP2_MIB_COLLISION 0x78
990 #define MVPP2_MIB_LATE_COLLISION 0x7c
997 #define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
1263 * them from 0
1281 #define MVPP2_TXD_L3_OFF_SHIFT 0
1294 #define MVPP2_RXD_ERR_CRC 0x0
1462 /* RX queue number, in the range 0-31 for physical RXQs */
1495 /* Pool number in the range 0-7 */
1547 return 0; in mvpp22_tai_probe()