Lines Matching +full:auto +full:- +full:retry
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
68 * Returns one's complement 8-bit sum.
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
93 int retry = 0;
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 return -EBUSY;
119 /* Re-start condition */
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 retry++;
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
151 } while (retry < max_retry);
153 return -EIO;
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
171 int retry = 0;
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 return -EBUSY;
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 retry++;
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
216 } while (retry < max_retry);
218 return -EIO;
222 * ixgbe_probe_phy - Probe a single address for a PHY
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
249 hw->phy.type = ixgbe_phy_cu_unknown;
251 hw->phy.type = ixgbe_phy_generic;
258 * ixgbe_identify_phy_generic - Get physical layer module
265 u32 status = -EFAULT;
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
275 if (hw->phy.type != ixgbe_phy_unknown)
278 if (hw->phy.nw_mng_if_sel) {
280 hw->phy.nw_mng_if_sel);
284 return -EFAULT;
299 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
305 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
318 if (hw->mac.type == ixgbe_mac_82598EB)
331 * ixgbe_get_phy_id - Get the phy type
341 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
345 hw->phy.id = (u32)(phy_id_high << 16);
346 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
349 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
355 * ixgbe_get_phy_type_from_id - Get the phy type
394 * ixgbe_reset_phy_generic - Performs a PHY reset
403 if (hw->phy.type == ixgbe_phy_unknown)
406 if (status != 0 || hw->phy.type == ixgbe_phy_none)
410 if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw))
421 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
426 * Poll for reset bit to self-clear indicating reset is complete.
432 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
433 status = hw->phy.ops.read_reg(hw,
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
458 return -EIO;
465 * ixgbe_read_phy_reg_mdi - read PHY register
481 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
501 return -EIO;
509 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
528 return -EIO;
542 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
543 * using the SWFW lock - this function is needed in most cases
552 u32 gssr = hw->phy.phy_semaphore_mask;
555 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
558 hw->mac.ops.release_swfw_sync(hw, gssr);
560 return -EBUSY;
567 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
585 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
605 return -EIO;
614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
633 return -EIO;
640 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
641 * using SWFW lock- this function is needed in most cases
650 u32 gssr = hw->phy.phy_semaphore_mask;
653 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
656 hw->mac.ops.release_swfw_sync(hw, gssr);
658 return -EBUSY;
667 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
681 * ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags
693 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
694 return -EBUSY;
709 hw->mac.ops.release_swfw_sync(hw, gssr);
714 * ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags
727 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
728 return -EBUSY;
747 hw->mac.ops.release_swfw_sync(hw, gssr);
752 * ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags
765 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
766 return -EBUSY;
777 hw->mac.ops.release_swfw_sync(hw, gssr);
782 * ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags
797 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
798 return -EBUSY;
814 hw->mac.ops.release_swfw_sync(hw, gssr);
819 * ixgbe_mii_bus_read_c22 - Read a clause 22 register
826 struct ixgbe_adapter *adapter = bus->priv;
827 struct ixgbe_hw *hw = &adapter->hw;
828 u32 gssr = hw->phy.phy_semaphore_mask;
834 * ixgbe_mii_bus_read_c45 - Read a clause 45 register
843 struct ixgbe_adapter *adapter = bus->priv;
844 struct ixgbe_hw *hw = &adapter->hw;
845 u32 gssr = hw->phy.phy_semaphore_mask;
851 * ixgbe_mii_bus_write_c22 - Write a clause 22 register
860 struct ixgbe_adapter *adapter = bus->priv;
861 struct ixgbe_hw *hw = &adapter->hw;
862 u32 gssr = hw->phy.phy_semaphore_mask;
868 * ixgbe_mii_bus_write_c45 - Write a clause 45 register
878 struct ixgbe_adapter *adapter = bus->priv;
879 struct ixgbe_hw *hw = &adapter->hw;
880 u32 gssr = hw->phy.phy_semaphore_mask;
887 * ixgbe_x550em_a_mii_bus_read_c22 - Read a clause 22 register on x550em_a
895 struct ixgbe_adapter *adapter = bus->priv;
896 struct ixgbe_hw *hw = &adapter->hw;
897 u32 gssr = hw->phy.phy_semaphore_mask;
904 * ixgbe_x550em_a_mii_bus_read_c45 - Read a clause 45 register on x550em_a
913 struct ixgbe_adapter *adapter = bus->priv;
914 struct ixgbe_hw *hw = &adapter->hw;
915 u32 gssr = hw->phy.phy_semaphore_mask;
922 * ixgbe_x550em_a_mii_bus_write_c22 - Write a clause 22 register on x550em_a
931 struct ixgbe_adapter *adapter = bus->priv;
932 struct ixgbe_hw *hw = &adapter->hw;
933 u32 gssr = hw->phy.phy_semaphore_mask;
940 * ixgbe_x550em_a_mii_bus_write_c45 - Write a clause 45 register on x550em_a
950 struct ixgbe_adapter *adapter = bus->priv;
951 struct ixgbe_hw *hw = &adapter->hw;
952 u32 gssr = hw->phy.phy_semaphore_mask;
960 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
972 if (rp_pdev && rp_pdev->subordinate) {
973 bus = rp_pdev->subordinate->number;
983 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
992 struct ixgbe_adapter *adapter = hw->back;
993 struct pci_dev *pdev = adapter->pdev;
1019 * ixgbe_mii_bus_init - mii_bus structure setup
1033 struct ixgbe_adapter *adapter = hw->back;
1034 struct pci_dev *pdev = adapter->pdev;
1035 struct device *dev = &adapter->netdev->dev;
1038 switch (hw->device_id) {
1066 return -ENOMEM;
1068 bus->read = read_c22;
1069 bus->write = write_c22;
1070 bus->read_c45 = read_c45;
1071 bus->write_c45 = write_c45;
1074 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
1077 bus->name = "ixgbe-mdio";
1078 bus->priv = adapter;
1079 bus->parent = dev;
1080 bus->phy_mask = GENMASK(31, 0);
1086 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
1088 adapter->mii_bus = bus;
1093 * ixgbe_setup_phy_link_generic - Set and restart autoneg
1107 /* Set or unset auto-negotiation 10G advertisement */
1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1111 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1120 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_e610) {
1121 /* Set or unset auto-negotiation 5G advertisement */
1123 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
1127 /* Set or unset auto-negotiation 2.5G advertisement */
1129 if ((hw->phy.autoneg_advertised &
1135 /* Set or unset auto-negotiation 1G advertisement */
1137 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1141 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1144 /* Set or unset auto-negotiation 100M advertisement */
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1148 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1171 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1183 hw->phy.autoneg_advertised = 0;
1186 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1189 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1192 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1195 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1198 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1201 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1204 if (hw->phy.ops.setup_link)
1205 hw->phy.ops.setup_link(hw);
1211 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1214 * Determines the supported link capabilities by reading the PHY auto
1222 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1228 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1230 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1232 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1234 switch (hw->mac.type) {
1237 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1238 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1242 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1252 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1255 * @autoneg: boolean auto-negotiation value
1264 if (!hw->phy.speeds_supported)
1267 *speed = hw->phy.speeds_supported;
1272 * ixgbe_check_phy_link_tnx - Determine link and speed status
1301 status = hw->phy.ops.read_reg(hw,
1322 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1339 /* Set or unset auto-negotiation 10G advertisement */
1340 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1345 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1348 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1354 /* Set or unset auto-negotiation 1G advertisement */
1355 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1360 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1363 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1369 /* Set or unset auto-negotiation 100M advertisement */
1370 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1376 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1379 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1389 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1394 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1400 * ixgbe_reset_phy_nl - Performs a PHY reset
1416 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1419 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1423 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1432 return -EIO;
1441 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1447 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1461 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1466 ret_val = hw->eeprom.ops.read(hw, data_offset,
1470 hw->phy.ops.write_reg(hw, phy_offset,
1488 return -EIO;
1493 return -EIO;
1501 return -EIO;
1505 * ixgbe_identify_module_generic - Identifies module type
1512 switch (hw->mac.ops.get_media_type(hw)) {
1518 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1519 return -ENOENT;
1522 return -ENOENT;
1526 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1533 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1534 struct ixgbe_adapter *adapter = hw->back;
1546 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1547 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1548 return -ENOENT;
1552 hw->mac.ops.set_lan_id(hw);
1554 status = hw->phy.ops.read_i2c_eeprom(hw,
1562 hw->phy.type = ixgbe_phy_sfp_unsupported;
1563 return -EOPNOTSUPP;
1565 status = hw->phy.ops.read_i2c_eeprom(hw,
1572 status = hw->phy.ops.read_i2c_eeprom(hw,
1578 status = hw->phy.ops.read_i2c_eeprom(hw,
1584 status = hw->phy.ops.read_i2c_eeprom(hw,
1595 * 3 SFP_DA_CORE0 - 82599-specific
1596 * 4 SFP_DA_CORE1 - 82599-specific
1597 * 5 SFP_SR/LR_CORE0 - 82599-specific
1598 * 6 SFP_SR/LR_CORE1 - 82599-specific
1599 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1600 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1601 * 9 SFP_1g_cu_CORE0 - 82599-specific
1602 * 10 SFP_1g_cu_CORE1 - 82599-specific
1603 * 11 SFP_1g_sx_CORE0 - 82599-specific
1604 * 12 SFP_1g_sx_CORE1 - 82599-specific
1606 if (hw->mac.type == ixgbe_mac_82598EB) {
1608 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1610 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1612 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1614 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1617 if (hw->bus.lan_id == 0)
1618 hw->phy.sfp_type =
1621 hw->phy.sfp_type =
1624 hw->phy.ops.read_i2c_eeprom(
1629 if (hw->bus.lan_id == 0)
1630 hw->phy.sfp_type =
1633 hw->phy.sfp_type =
1636 hw->phy.sfp_type =
1642 if (hw->bus.lan_id == 0)
1643 hw->phy.sfp_type =
1646 hw->phy.sfp_type =
1649 if (hw->bus.lan_id == 0)
1650 hw->phy.sfp_type =
1653 hw->phy.sfp_type =
1656 if (hw->bus.lan_id == 0)
1657 hw->phy.sfp_type =
1660 hw->phy.sfp_type =
1663 if (hw->bus.lan_id == 0)
1664 hw->phy.sfp_type =
1667 hw->phy.sfp_type =
1669 /* Support only Ethernet 1000BASE-BX10, checking the Bit Rate
1670 * Nominal Value as per SFF-8472 by convention 1.25 Gb/s should
1671 * be rounded up to 0Dh (13 in units of 100 MBd) for 1000BASE-BX
1675 if (hw->bus.lan_id == 0)
1676 hw->phy.sfp_type =
1679 hw->phy.sfp_type =
1682 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1686 if (hw->phy.sfp_type != stored_sfp_type)
1687 hw->phy.sfp_setup_needed = true;
1690 hw->phy.multispeed_fiber = false;
1695 hw->phy.multispeed_fiber = true;
1698 if (hw->phy.type != ixgbe_phy_nl) {
1699 hw->phy.id = identifier;
1700 status = hw->phy.ops.read_i2c_eeprom(hw,
1707 status = hw->phy.ops.read_i2c_eeprom(hw,
1714 status = hw->phy.ops.read_i2c_eeprom(hw,
1729 hw->phy.type =
1734 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1736 hw->phy.type = ixgbe_phy_sfp_ftl;
1739 hw->phy.type = ixgbe_phy_sfp_avago;
1742 hw->phy.type = ixgbe_phy_sfp_intel;
1746 hw->phy.type =
1749 hw->phy.type =
1752 hw->phy.type = ixgbe_phy_sfp_unknown;
1764 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1765 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1766 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1767 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1768 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1769 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1770 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1771 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {
1772 hw->phy.type = ixgbe_phy_sfp_unsupported;
1773 return -EOPNOTSUPP;
1776 /* Anything else 82598-based is supported */
1777 if (hw->mac.type == ixgbe_mac_82598EB)
1780 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1782 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1783 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1784 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1785 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1786 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1787 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1788 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1789 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {
1791 if (hw->phy.type == ixgbe_phy_sfp_intel)
1793 if (hw->allow_unsupported_sfp) {
1798 hw->phy.type = ixgbe_phy_sfp_unsupported;
1799 return -EOPNOTSUPP;
1804 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1805 if (hw->phy.type != ixgbe_phy_nl) {
1806 hw->phy.id = 0;
1807 hw->phy.type = ixgbe_phy_unknown;
1809 return -ENOENT;
1813 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1820 struct ixgbe_adapter *adapter = hw->back;
1823 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1834 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1835 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1836 return -ENOENT;
1840 hw->mac.ops.set_lan_id(hw);
1842 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1849 hw->phy.type = ixgbe_phy_sfp_unsupported;
1850 return -EOPNOTSUPP;
1853 hw->phy.id = identifier;
1855 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1861 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1868 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1869 if (hw->bus.lan_id == 0)
1870 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1872 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1875 if (hw->bus.lan_id == 0)
1876 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1878 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1884 /* check for active DA cables that pre-date
1885 * SFF-8436 v3.6
1887 hw->phy.ops.read_i2c_eeprom(hw,
1891 hw->phy.ops.read_i2c_eeprom(hw,
1895 hw->phy.ops.read_i2c_eeprom(hw,
1908 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1909 if (hw->bus.lan_id == 0)
1910 hw->phy.sfp_type =
1913 hw->phy.sfp_type =
1917 hw->phy.type = ixgbe_phy_sfp_unsupported;
1918 return -EOPNOTSUPP;
1922 if (hw->phy.sfp_type != stored_sfp_type)
1923 hw->phy.sfp_setup_needed = true;
1926 hw->phy.multispeed_fiber = false;
1931 hw->phy.multispeed_fiber = true;
1936 status = hw->phy.ops.read_i2c_eeprom(hw,
1943 status = hw->phy.ops.read_i2c_eeprom(hw,
1950 status = hw->phy.ops.read_i2c_eeprom(hw,
1963 hw->phy.type = ixgbe_phy_qsfp_intel;
1965 hw->phy.type = ixgbe_phy_qsfp_unknown;
1967 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1970 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1972 if (hw->allow_unsupported_sfp) {
1977 hw->phy.type = ixgbe_phy_sfp_unsupported;
1978 return -EOPNOTSUPP;
1985 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1986 hw->phy.id = 0;
1987 hw->phy.type = ixgbe_phy_unknown;
1989 return -ENOENT;
1993 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
2006 u16 sfp_type = hw->phy.sfp_type;
2008 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
2009 return -EOPNOTSUPP;
2011 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2012 return -ENOENT;
2014 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
2015 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
2016 return -EOPNOTSUPP;
2036 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
2039 return -EIO;
2043 return -EIO;
2052 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2058 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
2062 return -EOPNOTSUPP;
2068 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2075 return -EOPNOTSUPP;
2082 return -EIO;
2086 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
2096 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2102 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
2107 * Performs byte read operation to SFP module's SFF-8472 data over I2C
2112 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2118 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2128 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2134 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2143 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2149 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2162 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2165 u32 retry = 0;
2168 if (hw->mac.type >= ixgbe_mac_X550)
2176 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2177 return -EBUSY;
2219 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2225 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2228 retry++;
2229 if (retry < max_retry)
2230 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2234 } while (retry < max_retry);
2240 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2257 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2274 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2287 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2289 u32 retry = 0;
2292 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2293 return -EBUSY;
2324 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2329 retry++;
2330 if (retry < max_retry)
2331 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2334 } while (retry < max_retry);
2337 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2343 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2360 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2377 * ixgbe_i2c_start - Sets I2C start condition
2380 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2381 * Set bit-bang mode on X550 hardware.
2409 * ixgbe_i2c_stop - Sets I2C stop condition
2412 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2413 * Disables bit-bang mode and negates data output enable on X550
2444 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2456 for (i = 7; i >= 0; i--) {
2465 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2478 for (i = 7; i >= 0; i--) {
2497 * ixgbe_get_i2c_ack - Polls for I2C ACK
2535 status = -EIO;
2547 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2581 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2607 return -EIO;
2613 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2617 * Raises the I2C clock line '0'->'1'
2646 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2650 * Lowers the I2C clock line '1'->'0'
2667 * ixgbe_set_i2c_data - Sets the I2C data bit
2688 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2702 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2703 return -EIO;
2710 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2734 * ixgbe_i2c_bus_clear - Clears the I2C bus
2769 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2781 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2785 status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2793 /** ixgbe_set_copper_phy_power - Control power for copper phy
2803 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2809 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2821 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);