Lines Matching full:hw
13 static int ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
14 static int ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
15 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
16 static int ixgbe_ready_eeprom(struct ixgbe_hw *hw);
17 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
18 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
20 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
21 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
22 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
23 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
25 static int ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
26 static int ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
27 static int ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
29 static int ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
31 static int ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
33 static int ixgbe_disable_pcie_primary(struct ixgbe_hw *hw);
43 * @hw: pointer to hardware structure
49 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) in ixgbe_device_supports_autoneg_fc() argument
55 switch (hw->phy.media_type) { in ixgbe_device_supports_autoneg_fc()
58 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
65 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_device_supports_autoneg_fc()
75 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) in ixgbe_device_supports_autoneg_fc()
82 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
105 hw_dbg(hw, "Device %x does not support flow control autoneg\n", in ixgbe_device_supports_autoneg_fc()
106 hw->device_id); in ixgbe_device_supports_autoneg_fc()
113 * @hw: pointer to hardware structure
117 int ixgbe_setup_fc_generic(struct ixgbe_hw *hw) in ixgbe_setup_fc_generic() argument
128 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { in ixgbe_setup_fc_generic()
129 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); in ixgbe_setup_fc_generic()
137 if (hw->fc.requested_mode == ixgbe_fc_default) in ixgbe_setup_fc_generic()
138 hw->fc.requested_mode = ixgbe_fc_full; in ixgbe_setup_fc_generic()
142 * HW will be able to do fc autoneg once the cable is plugged in. If in ixgbe_setup_fc_generic()
145 switch (hw->phy.media_type) { in ixgbe_setup_fc_generic()
148 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); in ixgbe_setup_fc_generic()
154 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_setup_fc_generic()
158 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc_generic()
175 switch (hw->fc.requested_mode) { in ixgbe_setup_fc_generic()
179 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
182 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
192 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
195 } else if (hw->phy.media_type == ixgbe_media_type_copper) { in ixgbe_setup_fc_generic()
213 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
216 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
220 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_setup_fc_generic()
224 if (hw->mac.type != ixgbe_mac_X540) { in ixgbe_setup_fc_generic()
229 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); in ixgbe_setup_fc_generic()
230 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); in ixgbe_setup_fc_generic()
233 if (hw->fc.strict_ieee) in ixgbe_setup_fc_generic()
236 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); in ixgbe_setup_fc_generic()
237 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); in ixgbe_setup_fc_generic()
245 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
250 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); in ixgbe_setup_fc_generic()
254 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && in ixgbe_setup_fc_generic()
255 ixgbe_device_supports_autoneg_fc(hw)) { in ixgbe_setup_fc_generic()
256 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc_generic()
260 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); in ixgbe_setup_fc_generic()
266 * @hw: pointer to hardware structure
273 int ixgbe_start_hw_generic(struct ixgbe_hw *hw) in ixgbe_start_hw_generic() argument
280 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
283 hw->phy.ops.identify(hw); in ixgbe_start_hw_generic()
286 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
289 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
292 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); in ixgbe_start_hw_generic()
294 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); in ixgbe_start_hw_generic()
295 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_generic()
298 if (hw->mac.ops.setup_fc) { in ixgbe_start_hw_generic()
299 ret_val = hw->mac.ops.setup_fc(hw); in ixgbe_start_hw_generic()
305 switch (hw->mac.type) { in ixgbe_start_hw_generic()
309 hw->mac.ops.get_device_caps(hw, &device_caps); in ixgbe_start_hw_generic()
311 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
313 hw->need_crosstalk_fix = true; in ixgbe_start_hw_generic()
316 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
321 hw->adapter_stopped = false; in ixgbe_start_hw_generic()
328 * @hw: pointer to hw structure
337 int ixgbe_start_hw_gen2(struct ixgbe_hw *hw) in ixgbe_start_hw_gen2() argument
342 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_start_hw_gen2()
343 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); in ixgbe_start_hw_gen2()
344 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); in ixgbe_start_hw_gen2()
346 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_gen2()
353 * @hw: pointer to hardware structure
361 int ixgbe_init_hw_generic(struct ixgbe_hw *hw) in ixgbe_init_hw_generic() argument
366 status = hw->mac.ops.reset_hw(hw); in ixgbe_init_hw_generic()
369 /* Start the HW */ in ixgbe_init_hw_generic()
370 status = hw->mac.ops.start_hw(hw); in ixgbe_init_hw_generic()
374 if (hw->mac.ops.init_led_link_act) in ixgbe_init_hw_generic()
375 hw->mac.ops.init_led_link_act(hw); in ixgbe_init_hw_generic()
382 * @hw: pointer to hardware structure
387 int ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) in ixgbe_clear_hw_cntrs_generic() argument
391 IXGBE_READ_REG(hw, IXGBE_CRCERRS); in ixgbe_clear_hw_cntrs_generic()
392 IXGBE_READ_REG(hw, IXGBE_ILLERRC); in ixgbe_clear_hw_cntrs_generic()
393 IXGBE_READ_REG(hw, IXGBE_ERRBC); in ixgbe_clear_hw_cntrs_generic()
394 IXGBE_READ_REG(hw, IXGBE_MSPDC); in ixgbe_clear_hw_cntrs_generic()
396 IXGBE_READ_REG(hw, IXGBE_MPC(i)); in ixgbe_clear_hw_cntrs_generic()
398 IXGBE_READ_REG(hw, IXGBE_MLFC); in ixgbe_clear_hw_cntrs_generic()
399 IXGBE_READ_REG(hw, IXGBE_MRFC); in ixgbe_clear_hw_cntrs_generic()
400 IXGBE_READ_REG(hw, IXGBE_RLEC); in ixgbe_clear_hw_cntrs_generic()
401 IXGBE_READ_REG(hw, IXGBE_LXONTXC); in ixgbe_clear_hw_cntrs_generic()
402 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); in ixgbe_clear_hw_cntrs_generic()
403 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
404 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); in ixgbe_clear_hw_cntrs_generic()
405 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); in ixgbe_clear_hw_cntrs_generic()
407 IXGBE_READ_REG(hw, IXGBE_LXONRXC); in ixgbe_clear_hw_cntrs_generic()
408 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); in ixgbe_clear_hw_cntrs_generic()
412 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); in ixgbe_clear_hw_cntrs_generic()
413 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); in ixgbe_clear_hw_cntrs_generic()
414 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
415 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
416 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
418 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); in ixgbe_clear_hw_cntrs_generic()
419 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); in ixgbe_clear_hw_cntrs_generic()
422 if (hw->mac.type >= ixgbe_mac_82599EB) in ixgbe_clear_hw_cntrs_generic()
424 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); in ixgbe_clear_hw_cntrs_generic()
425 IXGBE_READ_REG(hw, IXGBE_PRC64); in ixgbe_clear_hw_cntrs_generic()
426 IXGBE_READ_REG(hw, IXGBE_PRC127); in ixgbe_clear_hw_cntrs_generic()
427 IXGBE_READ_REG(hw, IXGBE_PRC255); in ixgbe_clear_hw_cntrs_generic()
428 IXGBE_READ_REG(hw, IXGBE_PRC511); in ixgbe_clear_hw_cntrs_generic()
429 IXGBE_READ_REG(hw, IXGBE_PRC1023); in ixgbe_clear_hw_cntrs_generic()
430 IXGBE_READ_REG(hw, IXGBE_PRC1522); in ixgbe_clear_hw_cntrs_generic()
431 IXGBE_READ_REG(hw, IXGBE_GPRC); in ixgbe_clear_hw_cntrs_generic()
432 IXGBE_READ_REG(hw, IXGBE_BPRC); in ixgbe_clear_hw_cntrs_generic()
433 IXGBE_READ_REG(hw, IXGBE_MPRC); in ixgbe_clear_hw_cntrs_generic()
434 IXGBE_READ_REG(hw, IXGBE_GPTC); in ixgbe_clear_hw_cntrs_generic()
435 IXGBE_READ_REG(hw, IXGBE_GORCL); in ixgbe_clear_hw_cntrs_generic()
436 IXGBE_READ_REG(hw, IXGBE_GORCH); in ixgbe_clear_hw_cntrs_generic()
437 IXGBE_READ_REG(hw, IXGBE_GOTCL); in ixgbe_clear_hw_cntrs_generic()
438 IXGBE_READ_REG(hw, IXGBE_GOTCH); in ixgbe_clear_hw_cntrs_generic()
439 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_clear_hw_cntrs_generic()
441 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); in ixgbe_clear_hw_cntrs_generic()
442 IXGBE_READ_REG(hw, IXGBE_RUC); in ixgbe_clear_hw_cntrs_generic()
443 IXGBE_READ_REG(hw, IXGBE_RFC); in ixgbe_clear_hw_cntrs_generic()
444 IXGBE_READ_REG(hw, IXGBE_ROC); in ixgbe_clear_hw_cntrs_generic()
445 IXGBE_READ_REG(hw, IXGBE_RJC); in ixgbe_clear_hw_cntrs_generic()
446 IXGBE_READ_REG(hw, IXGBE_MNGPRC); in ixgbe_clear_hw_cntrs_generic()
447 IXGBE_READ_REG(hw, IXGBE_MNGPDC); in ixgbe_clear_hw_cntrs_generic()
448 IXGBE_READ_REG(hw, IXGBE_MNGPTC); in ixgbe_clear_hw_cntrs_generic()
449 IXGBE_READ_REG(hw, IXGBE_TORL); in ixgbe_clear_hw_cntrs_generic()
450 IXGBE_READ_REG(hw, IXGBE_TORH); in ixgbe_clear_hw_cntrs_generic()
451 IXGBE_READ_REG(hw, IXGBE_TPR); in ixgbe_clear_hw_cntrs_generic()
452 IXGBE_READ_REG(hw, IXGBE_TPT); in ixgbe_clear_hw_cntrs_generic()
453 IXGBE_READ_REG(hw, IXGBE_PTC64); in ixgbe_clear_hw_cntrs_generic()
454 IXGBE_READ_REG(hw, IXGBE_PTC127); in ixgbe_clear_hw_cntrs_generic()
455 IXGBE_READ_REG(hw, IXGBE_PTC255); in ixgbe_clear_hw_cntrs_generic()
456 IXGBE_READ_REG(hw, IXGBE_PTC511); in ixgbe_clear_hw_cntrs_generic()
457 IXGBE_READ_REG(hw, IXGBE_PTC1023); in ixgbe_clear_hw_cntrs_generic()
458 IXGBE_READ_REG(hw, IXGBE_PTC1522); in ixgbe_clear_hw_cntrs_generic()
459 IXGBE_READ_REG(hw, IXGBE_MPTC); in ixgbe_clear_hw_cntrs_generic()
460 IXGBE_READ_REG(hw, IXGBE_BPTC); in ixgbe_clear_hw_cntrs_generic()
462 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); in ixgbe_clear_hw_cntrs_generic()
463 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); in ixgbe_clear_hw_cntrs_generic()
464 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
465 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); in ixgbe_clear_hw_cntrs_generic()
466 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); in ixgbe_clear_hw_cntrs_generic()
467 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); in ixgbe_clear_hw_cntrs_generic()
468 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); in ixgbe_clear_hw_cntrs_generic()
469 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); in ixgbe_clear_hw_cntrs_generic()
471 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); in ixgbe_clear_hw_cntrs_generic()
472 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); in ixgbe_clear_hw_cntrs_generic()
476 if (hw->mac.type == ixgbe_mac_X550 || in ixgbe_clear_hw_cntrs_generic()
477 hw->mac.type == ixgbe_mac_X540 || in ixgbe_clear_hw_cntrs_generic()
478 hw->mac.type == ixgbe_mac_e610) { in ixgbe_clear_hw_cntrs_generic()
479 if (hw->phy.id == 0) in ixgbe_clear_hw_cntrs_generic()
480 hw->phy.ops.identify(hw); in ixgbe_clear_hw_cntrs_generic()
483 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { in ixgbe_clear_hw_cntrs_generic()
484 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
485 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
486 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
487 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
495 * @hw: pointer to hardware structure
501 int ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, in ixgbe_read_pba_string_generic() argument
511 hw_dbg(hw, "PBA string buffer was null\n"); in ixgbe_read_pba_string_generic()
515 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); in ixgbe_read_pba_string_generic()
517 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
521 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); in ixgbe_read_pba_string_generic()
523 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
533 hw_dbg(hw, "NVM PBA number is not stored as string\n"); in ixgbe_read_pba_string_generic()
537 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
567 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); in ixgbe_read_pba_string_generic()
569 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
574 hw_dbg(hw, "NVM PBA number section invalid length\n"); in ixgbe_read_pba_string_generic()
580 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
589 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); in ixgbe_read_pba_string_generic()
591 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
604 * @hw: pointer to hardware structure
611 int ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) in ixgbe_get_mac_addr_generic() argument
617 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); in ixgbe_get_mac_addr_generic()
618 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); in ixgbe_get_mac_addr_generic()
661 * @hw: pointer to hardware structure
665 int ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) in ixgbe_get_bus_info_generic() argument
669 hw->bus.type = ixgbe_bus_type_pci_express; in ixgbe_get_bus_info_generic()
672 if (hw->mac.type == ixgbe_mac_e610) in ixgbe_get_bus_info_generic()
673 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS_E610); in ixgbe_get_bus_info_generic()
675 link_status = ixgbe_read_pci_cfg_word(hw, in ixgbe_get_bus_info_generic()
678 hw->bus.width = ixgbe_convert_bus_width(link_status); in ixgbe_get_bus_info_generic()
679 hw->bus.speed = ixgbe_convert_bus_speed(link_status); in ixgbe_get_bus_info_generic()
681 hw->mac.ops.set_lan_id(hw); in ixgbe_get_bus_info_generic()
688 * @hw: pointer to the HW structure
693 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) in ixgbe_set_lan_id_multi_port_pcie() argument
695 struct ixgbe_bus_info *bus = &hw->bus; in ixgbe_set_lan_id_multi_port_pcie()
699 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); in ixgbe_set_lan_id_multi_port_pcie()
704 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); in ixgbe_set_lan_id_multi_port_pcie()
709 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { in ixgbe_set_lan_id_multi_port_pcie()
710 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); in ixgbe_set_lan_id_multi_port_pcie()
718 * @hw: pointer to hardware structure
725 int ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) in ixgbe_stop_adapter_generic() argument
734 hw->adapter_stopped = true; in ixgbe_stop_adapter_generic()
737 hw->mac.ops.disable_rx(hw); in ixgbe_stop_adapter_generic()
740 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); in ixgbe_stop_adapter_generic()
743 IXGBE_READ_REG(hw, IXGBE_EICR); in ixgbe_stop_adapter_generic()
746 for (i = 0; i < hw->mac.max_tx_queues; i++) in ixgbe_stop_adapter_generic()
747 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); in ixgbe_stop_adapter_generic()
750 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_stop_adapter_generic()
751 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); in ixgbe_stop_adapter_generic()
754 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); in ixgbe_stop_adapter_generic()
758 IXGBE_WRITE_FLUSH(hw); in ixgbe_stop_adapter_generic()
765 return ixgbe_disable_pcie_primary(hw); in ixgbe_stop_adapter_generic()
770 * @hw: pointer to hardware structure
775 int ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) in ixgbe_init_led_link_act_generic() argument
777 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_led_link_act_generic()
781 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_init_led_link_act_generic()
797 switch (hw->mac.type) { in ixgbe_init_led_link_act_generic()
813 * @hw: pointer to hardware structure
816 int ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_on_generic() argument
818 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_on_generic()
826 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_on_generic()
827 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_on_generic()
834 * @hw: pointer to hardware structure
837 int ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_off_generic() argument
839 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_off_generic()
847 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_off_generic()
848 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_off_generic()
855 * @hw: pointer to hardware structure
860 int ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) in ixgbe_init_eeprom_params_generic() argument
862 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_eeprom_params_generic()
878 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_init_eeprom_params_generic()
895 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", in ixgbe_init_eeprom_params_generic()
904 * @hw: pointer to hardware structure
911 int ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang_generic() argument
917 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_buffer_bit_bang_generic()
919 if (words == 0 || (offset + words > hw->eeprom.word_size)) in ixgbe_write_eeprom_buffer_bit_bang_generic()
926 if ((hw->eeprom.word_page_size == 0) && in ixgbe_write_eeprom_buffer_bit_bang_generic()
928 ixgbe_detect_eeprom_page_size_generic(hw, offset); in ixgbe_write_eeprom_buffer_bit_bang_generic()
938 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_write_eeprom_buffer_bit_bang_generic()
950 * @hw: pointer to hardware structure
958 static int ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang() argument
968 status = ixgbe_acquire_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
972 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_write_eeprom_buffer_bit_bang()
973 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
978 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
981 ixgbe_shift_out_eeprom_bits(hw, in ixgbe_write_eeprom_buffer_bit_bang()
985 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
990 if ((hw->eeprom.address_bits == 8) && in ixgbe_write_eeprom_buffer_bit_bang()
995 ixgbe_shift_out_eeprom_bits(hw, write_opcode, in ixgbe_write_eeprom_buffer_bit_bang()
997 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_write_eeprom_buffer_bit_bang()
998 hw->eeprom.address_bits); in ixgbe_write_eeprom_buffer_bit_bang()
1000 page_size = hw->eeprom.word_page_size; in ixgbe_write_eeprom_buffer_bit_bang()
1006 ixgbe_shift_out_eeprom_bits(hw, word, 16); in ixgbe_write_eeprom_buffer_bit_bang()
1017 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1021 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1028 * @hw: pointer to hardware structure
1035 int ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eeprom_generic() argument
1037 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_generic()
1039 if (offset >= hw->eeprom.word_size) in ixgbe_write_eeprom_generic()
1042 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); in ixgbe_write_eeprom_generic()
1047 * @hw: pointer to hardware structure
1054 int ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang_generic() argument
1060 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_buffer_bit_bang_generic()
1062 if (words == 0 || (offset + words > hw->eeprom.word_size)) in ixgbe_read_eeprom_buffer_bit_bang_generic()
1074 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_read_eeprom_buffer_bit_bang_generic()
1086 * @hw: pointer to hardware structure
1093 static int ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang() argument
1102 status = ixgbe_acquire_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1106 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_read_eeprom_buffer_bit_bang()
1107 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1112 ixgbe_standby_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1116 if ((hw->eeprom.address_bits == 8) && in ixgbe_read_eeprom_buffer_bit_bang()
1121 ixgbe_shift_out_eeprom_bits(hw, read_opcode, in ixgbe_read_eeprom_buffer_bit_bang()
1123 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_read_eeprom_buffer_bit_bang()
1124 hw->eeprom.address_bits); in ixgbe_read_eeprom_buffer_bit_bang()
1127 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); in ixgbe_read_eeprom_buffer_bit_bang()
1132 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1139 * @hw: pointer to hardware structure
1145 int ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_bit_bang_generic() argument
1148 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_bit_bang_generic()
1150 if (offset >= hw->eeprom.word_size) in ixgbe_read_eeprom_bit_bang_generic()
1153 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_read_eeprom_bit_bang_generic()
1158 * @hw: pointer to hardware structure
1165 int ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eerd_buffer_generic() argument
1172 hw->eeprom.ops.init_params(hw); in ixgbe_read_eerd_buffer_generic()
1174 if (words == 0 || offset >= hw->eeprom.word_size) in ixgbe_read_eerd_buffer_generic()
1181 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); in ixgbe_read_eerd_buffer_generic()
1182 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); in ixgbe_read_eerd_buffer_generic()
1185 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> in ixgbe_read_eerd_buffer_generic()
1188 hw_dbg(hw, "Eeprom read timed out\n"); in ixgbe_read_eerd_buffer_generic()
1198 * @hw: pointer to hardware structure
1205 static int ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, in ixgbe_detect_eeprom_page_size_generic() argument
1215 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; in ixgbe_detect_eeprom_page_size_generic()
1216 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, in ixgbe_detect_eeprom_page_size_generic()
1218 hw->eeprom.word_page_size = 0; in ixgbe_detect_eeprom_page_size_generic()
1222 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_detect_eeprom_page_size_generic()
1230 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; in ixgbe_detect_eeprom_page_size_generic()
1232 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", in ixgbe_detect_eeprom_page_size_generic()
1233 hw->eeprom.word_page_size); in ixgbe_detect_eeprom_page_size_generic()
1239 * @hw: pointer to hardware structure
1245 int ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) in ixgbe_read_eerd_generic() argument
1247 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); in ixgbe_read_eerd_generic()
1252 * @hw: pointer to hardware structure
1259 int ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eewr_buffer_generic() argument
1266 hw->eeprom.ops.init_params(hw); in ixgbe_write_eewr_buffer_generic()
1268 if (words == 0 || offset >= hw->eeprom.word_size) in ixgbe_write_eewr_buffer_generic()
1276 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1278 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1282 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); in ixgbe_write_eewr_buffer_generic()
1284 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1286 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1296 * @hw: pointer to hardware structure
1302 int ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eewr_generic() argument
1304 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); in ixgbe_write_eewr_generic()
1309 * @hw: pointer to hardware structure
1315 static int ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) in ixgbe_poll_eerd_eewr_done() argument
1322 reg = IXGBE_READ_REG(hw, IXGBE_EERD); in ixgbe_poll_eerd_eewr_done()
1324 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); in ixgbe_poll_eerd_eewr_done()
1336 * @hw: pointer to hardware structure
1341 static int ixgbe_acquire_eeprom(struct ixgbe_hw *hw) in ixgbe_acquire_eeprom() argument
1346 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) in ixgbe_acquire_eeprom()
1349 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1353 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1356 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1365 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1366 hw_dbg(hw, "Could not acquire EEPROM grant\n"); in ixgbe_acquire_eeprom()
1368 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_acquire_eeprom()
1375 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1376 IXGBE_WRITE_FLUSH(hw); in ixgbe_acquire_eeprom()
1383 * @hw: pointer to hardware structure
1387 static int ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_get_eeprom_semaphore() argument
1399 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1406 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1412 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1419 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1421 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); in ixgbe_get_eeprom_semaphore()
1428 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1432 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_get_eeprom_semaphore()
1437 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1448 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1449 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1458 * @hw: pointer to hardware structure
1462 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_release_eeprom_semaphore() argument
1466 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_release_eeprom_semaphore()
1470 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_release_eeprom_semaphore()
1471 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom_semaphore()
1476 * @hw: pointer to hardware structure
1478 static int ixgbe_ready_eeprom(struct ixgbe_hw *hw) in ixgbe_ready_eeprom() argument
1490 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, in ixgbe_ready_eeprom()
1492 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); in ixgbe_ready_eeprom()
1497 ixgbe_standby_eeprom(hw); in ixgbe_ready_eeprom()
1505 hw_dbg(hw, "SPI EEPROM Status error\n"); in ixgbe_ready_eeprom()
1514 * @hw: pointer to hardware structure
1516 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) in ixgbe_standby_eeprom() argument
1520 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_standby_eeprom()
1524 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1525 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1528 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1529 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1535 * @hw: pointer to hardware structure
1539 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, in ixgbe_shift_out_eeprom_bits() argument
1546 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_out_eeprom_bits()
1567 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1568 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1572 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1573 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1584 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1585 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1590 * @hw: pointer to hardware structure
1593 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) in ixgbe_shift_in_eeprom_bits() argument
1606 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1612 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1614 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1620 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1628 * @hw: pointer to hardware structure
1631 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_raise_eeprom_clk() argument
1638 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_raise_eeprom_clk()
1639 IXGBE_WRITE_FLUSH(hw); in ixgbe_raise_eeprom_clk()
1645 * @hw: pointer to hardware structure
1648 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_lower_eeprom_clk() argument
1655 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_lower_eeprom_clk()
1656 IXGBE_WRITE_FLUSH(hw); in ixgbe_lower_eeprom_clk()
1662 * @hw: pointer to hardware structure
1664 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) in ixgbe_release_eeprom() argument
1668 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_release_eeprom()
1673 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1674 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom()
1680 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1682 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_release_eeprom()
1688 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_release_eeprom()
1689 hw->eeprom.semaphore_delay * 2000); in ixgbe_release_eeprom()
1694 * @hw: pointer to hardware structure
1696 int ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_calc_eeprom_checksum_generic() argument
1707 if (hw->eeprom.ops.read(hw, i, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1708 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1716 if (hw->eeprom.ops.read(hw, i, &pointer)) { in ixgbe_calc_eeprom_checksum_generic()
1717 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1725 if (hw->eeprom.ops.read(hw, pointer, &length)) { in ixgbe_calc_eeprom_checksum_generic()
1726 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1734 if (hw->eeprom.ops.read(hw, j, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1735 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1749 * @hw: pointer to hardware structure
1755 int ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, in ixgbe_validate_eeprom_checksum_generic() argument
1767 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_validate_eeprom_checksum_generic()
1769 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1773 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_validate_eeprom_checksum_generic()
1779 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); in ixgbe_validate_eeprom_checksum_generic()
1781 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1800 * @hw: pointer to hardware structure
1802 int ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_update_eeprom_checksum_generic() argument
1812 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_update_eeprom_checksum_generic()
1814 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_update_eeprom_checksum_generic()
1818 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_update_eeprom_checksum_generic()
1824 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); in ixgbe_update_eeprom_checksum_generic()
1831 * @hw: pointer to hardware structure
1839 int ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ixgbe_set_rar_generic() argument
1843 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_rar_generic()
1847 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_set_rar_generic()
1852 hw->mac.ops.set_vmdq(hw, index, vmdq); in ixgbe_set_rar_generic()
1855 * HW expects these in little endian so we reverse the byte in ixgbe_set_rar_generic()
1867 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_set_rar_generic()
1878 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); in ixgbe_set_rar_generic()
1879 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_rar_generic()
1880 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_set_rar_generic()
1887 * @hw: pointer to hardware structure
1892 int ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_clear_rar_generic() argument
1895 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_rar_generic()
1899 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_clear_rar_generic()
1908 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_clear_rar_generic()
1915 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_clear_rar_generic()
1916 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_rar_generic()
1917 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); in ixgbe_clear_rar_generic()
1920 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_clear_rar_generic()
1927 * @hw: pointer to hardware structure
1933 int ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) in ixgbe_init_rx_addrs_generic() argument
1936 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_init_rx_addrs_generic()
1943 if (!is_valid_ether_addr(hw->mac.addr)) { in ixgbe_init_rx_addrs_generic()
1945 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1947 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1950 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); in ixgbe_init_rx_addrs_generic()
1951 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1953 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); in ixgbe_init_rx_addrs_generic()
1957 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_init_rx_addrs_generic()
1959 hw->addr_ctrl.overflow_promisc = 0; in ixgbe_init_rx_addrs_generic()
1961 hw->addr_ctrl.rar_used_count = 1; in ixgbe_init_rx_addrs_generic()
1964 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); in ixgbe_init_rx_addrs_generic()
1966 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); in ixgbe_init_rx_addrs_generic()
1967 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); in ixgbe_init_rx_addrs_generic()
1971 hw->addr_ctrl.mta_in_use = 0; in ixgbe_init_rx_addrs_generic()
1972 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_init_rx_addrs_generic()
1974 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_init_rx_addrs_generic()
1975 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_init_rx_addrs_generic()
1976 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); in ixgbe_init_rx_addrs_generic()
1978 if (hw->mac.ops.init_uta_tables) in ixgbe_init_rx_addrs_generic()
1979 hw->mac.ops.init_uta_tables(hw); in ixgbe_init_rx_addrs_generic()
1986 * @hw: pointer to hardware structure
1996 static int ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_mta_vector() argument
2000 switch (hw->mac.mc_filter_type) { in ixgbe_mta_vector()
2014 hw_dbg(hw, "MC filter type param set incorrectly\n"); in ixgbe_mta_vector()
2025 * @hw: pointer to hardware structure
2030 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_set_mta() argument
2036 hw->addr_ctrl.mta_in_use++; in ixgbe_set_mta()
2038 vector = ixgbe_mta_vector(hw, mc_addr); in ixgbe_set_mta()
2039 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); in ixgbe_set_mta()
2052 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); in ixgbe_set_mta()
2057 * @hw: pointer to hardware structure
2065 int ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, in ixgbe_update_mc_addr_list_generic() argument
2075 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); in ixgbe_update_mc_addr_list_generic()
2076 hw->addr_ctrl.mta_in_use = 0; in ixgbe_update_mc_addr_list_generic()
2079 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_update_mc_addr_list_generic()
2080 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in ixgbe_update_mc_addr_list_generic()
2084 hw_dbg(hw, " Adding the multicast addresses:\n"); in ixgbe_update_mc_addr_list_generic()
2085 ixgbe_set_mta(hw, ha->addr); in ixgbe_update_mc_addr_list_generic()
2089 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_update_mc_addr_list_generic()
2090 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, in ixgbe_update_mc_addr_list_generic()
2091 hw->mac.mta_shadow[i]); in ixgbe_update_mc_addr_list_generic()
2093 if (hw->addr_ctrl.mta_in_use > 0) in ixgbe_update_mc_addr_list_generic()
2094 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, in ixgbe_update_mc_addr_list_generic()
2095 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); in ixgbe_update_mc_addr_list_generic()
2097 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); in ixgbe_update_mc_addr_list_generic()
2103 * @hw: pointer to hardware structure
2107 int ixgbe_enable_mc_generic(struct ixgbe_hw *hw) in ixgbe_enable_mc_generic() argument
2109 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_enable_mc_generic()
2112 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | in ixgbe_enable_mc_generic()
2113 hw->mac.mc_filter_type); in ixgbe_enable_mc_generic()
2120 * @hw: pointer to hardware structure
2124 int ixgbe_disable_mc_generic(struct ixgbe_hw *hw) in ixgbe_disable_mc_generic() argument
2126 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_disable_mc_generic()
2129 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_disable_mc_generic()
2136 * @hw: pointer to hardware structure
2140 int ixgbe_fc_enable_generic(struct ixgbe_hw *hw) in ixgbe_fc_enable_generic() argument
2148 if (!hw->fc.pause_time) in ixgbe_fc_enable_generic()
2153 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2154 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2155 if (!hw->fc.low_water[i] || in ixgbe_fc_enable_generic()
2156 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2157 hw_dbg(hw, "Invalid water mark configuration\n"); in ixgbe_fc_enable_generic()
2164 hw->mac.ops.fc_autoneg(hw); in ixgbe_fc_enable_generic()
2167 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); in ixgbe_fc_enable_generic()
2170 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); in ixgbe_fc_enable_generic()
2183 switch (hw->fc.current_mode) { in ixgbe_fc_enable_generic()
2187 * The code below will actually disable it in the HW. in ixgbe_fc_enable_generic()
2214 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_fc_enable_generic()
2220 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); in ixgbe_fc_enable_generic()
2221 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); in ixgbe_fc_enable_generic()
2225 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2226 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2227 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_fc_enable_generic()
2228 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); in ixgbe_fc_enable_generic()
2229 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_generic()
2231 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); in ixgbe_fc_enable_generic()
2239 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; in ixgbe_fc_enable_generic()
2242 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); in ixgbe_fc_enable_generic()
2246 reg = hw->fc.pause_time * 0x00010001U; in ixgbe_fc_enable_generic()
2248 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_fc_enable_generic()
2250 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); in ixgbe_fc_enable_generic()
2257 * @hw: pointer to hardware structure
2268 int ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, in ixgbe_negotiate_fc() argument
2282 if (hw->fc.requested_mode == ixgbe_fc_full) { in ixgbe_negotiate_fc()
2283 hw->fc.current_mode = ixgbe_fc_full; in ixgbe_negotiate_fc()
2284 hw_dbg(hw, "Flow Control = FULL.\n"); in ixgbe_negotiate_fc()
2286 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2287 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); in ixgbe_negotiate_fc()
2291 hw->fc.current_mode = ixgbe_fc_tx_pause; in ixgbe_negotiate_fc()
2292 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2295 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2296 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2298 hw->fc.current_mode = ixgbe_fc_none; in ixgbe_negotiate_fc()
2299 hw_dbg(hw, "Flow Control = NONE.\n"); in ixgbe_negotiate_fc()
2306 * @hw: pointer to hardware structure
2310 static int ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_fiber() argument
2321 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); in ixgbe_fc_autoneg_fiber()
2326 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_fc_autoneg_fiber()
2327 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); in ixgbe_fc_autoneg_fiber()
2329 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, in ixgbe_fc_autoneg_fiber()
2340 * @hw: pointer to hardware structure
2344 static int ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_backplane() argument
2354 links = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_fc_autoneg_backplane()
2358 if (hw->mac.type == ixgbe_mac_82599EB) { in ixgbe_fc_autoneg_backplane()
2359 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); in ixgbe_fc_autoneg_backplane()
2367 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_fc_autoneg_backplane()
2368 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); in ixgbe_fc_autoneg_backplane()
2370 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, in ixgbe_fc_autoneg_backplane()
2379 * @hw: pointer to hardware structure
2383 static int ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_copper() argument
2388 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_fc_autoneg_copper()
2391 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, in ixgbe_fc_autoneg_copper()
2395 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, in ixgbe_fc_autoneg_copper()
2403 * @hw: pointer to hardware structure
2408 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) in ixgbe_fc_autoneg() argument
2423 if (hw->fc.disable_fc_autoneg) in ixgbe_fc_autoneg()
2426 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_fc_autoneg()
2430 switch (hw->phy.media_type) { in ixgbe_fc_autoneg()
2434 ret_val = ixgbe_fc_autoneg_fiber(hw); in ixgbe_fc_autoneg()
2439 ret_val = ixgbe_fc_autoneg_backplane(hw); in ixgbe_fc_autoneg()
2444 if (ixgbe_device_supports_autoneg_fc(hw)) in ixgbe_fc_autoneg()
2445 ret_val = ixgbe_fc_autoneg_copper(hw); in ixgbe_fc_autoneg()
2454 hw->fc.fc_was_autonegged = true; in ixgbe_fc_autoneg()
2456 hw->fc.fc_was_autonegged = false; in ixgbe_fc_autoneg()
2457 hw->fc.current_mode = hw->fc.requested_mode; in ixgbe_fc_autoneg()
2463 * @hw: pointer to hardware structure
2471 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) in ixgbe_pcie_timeout_poll() argument
2476 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); in ixgbe_pcie_timeout_poll()
2510 * @hw: pointer to hardware structure
2517 static int ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) in ixgbe_disable_pcie_primary() argument
2523 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); in ixgbe_disable_pcie_primary()
2527 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) in ixgbe_disable_pcie_primary()
2532 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); in ixgbe_disable_pcie_primary()
2537 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || in ixgbe_disable_pcie_primary()
2538 ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_primary()
2544 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) in ixgbe_disable_pcie_primary()
2556 hw_dbg(hw, "GIO Primary Disable bit didn't clear - requesting resets\n"); in ixgbe_disable_pcie_primary()
2558 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_disable_pcie_primary()
2560 if (hw->mac.type >= ixgbe_mac_X550) in ixgbe_disable_pcie_primary()
2567 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_disable_pcie_primary()
2570 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_disable_pcie_primary()
2571 if (ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_primary()
2577 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); in ixgbe_disable_pcie_primary()
2583 * @hw: pointer to hardware structure
2589 int ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_acquire_swfw_sync() argument
2602 if (ixgbe_get_eeprom_semaphore(hw)) in ixgbe_acquire_swfw_sync()
2605 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_acquire_swfw_sync()
2608 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_acquire_swfw_sync()
2609 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2613 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2620 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); in ixgbe_acquire_swfw_sync()
2628 * @hw: pointer to hardware structure
2634 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_release_swfw_sync() argument
2639 ixgbe_get_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2641 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_release_swfw_sync()
2643 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_release_swfw_sync()
2645 ixgbe_release_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2650 * @hw: pointer to hardware structure
2657 int prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) in prot_autoc_read_generic() argument
2660 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); in prot_autoc_read_generic()
2666 * @hw: pointer to hardware structure
2671 int prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) in prot_autoc_write_generic() argument
2673 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); in prot_autoc_write_generic()
2679 * @hw: pointer to hardware structure
2681 * Stops the receive data path and waits for the HW to internally
2684 int ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_buff_generic() argument
2690 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_disable_rx_buff_generic()
2692 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_disable_rx_buff_generic()
2694 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); in ixgbe_disable_rx_buff_generic()
2704 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); in ixgbe_disable_rx_buff_generic()
2712 * @hw: pointer to hardware structure
2716 int ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_buff_generic() argument
2720 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_enable_rx_buff_generic()
2722 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_enable_rx_buff_generic()
2723 IXGBE_WRITE_FLUSH(hw); in ixgbe_enable_rx_buff_generic()
2730 * @hw: pointer to hardware structure
2735 int ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_generic() argument
2738 hw->mac.ops.enable_rx(hw); in ixgbe_enable_rx_dma_generic()
2740 hw->mac.ops.disable_rx(hw); in ixgbe_enable_rx_dma_generic()
2747 * @hw: pointer to hardware structure
2750 int ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_start_generic() argument
2752 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_blink_led_start_generic()
2753 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_start_generic()
2766 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_blink_led_start_generic()
2769 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_start_generic()
2776 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_start_generic()
2780 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2787 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_start_generic()
2788 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2795 * @hw: pointer to hardware structure
2798 int ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_stop_generic() argument
2800 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_stop_generic()
2808 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_stop_generic()
2815 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_stop_generic()
2822 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_stop_generic()
2823 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_stop_generic()
2830 * @hw: pointer to hardware structure
2837 static int ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, in ixgbe_get_san_mac_addr_offset() argument
2846 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, in ixgbe_get_san_mac_addr_offset()
2849 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_offset()
2857 * @hw: pointer to hardware structure
2865 int ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) in ixgbe_get_san_mac_addr_generic() argument
2875 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); in ixgbe_get_san_mac_addr_generic()
2881 hw->mac.ops.set_lan_id(hw); in ixgbe_get_san_mac_addr_generic()
2883 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : in ixgbe_get_san_mac_addr_generic()
2886 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, in ixgbe_get_san_mac_addr_generic()
2889 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_generic()
2910 * @hw: pointer to hardware structure
2915 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) in ixgbe_get_pcie_msix_count_generic() argument
2921 switch (hw->mac.type) { in ixgbe_get_pcie_msix_count_generic()
2942 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); in ixgbe_get_pcie_msix_count_generic()
2943 if (ixgbe_removed(hw->hw_addr)) in ixgbe_get_pcie_msix_count_generic()
2947 /* MSI-X count is zero-based in HW */ in ixgbe_get_pcie_msix_count_generic()
2958 * @hw: pointer to hardware struct
2962 int ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_clear_vmdq_generic() argument
2965 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_vmdq_generic()
2969 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_clear_vmdq_generic()
2973 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_clear_vmdq_generic()
2974 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_clear_vmdq_generic()
2976 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_vmdq_generic()
2984 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_clear_vmdq_generic()
2988 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_clear_vmdq_generic()
2993 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); in ixgbe_clear_vmdq_generic()
2996 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); in ixgbe_clear_vmdq_generic()
3001 rar != 0 && rar != hw->mac.san_mac_rar_index) in ixgbe_clear_vmdq_generic()
3002 hw->mac.ops.clear_rar(hw, rar); in ixgbe_clear_vmdq_generic()
3009 * @hw: pointer to hardware struct
3013 int ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_set_vmdq_generic() argument
3016 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_vmdq_generic()
3020 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_set_vmdq_generic()
3025 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_set_vmdq_generic()
3027 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); in ixgbe_set_vmdq_generic()
3029 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_set_vmdq_generic()
3031 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); in ixgbe_set_vmdq_generic()
3038 * @hw: pointer to hardware struct
3044 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3046 int ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) in ixgbe_set_vmdq_san_mac_generic() argument
3048 u32 rar = hw->mac.san_mac_rar_index; in ixgbe_set_vmdq_san_mac_generic()
3051 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); in ixgbe_set_vmdq_san_mac_generic()
3052 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3054 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3055 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); in ixgbe_set_vmdq_san_mac_generic()
3063 * @hw: pointer to hardware structure
3065 int ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) in ixgbe_init_uta_tables_generic() argument
3070 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); in ixgbe_init_uta_tables_generic()
3077 * @hw: pointer to hardware structure
3085 static int ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) in ixgbe_find_vlvf_slot() argument
3109 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); in ixgbe_find_vlvf_slot()
3120 hw_dbg(hw, "No space in VLVF.\n"); in ixgbe_find_vlvf_slot()
3127 * @hw: pointer to hardware structure
3135 int ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, in ixgbe_set_vfta_generic() argument
3158 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); in ixgbe_set_vfta_generic()
3175 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) in ixgbe_set_vfta_generic()
3178 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); in ixgbe_set_vfta_generic()
3185 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); in ixgbe_set_vfta_generic()
3196 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { in ixgbe_set_vfta_generic()
3202 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
3205 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); in ixgbe_set_vfta_generic()
3206 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); in ixgbe_set_vfta_generic()
3229 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); in ixgbe_set_vfta_generic()
3230 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); in ixgbe_set_vfta_generic()
3235 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
3242 * @hw: pointer to hardware structure
3246 int ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) in ixgbe_clear_vfta_generic() argument
3250 for (offset = 0; offset < hw->mac.vft_size; offset++) in ixgbe_clear_vfta_generic()
3251 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); in ixgbe_clear_vfta_generic()
3254 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); in ixgbe_clear_vfta_generic()
3255 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); in ixgbe_clear_vfta_generic()
3256 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); in ixgbe_clear_vfta_generic()
3264 * @hw: pointer to hardware structure
3269 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) in ixgbe_need_crosstalk_fix() argument
3272 if (!hw->need_crosstalk_fix) in ixgbe_need_crosstalk_fix()
3276 switch (hw->mac.ops.get_media_type(hw)) { in ixgbe_need_crosstalk_fix()
3289 * @hw: pointer to hardware structure
3296 int ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, in ixgbe_check_mac_link_generic() argument
3299 bool crosstalk_fix_active = ixgbe_need_crosstalk_fix(hw); in ixgbe_check_mac_link_generic()
3309 switch (hw->mac.type) { in ixgbe_check_mac_link_generic()
3311 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
3316 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
3333 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3335 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3338 hw_dbg(hw, "LINKS changed from %08X to %08X\n", in ixgbe_check_mac_link_generic()
3351 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3361 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3376 if ((hw->mac.type >= ixgbe_mac_X550) && in ixgbe_check_mac_link_generic()
3386 if ((hw->mac.type >= ixgbe_mac_X550 || in ixgbe_check_mac_link_generic()
3387 hw->mac.type == ixgbe_mac_e610) && in ixgbe_check_mac_link_generic()
3395 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || in ixgbe_check_mac_link_generic()
3396 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { in ixgbe_check_mac_link_generic()
3410 * @hw: pointer to hardware structure
3417 int ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, in ixgbe_get_wwn_prefix_generic() argument
3429 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) in ixgbe_get_wwn_prefix_generic()
3438 if (hw->eeprom.ops.read(hw, offset, &caps)) in ixgbe_get_wwn_prefix_generic()
3445 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) in ixgbe_get_wwn_prefix_generic()
3446 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3449 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) in ixgbe_get_wwn_prefix_generic()
3455 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3461 * @hw: pointer to hardware structure
3466 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_mac_anti_spoofing() argument
3472 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_mac_anti_spoofing()
3475 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_mac_anti_spoofing()
3480 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_mac_anti_spoofing()
3485 * @hw: pointer to hardware structure
3490 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_vlan_anti_spoofing() argument
3496 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_vlan_anti_spoofing()
3499 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_vlan_anti_spoofing()
3504 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_vlan_anti_spoofing()
3509 * @hw: pointer to hardware structure
3515 int ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) in ixgbe_get_device_caps_generic() argument
3517 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); in ixgbe_get_device_caps_generic()
3524 * @hw: pointer to hardware structure
3529 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, in ixgbe_set_rxpba_generic() argument
3534 u32 pbsize = hw->mac.rx_pb_size; in ixgbe_set_rxpba_generic()
3556 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3562 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3576 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); in ixgbe_set_rxpba_generic()
3577 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); in ixgbe_set_rxpba_generic()
3582 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3583 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3584 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); in ixgbe_set_rxpba_generic()
3612 * @hw: pointer to the HW structure
3625 int ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, in ixgbe_hic_unlocked() argument
3632 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_hic_unlocked()
3637 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); in ixgbe_hic_unlocked()
3638 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); in ixgbe_hic_unlocked()
3641 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
3643 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); in ixgbe_hic_unlocked()
3649 hw_dbg(hw, "Buffer length failure, not aligned to dword"); in ixgbe_hic_unlocked()
3659 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, in ixgbe_hic_unlocked()
3663 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); in ixgbe_hic_unlocked()
3666 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
3674 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) in ixgbe_hic_unlocked()
3682 * @hw: pointer to the HW structure
3697 int ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, in ixgbe_host_interface_command() argument
3709 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_host_interface_command()
3713 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
3717 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); in ixgbe_host_interface_command()
3729 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3739 hw_dbg(hw, "Buffer not large enough for reply message.\n"); in ixgbe_host_interface_command()
3749 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3754 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
3761 * @hw: pointer to the HW structure
3774 int ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, in ixgbe_set_fw_drv_ver_generic() argument
3785 fw_cmd.port_num = hw->bus.func; in ixgbe_set_fw_drv_ver_generic()
3797 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, in ixgbe_set_fw_drv_ver_generic()
3818 * @hw: pointer to the hardware structure
3824 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) in ixgbe_clear_tx_pending() argument
3833 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) in ixgbe_clear_tx_pending()
3841 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); in ixgbe_clear_tx_pending()
3842 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); in ixgbe_clear_tx_pending()
3845 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3851 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_clear_tx_pending()
3854 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_clear_tx_pending()
3855 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_tx_pending()
3862 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); in ixgbe_clear_tx_pending()
3863 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, in ixgbe_clear_tx_pending()
3867 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3871 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); in ixgbe_clear_tx_pending()
3872 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); in ixgbe_clear_tx_pending()
3890 * @hw: pointer to hardware structure
3896 static int ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, in ixgbe_get_ets_data() argument
3901 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); in ixgbe_get_ets_data()
3908 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); in ixgbe_get_ets_data()
3920 * @hw: pointer to hardware structure
3924 int ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) in ixgbe_get_thermal_sensor_data_generic() argument
3932 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_get_thermal_sensor_data_generic()
3935 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_get_thermal_sensor_data_generic()
3938 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_get_thermal_sensor_data_generic()
3950 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), in ixgbe_get_thermal_sensor_data_generic()
3961 status = hw->phy.ops.read_i2c_byte(hw, in ixgbe_get_thermal_sensor_data_generic()
3975 * @hw: pointer to hardware structure
3980 int ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) in ixgbe_init_thermal_sensor_thresh_generic() argument
3982 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_init_thermal_sensor_thresh_generic()
3995 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_init_thermal_sensor_thresh_generic()
3998 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_init_thermal_sensor_thresh_generic()
4011 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { in ixgbe_init_thermal_sensor_thresh_generic()
4012 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_init_thermal_sensor_thresh_generic()
4022 hw->phy.ops.write_i2c_byte(hw, in ixgbe_init_thermal_sensor_thresh_generic()
4040 * @hw: pointer to hardware structure
4046 void ixgbe_get_orom_version(struct ixgbe_hw *hw, in ixgbe_get_orom_version() argument
4053 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); in ixgbe_get_orom_version()
4059 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); in ixgbe_get_orom_version()
4060 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); in ixgbe_get_orom_version()
4077 * @hw: pointer to hardware structure
4083 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, in ixgbe_get_oem_prod_version() argument
4089 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); in ixgbe_get_oem_prod_version()
4096 hw->eeprom.ops.read(hw, offset, &mod_len); in ixgbe_get_oem_prod_version()
4097 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); in ixgbe_get_oem_prod_version()
4104 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); in ixgbe_get_oem_prod_version()
4105 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); in ixgbe_get_oem_prod_version()
4121 * @hw: pointer to hardware structure
4126 void ixgbe_get_etk_id(struct ixgbe_hw *hw, in ixgbe_get_etk_id() argument
4131 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) in ixgbe_get_etk_id()
4133 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) in ixgbe_get_etk_id()
4148 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_generic() argument
4152 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_disable_rx_generic()
4154 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_disable_rx_generic()
4157 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_disable_rx_generic()
4160 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_disable_rx_generic()
4161 hw->mac.set_lben = true; in ixgbe_disable_rx_generic()
4163 hw->mac.set_lben = false; in ixgbe_disable_rx_generic()
4167 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); in ixgbe_disable_rx_generic()
4171 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_generic() argument
4175 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_enable_rx_generic()
4176 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); in ixgbe_enable_rx_generic()
4178 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_enable_rx_generic()
4179 if (hw->mac.set_lben) { in ixgbe_enable_rx_generic()
4182 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_enable_rx_generic()
4184 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_enable_rx_generic()
4185 hw->mac.set_lben = false; in ixgbe_enable_rx_generic()
4191 * @hw: pointer to hardware structure
4193 bool ixgbe_mng_present(struct ixgbe_hw *hw) in ixgbe_mng_present() argument
4197 if (hw->mac.type < ixgbe_mac_82599EB) in ixgbe_mng_present()
4200 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); in ixgbe_mng_present()
4207 * @hw: pointer to hardware structure
4213 int ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_multispeed_fiber() argument
4225 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); in ixgbe_setup_mac_link_multispeed_fiber()
4239 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4241 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4248 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4255 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4262 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4263 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4274 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_multispeed_fiber()
4290 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4292 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4299 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4306 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4313 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4314 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4320 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, in ixgbe_setup_mac_link_multispeed_fiber()
4334 status = ixgbe_setup_mac_link_multispeed_fiber(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4340 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_multispeed_fiber()
4343 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4346 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4353 * @hw: pointer to hardware structure
4358 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, in ixgbe_set_soft_rate_select_speed() argument
4373 hw_dbg(hw, "Invalid fixed module speed\n"); in ixgbe_set_soft_rate_select_speed()
4378 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4382 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4388 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4392 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4397 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
4401 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); in ixgbe_set_soft_rate_select_speed()
4407 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
4411 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); in ixgbe_set_soft_rate_select_speed()