Lines Matching +full:tcs +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
25 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
30 * than the 10ms recommended by the pci-e spec. To address this we need to
39 if (ixgbe_removed(hw->hw_addr)) in ixgbe_set_pcie_completion_timeout()
71 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_82598()
76 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; in ixgbe_get_invariants_82598()
77 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; in ixgbe_get_invariants_82598()
78 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; in ixgbe_get_invariants_82598()
79 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; in ixgbe_get_invariants_82598()
80 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; in ixgbe_get_invariants_82598()
81 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; in ixgbe_get_invariants_82598()
82 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); in ixgbe_get_invariants_82598()
88 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
98 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_phy_ops_82598()
99 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82598()
104 phy->ops.identify(hw); in ixgbe_init_phy_ops_82598()
107 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { in ixgbe_init_phy_ops_82598()
108 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; in ixgbe_init_phy_ops_82598()
109 mac->ops.get_link_capabilities = in ixgbe_init_phy_ops_82598()
113 switch (hw->phy.type) { in ixgbe_init_phy_ops_82598()
115 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; in ixgbe_init_phy_ops_82598()
116 phy->ops.check_link = &ixgbe_check_phy_link_tnx; in ixgbe_init_phy_ops_82598()
119 phy->ops.reset = &ixgbe_reset_phy_nl; in ixgbe_init_phy_ops_82598()
122 ret_val = phy->ops.identify_sfp(hw); in ixgbe_init_phy_ops_82598()
125 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) in ixgbe_init_phy_ops_82598()
126 return -EOPNOTSUPP; in ixgbe_init_phy_ops_82598()
133 return -EOPNOTSUPP; in ixgbe_init_phy_ops_82598()
143 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
166 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
169 * @autoneg: boolean auto-negotiation value
184 if (hw->mac.orig_link_settings_stored) in ixgbe_get_link_capabilities_82598()
185 autoc = hw->mac.orig_autoc; in ixgbe_get_link_capabilities_82598()
216 return -EIO; in ixgbe_get_link_capabilities_82598()
223 * ixgbe_get_media_type_82598 - Determines media type
231 switch (hw->phy.type) { in ixgbe_get_media_type_82598()
241 switch (hw->device_id) { in ixgbe_get_media_type_82598()
269 * ixgbe_fc_enable_82598 - Enable flow control
285 if (!hw->fc.pause_time) in ixgbe_fc_enable_82598()
286 return -EINVAL; in ixgbe_fc_enable_82598()
290 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_82598()
291 hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
292 if (!hw->fc.low_water[i] || in ixgbe_fc_enable_82598()
293 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
295 return -EINVAL; in ixgbe_fc_enable_82598()
305 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); in ixgbe_fc_enable_82598()
307 switch (hw->fc.requested_mode) { in ixgbe_fc_enable_82598()
309 hw->fc.requested_mode = ixgbe_fc_tx_pause; in ixgbe_fc_enable_82598()
312 hw->fc.requested_mode = ixgbe_fc_none; in ixgbe_fc_enable_82598()
321 hw->mac.ops.fc_autoneg(hw); in ixgbe_fc_enable_82598()
340 switch (hw->fc.current_mode) { in ixgbe_fc_enable_82598()
372 return -EIO; in ixgbe_fc_enable_82598()
382 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_82598()
383 hw->fc.high_water[i]) { in ixgbe_fc_enable_82598()
384 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_fc_enable_82598()
385 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_82598()
395 /* Configure pause time (2 TCs per register) */ in ixgbe_fc_enable_82598()
396 reg = hw->fc.pause_time * 0x00010001; in ixgbe_fc_enable_82598()
401 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); in ixgbe_fc_enable_82598()
407 * ixgbe_start_mac_link_82598 - Configures MAC link settings
441 status = -EIO; in ixgbe_start_mac_link_82598()
454 * ixgbe_validate_link_ready - Function looks for phy link
465 if (hw->device_id != IXGBE_DEV_ID_82598AT2) in ixgbe_validate_link_ready()
470 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); in ixgbe_validate_link_ready()
481 return -EIO; in ixgbe_validate_link_ready()
488 * ixgbe_check_mac_link_82598 - Get link/speed status
510 if (hw->phy.type == ixgbe_phy_nl) { in ixgbe_check_mac_link_82598()
511 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); in ixgbe_check_mac_link_82598()
512 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); in ixgbe_check_mac_link_82598()
513 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, in ixgbe_check_mac_link_82598()
525 hw->phy.ops.read_reg(hw, 0xC79F, in ixgbe_check_mac_link_82598()
528 hw->phy.ops.read_reg(hw, 0xC00C, in ixgbe_check_mac_link_82598()
567 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && in ixgbe_check_mac_link_82598()
575 * ixgbe_setup_mac_link_82598 - Set MAC link speed
597 return -EINVAL; in ixgbe_setup_mac_link_82598()
620 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
634 status = hw->phy.ops.setup_link_speed(hw, speed, in ixgbe_setup_copper_link_82598()
643 * ixgbe_reset_hw_82598 - Performs hardware reset
661 status = hw->mac.ops.stop_adapter(hw); in ixgbe_reset_hw_82598()
670 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); in ixgbe_reset_hw_82598()
673 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, in ixgbe_reset_hw_82598()
676 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, in ixgbe_reset_hw_82598()
679 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, in ixgbe_reset_hw_82598()
682 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, in ixgbe_reset_hw_82598()
685 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, in ixgbe_reset_hw_82598()
688 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, in ixgbe_reset_hw_82598()
691 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, in ixgbe_reset_hw_82598()
694 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, in ixgbe_reset_hw_82598()
699 if (hw->phy.reset_disable == false) { in ixgbe_reset_hw_82598()
703 phy_status = hw->phy.ops.init(hw); in ixgbe_reset_hw_82598()
704 if (phy_status == -EOPNOTSUPP) in ixgbe_reset_hw_82598()
706 if (phy_status == -ENOENT) in ixgbe_reset_hw_82598()
709 hw->phy.ops.reset(hw); in ixgbe_reset_hw_82598()
722 /* Poll for reset bit to self-clear indicating reset is complete */ in ixgbe_reset_hw_82598()
730 status = -EIO; in ixgbe_reset_hw_82598()
741 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { in ixgbe_reset_hw_82598()
742 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_reset_hw_82598()
756 if (hw->mac.orig_link_settings_stored == false) { in ixgbe_reset_hw_82598()
757 hw->mac.orig_autoc = autoc; in ixgbe_reset_hw_82598()
758 hw->mac.orig_link_settings_stored = true; in ixgbe_reset_hw_82598()
759 } else if (autoc != hw->mac.orig_autoc) { in ixgbe_reset_hw_82598()
760 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); in ixgbe_reset_hw_82598()
764 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_82598()
770 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_82598()
779 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
787 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_vmdq_82598()
792 return -EINVAL; in ixgbe_set_vmdq_82598()
803 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
811 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_vmdq_82598()
817 return -EINVAL; in ixgbe_clear_vmdq_82598()
830 * ixgbe_set_vfta_82598 - Set VLAN filter table
835 * @vlvf_bypass: boolean flag - unused
848 return -EINVAL; in ixgbe_set_vfta_82598()
850 /* Determine 32-bit word position in array */ in ixgbe_set_vfta_82598()
879 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
886 u32 offset; in ixgbe_clear_vfta_82598() local
889 for (offset = 0; offset < hw->mac.vft_size; offset++) in ixgbe_clear_vfta_82598()
890 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); in ixgbe_clear_vfta_82598()
893 for (offset = 0; offset < hw->mac.vft_size; offset++) in ixgbe_clear_vfta_82598()
894 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), in ixgbe_clear_vfta_82598()
901 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
923 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
943 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
946 * @byte_offset: byte offset to read from dev_addr
966 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) in ixgbe_read_i2c_phy_82598()
967 return -EBUSY; in ixgbe_read_i2c_phy_82598()
969 if (hw->phy.type == ixgbe_phy_nl) { in ixgbe_read_i2c_phy_82598()
977 hw->phy.ops.write_reg_mdi(hw, in ixgbe_read_i2c_phy_82598()
984 hw->phy.ops.read_reg_mdi(hw, in ixgbe_read_i2c_phy_82598()
996 status = -ENOENT; in ixgbe_read_i2c_phy_82598()
1001 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, in ixgbe_read_i2c_phy_82598()
1006 status = -EIO; in ixgbe_read_i2c_phy_82598()
1010 hw->mac.ops.release_swfw_sync(hw, gssr); in ixgbe_read_i2c_phy_82598()
1015 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1017 * @byte_offset: EEPROM byte offset to read
1030 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1032 * @byte_offset: byte offset at address 0xA2
1035 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1045 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1054 struct ixgbe_bus_info *bus = &hw->bus; in ixgbe_set_lan_id_multi_port_pcie_82598()
1061 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); in ixgbe_set_lan_id_multi_port_pcie_82598()
1064 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); in ixgbe_set_lan_id_multi_port_pcie_82598()
1071 bus->func = 0; in ixgbe_set_lan_id_multi_port_pcie_82598()
1077 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1099 /* Setup the last four at 48KB...don't re-init i */ in ixgbe_set_rxpba_82598()
1104 /* Divide the remaining Rx packet buffer evenly among the TCs */ in ixgbe_set_rxpba_82598()