Lines Matching full:rw
8 #define IGC_CTRL 0x00000 /* Device Control - RW */
10 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define IGC_MDIC 0x00020 /* MDI Control - RW */
13 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
14 #define IGC_VET 0x00038 /* VLAN Ether Type - RW */
15 #define IGC_LEDCTL 0x00E00 /* LED Control - RW */
20 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
21 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
24 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
25 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
28 #define IGC_FCAL 0x00028 /* FC Address Low - RW */
29 #define IGC_FCAH 0x0002C /* FC Address High - RW */
30 #define IGC_FCT 0x00030 /* FC Type - RW */
31 #define IGC_FCTTV 0x00170 /* FC Transmit Timer - RW */
32 #define IGC_FCRTL 0x02160 /* FC Receive Threshold Low - RW */
33 #define IGC_FCRTH 0x02168 /* FC Receive Threshold High - RW */
34 #define IGC_FCRTV 0x02460 /* FC Refresh Timer Value - RW */
37 #define IGC_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
47 #define IGC_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
49 #define IGC_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
50 #define IGC_EIAM 0x01530 /* Ext. Interrupt Auto Mask - RW */
53 #define IGC_IMS 0x01508 /* Intr Mask Set/Read - RW */
55 #define IGC_IAM 0x01510 /* Intr Ack Auto Mask- RW */
56 /* Intr Throttle - RW */
58 /* Interrupt Vector Allocation - RW */
60 #define IGC_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
61 #define IGC_GPIE 0x01514 /* General Purpose Intr Enable - RW */
64 #define IGC_MRQC 0x05818 /* Multiple Receive Control - RW */
92 /* Redirection Table - RW Array */
94 /* RSS Random Key - RW Array */
98 #define IGC_RCTL 0x00100 /* Rx Control - RW */
108 #define IGC_RXCSUM 0x05000 /* Rx Checksum Control - RW */
111 #define IGC_MTA 0x05200 /* Multicast Table Array - RW Array */
112 #define IGC_RA 0x05400 /* Receive Address - RW Array */
113 #define IGC_UTA 0x0A000 /* Unicast Table Array - RW */
116 #define IGC_VLANPQF 0x055B0 /* VLAN Priority Queue Filter - RW */
119 #define IGC_TCTL 0x00400 /* Tx Control - RW */
120 #define IGC_TIPG 0x00410 /* Tx Inter-packet gap - RW */
205 #define IGC_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
206 #define IGC_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
207 #define IGC_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
208 #define IGC_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */
209 #define IGC_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */
210 #define IGC_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
211 #define IGC_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
212 #define IGC_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
213 #define IGC_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
214 #define IGC_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
241 #define IGC_TXARB 0x3354 /* Tx Arbitration Control TxARB - RW */
247 #define IGC_TIMINCA 0x0B608 /* Increment attributes register - RW */
252 #define IGC_TIMINCA_1 0x0B690 /* Increment attributes register - RW (timer 1) */
293 #define IGC_MANC 0x05820 /* Management Control - RW */
295 /* Shadow Ram Write Register - RW */
299 #define IGC_WUC 0x05800 /* Wakeup Control - RW */
300 #define IGC_WUFC 0x05808 /* Wakeup Filter Control - RW */
302 #define IGC_WUPL 0x05900 /* Wakeup Packet Length - RW */
303 #define IGC_WUFC_EXT 0x0580C /* Wakeup Filter Control Register Extended - RW */