Lines Matching +full:1 +full:qbv
29 #define IGC_WUFC_FLX1 BIT(17) /* Flexible Filter 1 Enable */
121 #define IGC_ERR_NVM 1
190 /* NVM Addressing bits based on type 0=small, 1=large */
204 #define IGC_NVM_RW_REG_START 1 /* Start operation */
223 #define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
224 #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
236 #define HALF_DUPLEX 1
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
257 #define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */
421 #define IGC_RXPBS_CFG_TS_EN FIELD_PREP(IGC_RXPBS_CFG_TS_EN_MASK, 1)
422 /* Default value following I225/I226 SW User Manual Section 8.3.1 */
456 #define IGC_RETX_CTL_QBVFULLTH_SHIFT 8 /* QBV Retry Buffer Full Threshold */
457 #define IGC_RETX_CTL_QBVFULLEN 0x1000 /* Enable QBV Retry Buffer Full Threshold */
470 #define IGC_TSICR_TXTS BIT(1) /* Transmit Timestamp. */
472 #define IGC_TSICR_TT1 BIT(4) /* Target Time 1 Trigger. */
474 #define IGC_TSICR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
511 #define IGC_TSYNCTXCTL_TXTT_1 0x00000002 /* Tx timestamp reg 1 valid */
527 #define IGC_AUX_IO_TIMER_SEL_SYSTIM1 (1u << 30) /* Select SYSTIM1 for auxiliary time stamp */
531 #define IGC_TT_IO_TIMER_SEL_SYSTIM1 (1u << 30) /* Select SYSTIM1 for target time stamp */
537 #define IGC_TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
540 #define IGC_TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
541 #define IGC_TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */
550 #define IGC_TSAUXC_DIS_TS_CLEAR BIT(30) /* Disable EN_TT0/1 auto clear. */
555 #define IGC_AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
558 #define IGC_AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
559 #define IGC_AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
560 #define IGC_AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
561 #define IGC_AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
562 #define IGC_AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
563 #define IGC_AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
565 #define IGC_TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
567 #define IGC_TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
568 #define IGC_TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
570 #define IGC_TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
572 #define IGC_TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
573 #define IGC_TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
575 #define IGC_TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
577 #define IGC_TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
578 #define IGC_TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
580 #define IGC_TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
582 #define IGC_TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
583 #define IGC_TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */
605 #define IGC_TXARB_TXQ_PRIO_0_MASK GENMASK(1, 0)
625 /* A short cycle time of 1us theoretically should work, but appears to be too
642 #define IGC_PTM_STAT_RET_ERR BIT(1) /* Root port timeout */
645 #define IGC_PTM_STAT_ADJUST_1ST BIT(4) /* 1588 timer adjusted during 1st PTM cycle */
646 #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */
663 #define IGC_FWSM_MODE_SHIFT 1
680 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
688 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
709 #define IGC_EEE_100BT_MASK BIT(1)
714 #define IGC_LP_EEE_100BT_MASK BIT(1)
716 #define IGC_N0_QUEUE -1
726 #define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type:1=IPv4 */
735 #define IGC_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */