Lines Matching +full:12 +full:gbps
67 #define IGC_WUFC_EXT_FLX12 BIT(12) /* Flexible Filter 12 Enable */
128 #define IGC_ERR_BLK_PHY_RESET 12
220 #define IGC_COLD_SHIFT 12
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
402 #define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */
411 #define IGC_RXPBSIZE_BE_MASK GENMASK(17, 12)
431 #define IGC_TXPB2SIZE_MASK GENMASK(17, 12)
574 #define IGC_TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
575 #define IGC_TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
576 #define IGC_TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
577 #define IGC_TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */