Lines Matching defs:igc_ring
146 struct igc_ring { struct
147 struct igc_q_vector *q_vector; /* backlink to q_vector */
148 struct net_device *netdev; /* back pointer to net_device */
149 struct device *dev; /* device for dma mapping */
150 union { /* array of buffer info structs */
154 void *desc; /* descriptor ring memory */
155 unsigned long flags; /* ring specific flags */
156 void __iomem *tail; /* pointer to ring tail register */
157 dma_addr_t dma; /* phys address of the ring */
158 unsigned int size; /* length of desc. ring in bytes */
160 u16 count; /* number of desc. in the ring */
161 u8 queue_index; /* logical index of the ring*/
162 u8 reg_idx; /* physical index of the ring */
163 bool launchtime_enable; /* true if LaunchTime is enabled */
164 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
165 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
167 u32 start_time;
168 u32 end_time;
169 u32 max_sdu;
170 bool oper_gate_closed; /* Operating gate. True if the TX Queue is closed */
171 bool admin_gate_closed; /* Future gate. True if the TX Queue will be closed */
174 bool cbs_enable; /* indicates if CBS is enabled */
175 s32 idleslope; /* idleSlope in kbps */
176 s32 sendslope; /* sendSlope in kbps */
177 s32 hicredit; /* hiCredit in bytes */
178 s32 locredit; /* loCredit in bytes */
181 u16 next_to_clean;
182 u16 next_to_use;
183 u16 next_to_alloc;
185 union {
221 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; argument