Lines Matching +full:0 +full:x4fc
131 #define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)
205 ICE_RCLKA_PIN = 0, /* SCL pin */
215 ZL_REF0P = 0,
229 ZL_OUT0 = 0,
240 SI_REF0P = 0,
252 SI_OUT0 = 0,
284 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
285 #define ICE_E810_E830_SYNC_DELAY 0
378 #define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
379 #define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL
380 #define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL
381 #define ICE_ETH56G_NOMINAL_THRESH4 0x7777
382 #define ICE_ETH56G_NOMINAL_TX_THRESH 0x6
388 * Return: base clock increment value for supported PHYs, 0 otherwise
401 return 0; in ice_get_base_incval()
407 #define ICE_PTP_CLOCK_INDEX_0 0x00
408 #define ICE_PTP_CLOCK_INDEX_1 0x01
415 #define GLTSYN_CMD_INIT_TIME BIT(0)
417 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
423 #define PHY_CMD_INIT_TIME BIT(0)
425 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
426 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
427 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
429 #define TS_CMD_MASK_E810 0xFF
430 #define TS_CMD_MASK 0xF
431 #define SYNC_EXEC_CMD 0x3
432 #define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
435 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
436 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
437 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
438 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
441 #define Q_0_BASE 0x94000
442 #define Q_1_BASE 0x114000
445 #define Q_REG_TS_CTRL 0x618
446 #define Q_REG_TS_CTRL_S 0
447 #define Q_REG_TS_CTRL_M BIT(0)
450 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
451 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
454 #define Q_REG_FIFO23_STATUS 0xCF8
455 #define Q_REG_FIFO01_STATUS 0xCFC
456 #define Q_REG_FIFO02_S 0
457 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
459 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
462 #define Q_REG_TX_MEM_GBL_CFG 0xC08
463 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
464 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
465 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
466 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
470 #define Q_REG_TX_MEMORY_BANK_START 0xA00
473 #define P_0_BASE 0x80000
474 #define P_4_BASE 0x106000
477 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
478 #define P_REG_RX_TIMER_INC_PRE_U 0x470
479 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
480 #define P_REG_TX_TIMER_INC_PRE_U 0x450
483 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
484 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
485 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
486 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
489 #define P_REG_RX_CAPTURE_L 0x4D8
490 #define P_REG_RX_CAPTURE_U 0x4DC
491 #define P_REG_TX_CAPTURE_L 0x4B4
492 #define P_REG_TX_CAPTURE_U 0x4B8
495 #define P_REG_TIMETUS_L 0x410
496 #define P_REG_TIMETUS_U 0x414
498 #define P_REG_40B_LOW_M GENMASK(7, 0)
502 #define P_REG_WL 0x40C
504 #define PTP_VERNIER_WL 0x111ed
507 #define P_REG_PS 0x408
508 #define P_REG_PS_START_S 0
509 #define P_REG_PS_START_M BIT(0)
520 #define P_REG_TX_OV_STATUS 0x4D4
521 #define P_REG_TX_OV_STATUS_OV_S 0
522 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
523 #define P_REG_RX_OV_STATUS 0x4F8
524 #define P_REG_RX_OV_STATUS_OV_S 0
525 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
528 #define P_REG_TX_OR 0x45C
529 #define P_REG_RX_OR 0x47C
532 #define P_REG_TOTAL_RX_OFFSET_L 0x460
533 #define P_REG_TOTAL_RX_OFFSET_U 0x464
534 #define P_REG_TOTAL_TX_OFFSET_L 0x440
535 #define P_REG_TOTAL_TX_OFFSET_U 0x444
538 #define P_REG_UIX66_10G_40G_L 0x480
539 #define P_REG_UIX66_10G_40G_U 0x484
540 #define P_REG_UIX66_25G_100G_L 0x488
541 #define P_REG_UIX66_25G_100G_U 0x48C
542 #define P_REG_DESK_PAR_RX_TUS_L 0x490
543 #define P_REG_DESK_PAR_RX_TUS_U 0x494
544 #define P_REG_DESK_PAR_TX_TUS_L 0x498
545 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
546 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
547 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
548 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
549 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
550 #define P_REG_PAR_RX_TUS_L 0x420
551 #define P_REG_PAR_RX_TUS_U 0x424
552 #define P_REG_PAR_TX_TUS_L 0x428
553 #define P_REG_PAR_TX_TUS_U 0x42C
554 #define P_REG_PCS_RX_TUS_L 0x430
555 #define P_REG_PCS_RX_TUS_U 0x434
556 #define P_REG_PCS_TX_TUS_L 0x438
557 #define P_REG_PCS_TX_TUS_U 0x43C
558 #define P_REG_PAR_RX_TIME_L 0x4F0
559 #define P_REG_PAR_RX_TIME_U 0x4F4
560 #define P_REG_PAR_TX_TIME_L 0x4CC
561 #define P_REG_PAR_TX_TIME_U 0x4D0
562 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
563 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
564 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
565 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
566 #define P_REG_LINK_SPEED 0x4FC
567 #define P_REG_LINK_SPEED_SERDES_S 0
568 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
570 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
576 #define P_REG_PMD_ALIGNMENT 0x0FC
577 #define P_REG_RX_80_TO_160_CNT 0x6FC
578 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
579 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
580 #define P_REG_RX_40_TO_160_CNT 0x8FC
581 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
582 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
585 #define P_REG_RX_OV_FS 0x4F8
587 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
590 #define P_REG_TX_TMR_CMD 0x448
591 #define P_REG_RX_TMR_CMD 0x468
594 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
597 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
598 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
601 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
602 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
605 #define E810_ETH_GLTSYN_CMD 0x03000344
608 #define E830_ETH_GLTSYN_CMD 0x00088814
611 #define E830_GLTSYN_TIME_L(_tmr_idx) (0x0008A000 + 0x1000 * (_tmr_idx))
614 #define INCVAL_HIGH_M 0xFF
617 #define PHY_EXT_40B_LOW_M GENMASK(31, 0)
619 #define PHY_40B_LOW_M GENMASK(7, 0)
621 #define TS_VALID BIT(0)
622 #define TS_LOW_M 0xFFFFFFFF
623 #define TS_HIGH_M 0xFF
632 #define REG_LL_PROXY_H_PHY_TMR_CMD_ADJ 0x1
633 #define REG_LL_PROXY_H_PHY_TMR_CMD_FREQ 0x2
649 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
652 #define LOW_TX_MEMORY_BANK_START 0x03090000
653 #define HIGH_TX_MEMORY_BANK_START 0x03090004
673 #define ICE_PCA9575_P0_IN 0x0
680 #define PHY_REG_TIMETUS_L 0x8
681 #define PHY_REG_TIMETUS_U 0xC
684 #define PHY_PCS_REF_TUS_L 0x18
685 #define PHY_PCS_REF_TUS_U 0x1C
688 #define PHY_PCS_REF_INC_L 0x20
689 #define PHY_PCS_REF_INC_U 0x24
692 #define PHY_REG_RX_TIMER_INC_PRE_L 0x64
693 #define PHY_REG_RX_TIMER_INC_PRE_U 0x68
694 #define PHY_REG_TX_TIMER_INC_PRE_L 0x44
695 #define PHY_REG_TX_TIMER_INC_PRE_U 0x48
698 #define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C
699 #define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70
700 #define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C
701 #define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50
704 #define PHY_REG_TX_TMR_CMD 0x40
705 #define PHY_REG_RX_TMR_CMD 0x60
708 #define PHY_REG_TX_OFFSET_READY 0x54
709 #define PHY_REG_RX_OFFSET_READY 0x74
712 #define PHY_REG_TOTAL_TX_OFFSET_L 0x38
713 #define PHY_REG_TOTAL_TX_OFFSET_U 0x3C
714 #define PHY_REG_TOTAL_RX_OFFSET_L 0x58
715 #define PHY_REG_TOTAL_RX_OFFSET_U 0x5C
718 #define PHY_REG_TX_CAPTURE_L 0x78
719 #define PHY_REG_TX_CAPTURE_U 0x7C
720 #define PHY_REG_RX_CAPTURE_L 0x8C
721 #define PHY_REG_RX_CAPTURE_U 0x90
724 #define PHY_REG_TX_MEMORY_STATUS_L 0x80
725 #define PHY_REG_TX_MEMORY_STATUS_U 0x84
728 #define PHY_REG_TS_INT_CONFIG 0x88
731 #define PHY_MAC_XIF_MODE 0x24
732 #define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
733 #define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
734 #define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
735 #define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
737 #define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)
741 #define PHY_TSTAMP_L(x) (((x) * 8) + 0)
744 #define PHY_REG_DESKEW_0 0x94
745 #define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)
750 #define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))
751 #define PHY_REVISION_ETH56G 0x10200
752 #define PHY_VENDOR_TXLANE_THRESH 0x2000C
754 #define PHY_MAC_TSU_CONFIG 0x40
755 #define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
756 #define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M ICE_M(0x7, 4)
757 #define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M ICE_M(0x7, 8)
758 #define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
759 #define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M ICE_M(0x1F, 16)
760 #define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M ICE_M(0x1F, 21)
761 #define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M ICE_M(0x1, 28)
762 #define PHY_MAC_RX_MODULO 0x44
763 #define PHY_MAC_RX_OFFSET 0x48
764 #define PHY_MAC_RX_OFFSET_M ICE_M(0xFFFFFF, 0)
765 #define PHY_MAC_TX_MODULO 0x4C
766 #define PHY_MAC_BLOCKTIME 0x50
767 #define PHY_MAC_MARKERTIME 0x54
768 #define PHY_MAC_TX_OFFSET 0x58
769 #define PHY_GPCS_BITSLIP 0x5C
771 #define PHY_PTP_INT_STATUS 0x7FD140
775 #define PHY_GPCS_CONFIG_REG0 0x268
778 #define PHY_PTP_1STEP_CONFIG 0x270
781 #define PHY_PTP_1STEP_PEER_DELAY(_quad_lane) (0x274 + 4 * (_quad_lane))
782 #define PHY_PTP_1STEP_PD_ADD_PD_M BIT(0)