Lines Matching +full:sync +full:- +full:pins

1 /* SPDX-License-Identifier: GPL-2.0 */
12  * enum ice_dpll_pin_sw - enumerate ice software pin indices:
15  * @ICE_DPLL_PIN_SW_NUM: number of SW pins in pair
23 /** ice_dpll_pin - store info about pins
27  * @num_parents: hols number of parent pins
28  * @parent_idx: hold indexes of parent pins
35  * @ref_sync: store id of reference sync pin
58 /** ice_dpll - store info required for DPLL control
69  * @dpll_state: current dpll sync state
70  * @prev_dpll_state: last dpll sync state
96 /** ice_dplls - store info required for CCU (clock controlling unit)
102  * @inputs: input pins pointer
103  * @outputs: output pins pointer
104  * @rclk: recovered pins pointer
105  * @num_inputs: number of input pins available on dpll
106  * @num_outputs: number of output pins available on dpll
108  * @base_rclk_idx: idx of first pin used for clock revocery pins
110  * @input_phase_adj_max: max phase adjust value for an input pins
111  * @output_phase_adj_max: max phase adjust value for an output pins