Lines Matching +full:sync +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0
53 * enum ice_dpll_pin_type - enumerate ice pin types:
58 * @ICE_DPLL_PIN_TYPE_SOFTWARE: software controlled SMA/U.FL pins
71 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
83 * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW
88 * Check if the pin shall be controlled by SW - instead of providing raw access
89 * for pin control. For E810 NIC with dpll there is additional MUX-related logic
90 * between SMA/U.FL pins/connectors and dpll device, best to give user access
92 * functionality rather then separated pins.
95 * * true - pin controlled by SW
96 * * false - pin not controlled by SW
100 if (input && pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) in ice_dpll_is_sw_pin()
101 index -= ICE_DPLL_SW_PIN_INPUT_BASE_QSFP - in ice_dpll_is_sw_pin()
113 * ice_dpll_is_reset - check if reset is in progress
120 * * false - no reset in progress
121 * * true - reset in progress
125 if (ice_is_reset_in_progress(pf->state)) { in ice_dpll_is_reset()
133 * ice_dpll_pin_freq_set - set pin's frequency
142 * Context: Called under pf->dplls.lock
144 * * 0 - success
145 * * negative - error on AQ or wrong pin type given
158 ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
159 pin->flags[0], freq, 0); in ice_dpll_pin_freq_set()
163 ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
167 return -EINVAL; in ice_dpll_pin_freq_set()
173 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_freq_set()
174 freq, pin->idx); in ice_dpll_pin_freq_set()
177 pin->freq = freq; in ice_dpll_pin_freq_set()
183 * ice_dpll_frequency_set - wrapper for pin callback for set frequency
194 * Context: Acquires pf->dplls.lock
196 * * 0 - success
197 * * negative - error pin not found or couldn't set in hw
208 struct ice_pf *pf = d->pf; in ice_dpll_frequency_set()
212 return -EBUSY; in ice_dpll_frequency_set()
214 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
216 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
222 * ice_dpll_input_frequency_set - input pin callback for set frequency
232 * Context: Calls a function which acquires pf->dplls.lock
234 * * 0 - success
235 * * negative - error pin not found or couldn't set in hw
247 * ice_dpll_output_frequency_set - output pin callback for set frequency
257 * Context: Calls a function which acquires pf->dplls.lock
259 * * 0 - success
260 * * negative - error pin not found or couldn't set in hw
272 * ice_dpll_frequency_get - wrapper for pin callback for get frequency
283 * Context: Acquires pf->dplls.lock
285 * * 0 - success
286 * * negative - error pin not found or couldn't get from hw
296 struct ice_pf *pf = d->pf; in ice_dpll_frequency_get()
298 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
299 *frequency = p->freq; in ice_dpll_frequency_get()
300 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
306 * ice_dpll_input_frequency_get - input pin callback for get frequency
316 * Context: Calls a function which acquires pf->dplls.lock
318 * * 0 - success
319 * * negative - error pin not found or couldn't get from hw
331 * ice_dpll_output_frequency_get - output pin callback for get frequency
341 * Context: Calls a function which acquires pf->dplls.lock
343 * * 0 - success
344 * * negative - error pin not found or couldn't get from hw
356 * ice_dpll_sw_pin_frequency_set - callback to set frequency of SW pin
366 * Context: Calls a function which acquires and releases pf->dplls.lock
368 * * 0 - success
369 * * negative - error pin not active or couldn't get from hw
379 if (!sma->active) { in ice_dpll_sw_pin_frequency_set()
381 return -EINVAL; in ice_dpll_sw_pin_frequency_set()
383 if (sma->direction == DPLL_PIN_DIRECTION_INPUT) in ice_dpll_sw_pin_frequency_set()
384 ret = ice_dpll_input_frequency_set(NULL, sma->input, dpll, in ice_dpll_sw_pin_frequency_set()
388 ret = ice_dpll_output_frequency_set(NULL, sma->output, dpll, in ice_dpll_sw_pin_frequency_set()
396 * ice_dpll_sw_pin_frequency_get - callback for get frequency of SW pin
406 * Context: Calls a function which acquires and releases pf->dplls.lock
408 * * 0 - success
409 * * negative - error pin not active or couldn't get from hw
419 if (!sma->active) { in ice_dpll_sw_pin_frequency_get()
423 if (sma->direction == DPLL_PIN_DIRECTION_INPUT) { in ice_dpll_sw_pin_frequency_get()
424 ret = ice_dpll_input_frequency_get(NULL, sma->input, dpll, in ice_dpll_sw_pin_frequency_get()
428 ret = ice_dpll_output_frequency_get(NULL, sma->output, dpll, in ice_dpll_sw_pin_frequency_get()
437 * ice_dpll_pin_enable - enable a pin on dplls
444 * Enable a pin on both dplls. Store current state in pin->flags.
446 * Context: Called under pf->dplls.lock
448 * * 0 - OK
449 * * negative - error
461 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_enable()
464 ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0); in ice_dpll_pin_enable()
468 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_enable()
471 ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, dpll_idx, in ice_dpll_pin_enable()
475 return -EINVAL; in ice_dpll_pin_enable()
480 ret, libie_aq_str(hw->adminq.sq_last_status), in ice_dpll_pin_enable()
481 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_enable()
487 * ice_dpll_pin_disable - disable a pin on dplls
493 * Disable a pin on both dplls. Store current state in pin->flags.
495 * Context: Called under pf->dplls.lock
497 * * 0 - OK
498 * * negative - error
510 if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_disable()
512 ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0); in ice_dpll_pin_disable()
515 if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_disable()
517 ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, 0, 0, 0); in ice_dpll_pin_disable()
520 return -EINVAL; in ice_dpll_pin_disable()
525 ret, libie_aq_str(hw->adminq.sq_last_status), in ice_dpll_pin_disable()
526 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_disable()
532 * ice_dpll_sw_pins_update - update status of all SW pins
536 * values for all the SW controlled pins.
538 * Context: Call with pf->dplls.lock held
540 * * 0 - OK
541 * * negative - error
546 struct ice_dplls *d = &pf->dplls; in ice_dpll_sw_pins_update()
551 ret = ice_read_sma_ctrl(&pf->hw, &data); in ice_dpll_sw_pins_update()
555 if (d->sma_data == data) in ice_dpll_sw_pins_update()
562 p = &d->sma[ICE_DPLL_PIN_SW_1_IDX]; in ice_dpll_sw_pins_update()
563 p->active = true; in ice_dpll_sw_pins_update()
564 p->direction = DPLL_PIN_DIRECTION_INPUT; in ice_dpll_sw_pins_update()
566 p->direction = DPLL_PIN_DIRECTION_OUTPUT; in ice_dpll_sw_pins_update()
568 p->active = false; in ice_dpll_sw_pins_update()
571 p = &d->sma[ICE_DPLL_PIN_SW_2_IDX]; in ice_dpll_sw_pins_update()
572 p->active = true; in ice_dpll_sw_pins_update()
573 p->direction = DPLL_PIN_DIRECTION_INPUT; in ice_dpll_sw_pins_update()
575 p->active = false; in ice_dpll_sw_pins_update()
577 p->direction = DPLL_PIN_DIRECTION_OUTPUT; in ice_dpll_sw_pins_update()
579 p = &d->ufl[ICE_DPLL_PIN_SW_1_IDX]; in ice_dpll_sw_pins_update()
581 p->active = true; in ice_dpll_sw_pins_update()
583 p->active = false; in ice_dpll_sw_pins_update()
585 p = &d->ufl[ICE_DPLL_PIN_SW_2_IDX]; in ice_dpll_sw_pins_update()
586 p->active = (data & ICE_SMA2_DIR_EN) && !(data & ICE_SMA2_UFL2_RX_DIS); in ice_dpll_sw_pins_update()
587 d->sma_data = data; in ice_dpll_sw_pins_update()
593 * ice_dpll_pin_state_update - update pin's state
601 * dpll, for rclk pins states are separated for each parent.
603 * Context: Called under pf->dplls.lock
605 * * 0 - OK
606 * * negative - error
618 ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, &pin->status, in ice_dpll_pin_state_update()
619 NULL, NULL, &pin->flags[0], in ice_dpll_pin_state_update()
620 &pin->freq, &pin->phase_adjust); in ice_dpll_pin_state_update()
623 if (ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN & pin->flags[0]) { in ice_dpll_pin_state_update()
624 if (pin->pin) { in ice_dpll_pin_state_update()
625 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
626 pin->pin == pf->dplls.eec.active_input ? in ice_dpll_pin_state_update()
629 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
630 pin->pin == pf->dplls.pps.active_input ? in ice_dpll_pin_state_update()
634 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
636 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
640 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
642 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
647 ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx, in ice_dpll_pin_state_update()
648 &pin->flags[0], &parent, in ice_dpll_pin_state_update()
649 &pin->freq, NULL); in ice_dpll_pin_state_update()
654 if (ICE_AQC_GET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) { in ice_dpll_pin_state_update()
655 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
656 parent == pf->dplls.eec.dpll_idx ? in ice_dpll_pin_state_update()
659 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
660 parent == pf->dplls.pps.dpll_idx ? in ice_dpll_pin_state_update()
664 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
666 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
671 for (parent = 0; parent < pf->dplls.rclk.num_parents; in ice_dpll_pin_state_update()
675 ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p, in ice_dpll_pin_state_update()
677 &pin->flags[parent], in ice_dpll_pin_state_update()
682 pin->flags[parent]) in ice_dpll_pin_state_update()
683 pin->state[parent] = DPLL_PIN_STATE_CONNECTED; in ice_dpll_pin_state_update()
685 pin->state[parent] = in ice_dpll_pin_state_update()
695 return -EINVAL; in ice_dpll_pin_state_update()
704 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
705 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_state_update()
710 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
711 pin_type_name[pin_type], pin->idx); in ice_dpll_pin_state_update()
716 * ice_dpll_hw_input_prio_set - set input priority value in hardware
725 * Context: Called under pf->dplls.lock
727 * * 0 - success
728 * * negative - failure
737 ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx, in ice_dpll_hw_input_prio_set()
743 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_hw_input_prio_set()
744 prio, pin->idx); in ice_dpll_hw_input_prio_set()
746 dpll->input_prio[pin->idx] = prio; in ice_dpll_hw_input_prio_set()
752 * ice_dpll_lock_status_get - get dpll lock status callback
761 * Context: Acquires pf->dplls.lock
763 * * 0 - success
764 * * negative - failure
773 struct ice_pf *pf = d->pf; in ice_dpll_lock_status_get()
775 mutex_lock(&pf->dplls.lock); in ice_dpll_lock_status_get()
776 *status = d->dpll_state; in ice_dpll_lock_status_get()
777 mutex_unlock(&pf->dplls.lock); in ice_dpll_lock_status_get()
783 * ice_dpll_mode_get - get dpll's working mode
791 * Context: Acquires pf->dplls.lock
793 * * 0 - success
794 * * negative - failure
801 struct ice_pf *pf = d->pf; in ice_dpll_mode_get()
803 mutex_lock(&pf->dplls.lock); in ice_dpll_mode_get()
804 *mode = d->mode; in ice_dpll_mode_get()
805 mutex_unlock(&pf->dplls.lock); in ice_dpll_mode_get()
811 * ice_dpll_phase_offset_monitor_set - set phase offset monitor state
819 * Context: Acquires and releases pf->dplls.lock
820 * Return: 0 - success
828 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_monitor_set()
830 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_monitor_set()
832 d->phase_offset_monitor_period = ICE_DPLL_PHASE_OFFSET_PERIOD; in ice_dpll_phase_offset_monitor_set()
834 d->phase_offset_monitor_period = 0; in ice_dpll_phase_offset_monitor_set()
835 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_monitor_set()
841 * ice_dpll_phase_offset_monitor_get - get phase offset monitor state
850 * Context: Acquires and releases pf->dplls.lock
851 * Return: 0 - success
859 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_monitor_get()
861 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_monitor_get()
862 if (d->phase_offset_monitor_period) in ice_dpll_phase_offset_monitor_get()
866 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_monitor_get()
872 * ice_dpll_pin_state_set - set pin's state on dpll
883 * Context: Acquires pf->dplls.lock
885 * * 0 - OK or no change required
886 * * negative - error
896 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_set()
900 return -EBUSY; in ice_dpll_pin_state_set()
902 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_set()
904 ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type, in ice_dpll_pin_state_set()
907 ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack); in ice_dpll_pin_state_set()
910 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_set()
916 * ice_dpll_output_state_set - enable/disable output pin on dpll device
926 * Context: Calls a function which acquires pf->dplls.lock
928 * * 0 - successfully enabled mode
929 * * negative - failed to enable mode
942 return -EINVAL; in ice_dpll_output_state_set()
943 if (!enable && p->state[d->dpll_idx] == DPLL_PIN_STATE_DISCONNECTED) in ice_dpll_output_state_set()
951 * ice_dpll_input_state_set - enable/disable input pin on dpll levice
961 * Context: Calls a function which acquires pf->dplls.lock
963 * * 0 - successfully enabled mode
964 * * negative - failed to enable mode
979 * ice_dpll_pin_state_get - set pin's state on dpll
990 * Context: Acquires pf->dplls.lock
992 * * 0 - success
993 * * negative - failed to get state
1004 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_get()
1008 return -EBUSY; in ice_dpll_pin_state_get()
1010 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_get()
1016 *state = p->state[d->dpll_idx]; in ice_dpll_pin_state_get()
1019 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_get()
1025 * ice_dpll_output_state_get - get output pin state on dpll device
1035 * Context: Calls a function which acquires pf->dplls.lock
1037 * * 0 - success
1038 * * negative - failed to get state
1051 * ice_dpll_input_state_get - get input pin state on dpll device
1061 * Context: Calls a function which acquires pf->dplls.lock
1063 * * 0 - success
1064 * * negative - failed to get state
1077 * ice_dpll_sma_direction_set - set direction of SMA pin
1084 * Context: Call with pf->dplls.lock held
1086 * * 0 - success
1087 * * negative - failed to get state
1096 if (p->direction == direction && p->active) in ice_dpll_sma_direction_set()
1098 ret = ice_read_sma_ctrl(&p->pf->hw, &data); in ice_dpll_sma_direction_set()
1102 switch (p->idx) { in ice_dpll_sma_direction_set()
1117 return -EINVAL; in ice_dpll_sma_direction_set()
1119 ret = ice_write_sma_ctrl(&p->pf->hw, data); in ice_dpll_sma_direction_set()
1121 ret = ice_dpll_pin_state_update(p->pf, p, in ice_dpll_sma_direction_set()
1129 * ice_dpll_ufl_pin_state_set - set U.FL pin state on dpll device
1139 * Context: Acquires and releases pf->dplls.lock
1141 * * 0 - success
1142 * * negative - error
1153 struct ice_pf *pf = p->pf; in ice_dpll_ufl_pin_state_set()
1160 return -EBUSY; in ice_dpll_ufl_pin_state_set()
1162 mutex_lock(&pf->dplls.lock); in ice_dpll_ufl_pin_state_set()
1163 hw = &pf->hw; in ice_dpll_ufl_pin_state_set()
1168 ret = -EINVAL; in ice_dpll_ufl_pin_state_set()
1169 switch (p->idx) { in ice_dpll_ufl_pin_state_set()
1180 target = p->output; in ice_dpll_ufl_pin_state_set()
1194 target = p->input; in ice_dpll_ufl_pin_state_set()
1210 ret = ice_dpll_pin_enable(hw, target, d->dpll_idx, type, extack); in ice_dpll_ufl_pin_state_set()
1217 mutex_unlock(&pf->dplls.lock); in ice_dpll_ufl_pin_state_set()
1223 * ice_dpll_sw_pin_state_get - get SW pin state
1233 * Context: Acquires and releases pf->dplls.lock
1235 * * 0 - success
1236 * * negative - error
1246 struct ice_pf *pf = p->pf; in ice_dpll_sw_pin_state_get()
1250 return -EBUSY; in ice_dpll_sw_pin_state_get()
1251 mutex_lock(&pf->dplls.lock); in ice_dpll_sw_pin_state_get()
1252 if (!p->active) { in ice_dpll_sw_pin_state_get()
1257 if (p->direction == DPLL_PIN_DIRECTION_INPUT) { in ice_dpll_sw_pin_state_get()
1258 ret = ice_dpll_pin_state_update(pf, p->input, in ice_dpll_sw_pin_state_get()
1263 *state = p->input->state[d->dpll_idx]; in ice_dpll_sw_pin_state_get()
1265 ret = ice_dpll_pin_state_update(pf, p->output, in ice_dpll_sw_pin_state_get()
1270 *state = p->output->state[d->dpll_idx]; in ice_dpll_sw_pin_state_get()
1273 mutex_unlock(&pf->dplls.lock); in ice_dpll_sw_pin_state_get()
1279 * ice_dpll_sma_pin_state_set - set SMA pin state on dpll device
1289 * Context: Acquires and releases pf->dplls.lock
1291 * * 0 - success
1292 * * negative - failed to get state
1302 struct ice_pf *pf = sma->pf; in ice_dpll_sma_pin_state_set()
1308 return -EBUSY; in ice_dpll_sma_pin_state_set()
1310 mutex_lock(&pf->dplls.lock); in ice_dpll_sma_pin_state_set()
1311 if (!sma->active) { in ice_dpll_sma_pin_state_set()
1312 ret = ice_dpll_sma_direction_set(sma, sma->direction, extack); in ice_dpll_sma_pin_state_set()
1316 if (sma->direction == DPLL_PIN_DIRECTION_INPUT) { in ice_dpll_sma_pin_state_set()
1318 target = sma->input; in ice_dpll_sma_pin_state_set()
1322 target = sma->output; in ice_dpll_sma_pin_state_set()
1327 ret = ice_dpll_pin_enable(&pf->hw, target, d->dpll_idx, type, in ice_dpll_sma_pin_state_set()
1330 ret = ice_dpll_pin_disable(&pf->hw, target, type, extack); in ice_dpll_sma_pin_state_set()
1335 mutex_unlock(&pf->dplls.lock); in ice_dpll_sma_pin_state_set()
1341 * ice_dpll_input_prio_get - get dpll's input prio
1346 * @prio: on success - returns input priority on dpll
1351 * Context: Acquires pf->dplls.lock
1353 * * 0 - success
1354 * * negative - failure
1363 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_get()
1365 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_get()
1366 *prio = d->input_prio[p->idx]; in ice_dpll_input_prio_get()
1367 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_get()
1373 * ice_dpll_input_prio_set - set dpll input prio
1383 * Context: Acquires pf->dplls.lock
1385 * * 0 - success
1386 * * negative - failure
1395 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_set()
1399 return -EBUSY; in ice_dpll_input_prio_set()
1401 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_set()
1403 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_set()
1415 struct ice_pf *pf = d->pf; in ice_dpll_sw_input_prio_get()
1417 mutex_lock(&pf->dplls.lock); in ice_dpll_sw_input_prio_get()
1418 if (p->input && p->direction == DPLL_PIN_DIRECTION_INPUT) in ice_dpll_sw_input_prio_get()
1419 *prio = d->input_prio[p->input->idx]; in ice_dpll_sw_input_prio_get()
1422 mutex_unlock(&pf->dplls.lock); in ice_dpll_sw_input_prio_get()
1434 struct ice_pf *pf = d->pf; in ice_dpll_sw_input_prio_set()
1437 if (!p->input || p->direction != DPLL_PIN_DIRECTION_INPUT) in ice_dpll_sw_input_prio_set()
1438 return -EINVAL; in ice_dpll_sw_input_prio_set()
1440 return -EBUSY; in ice_dpll_sw_input_prio_set()
1442 mutex_lock(&pf->dplls.lock); in ice_dpll_sw_input_prio_set()
1443 ret = ice_dpll_hw_input_prio_set(pf, d, p->input, prio, extack); in ice_dpll_sw_input_prio_set()
1444 mutex_unlock(&pf->dplls.lock); in ice_dpll_sw_input_prio_set()
1450 * ice_dpll_input_direction - callback for get input pin direction
1461 * * 0 - success
1475 * ice_dpll_output_direction - callback for get output pin direction
1486 * * 0 - success
1500 * ice_dpll_pin_sma_direction_set - callback for set SMA pin direction
1510 * Context: Acquires and releases pf->dplls.lock
1512 * * 0 - success
1513 * * negative - error
1522 struct ice_pf *pf = p->pf; in ice_dpll_pin_sma_direction_set()
1526 return -EBUSY; in ice_dpll_pin_sma_direction_set()
1528 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_sma_direction_set()
1530 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_sma_direction_set()
1536 * ice_dpll_pin_sw_direction_get - callback for get SW pin direction
1546 * Context: Acquires and releases pf->dplls.lock
1548 * * 0 - success
1549 * * negative - error
1558 struct ice_pf *pf = p->pf; in ice_dpll_pin_sw_direction_get()
1561 return -EBUSY; in ice_dpll_pin_sw_direction_get()
1562 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_sw_direction_get()
1563 *direction = p->direction; in ice_dpll_pin_sw_direction_get()
1564 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_sw_direction_get()
1570 * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
1580 * Context: Acquires pf->dplls.lock
1582 * * 0 - success
1583 * * negative - error
1592 struct ice_pf *pf = p->pf; in ice_dpll_pin_phase_adjust_get()
1594 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
1595 *phase_adjust = p->phase_adjust; in ice_dpll_pin_phase_adjust_get()
1596 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
1602 * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
1614 * Context: Acquires pf->dplls.lock
1616 * * 0 - success
1617 * * negative - error
1628 struct ice_pf *pf = d->pf; in ice_dpll_pin_phase_adjust_set()
1633 return -EBUSY; in ice_dpll_pin_phase_adjust_set()
1635 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
1639 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) in ice_dpll_pin_phase_adjust_set()
1641 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) in ice_dpll_pin_phase_adjust_set()
1643 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en, in ice_dpll_pin_phase_adjust_set()
1648 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN) in ice_dpll_pin_phase_adjust_set()
1650 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) in ice_dpll_pin_phase_adjust_set()
1652 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0, in ice_dpll_pin_phase_adjust_set()
1656 ret = -EINVAL; in ice_dpll_pin_phase_adjust_set()
1659 p->phase_adjust = phase_adjust; in ice_dpll_pin_phase_adjust_set()
1660 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
1665 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_phase_adjust_set()
1666 phase_adjust, p->idx, d->dpll_idx); in ice_dpll_pin_phase_adjust_set()
1672 * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
1683 * Context: Calls a function which acquires and releases pf->dplls.lock
1685 * * 0 - success
1686 * * negative - error
1700 * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
1711 * Context: Calls a function which acquires pf->dplls.lock
1713 * * 0 - success
1714 * * negative - error
1728 * ice_dpll_sw_phase_adjust_get - callback for get SW pin phase adjust
1739 * Context: Calls a function which acquires and releases pf->dplls.lock
1741 * * 0 - success
1742 * * negative - error
1752 if (p->direction == DPLL_PIN_DIRECTION_INPUT) in ice_dpll_sw_phase_adjust_get()
1753 return ice_dpll_pin_phase_adjust_get(p->input->pin, p->input, in ice_dpll_sw_phase_adjust_get()
1757 return ice_dpll_pin_phase_adjust_get(p->output->pin, p->output, in ice_dpll_sw_phase_adjust_get()
1763 * ice_dpll_sw_phase_adjust_set - callback for set SW pin phase adjust value
1774 * Context: Calls a function which acquires and releases pf->dplls.lock
1776 * * 0 - success
1777 * * negative - error
1787 if (!p->active) { in ice_dpll_sw_phase_adjust_set()
1789 return -EINVAL; in ice_dpll_sw_phase_adjust_set()
1791 if (p->direction == DPLL_PIN_DIRECTION_INPUT) in ice_dpll_sw_phase_adjust_set()
1792 return ice_dpll_pin_phase_adjust_set(p->input->pin, p->input, in ice_dpll_sw_phase_adjust_set()
1797 return ice_dpll_pin_phase_adjust_set(p->output->pin, p->output, in ice_dpll_sw_phase_adjust_set()
1807 * ice_dpll_phase_offset_get - callback for get dpll phase shift value
1818 * Context: Acquires pf->dplls.lock
1820 * * 0 - success
1821 * * negative - error
1830 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_get()
1832 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1833 if (d->active_input == pin || (p->input && in ice_dpll_phase_offset_get()
1834 d->active_input == p->input->pin)) in ice_dpll_phase_offset_get()
1835 *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1836 else if (d->phase_offset_monitor_period) in ice_dpll_phase_offset_get()
1837 *phase_offset = p->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1840 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1846 * ice_dpll_output_esync_set - callback for setting embedded sync
1851 * @freq: requested embedded sync frequency
1854 * Dpll subsystem callback. Handler for setting embedded sync frequency value
1857 * Context: Acquires pf->dplls.lock
1859 * * 0 - success
1860 * * negative - error
1869 struct ice_pf *pf = d->pf; in ice_dpll_output_esync_set()
1874 return -EBUSY; in ice_dpll_output_esync_set()
1875 mutex_lock(&pf->dplls.lock); in ice_dpll_output_esync_set()
1876 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN) in ice_dpll_output_esync_set()
1879 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) { in ice_dpll_output_esync_set()
1883 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, in ice_dpll_output_esync_set()
1887 if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)) { in ice_dpll_output_esync_set()
1891 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, in ice_dpll_output_esync_set()
1895 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_set()
1901 * ice_dpll_output_esync_get - callback for getting embedded sync config
1906 * @esync: on success holds embedded sync pin properties
1909 * Dpll subsystem callback. Handler for getting embedded sync frequency value
1912 * Context: Acquires pf->dplls.lock
1914 * * 0 - success
1915 * * negative - error
1925 struct ice_pf *pf = d->pf; in ice_dpll_output_esync_get()
1928 return -EBUSY; in ice_dpll_output_esync_get()
1929 mutex_lock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1930 if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY) || in ice_dpll_output_esync_get()
1931 p->freq != DPLL_PIN_FREQUENCY_10_MHZ) { in ice_dpll_output_esync_get()
1932 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1933 return -EOPNOTSUPP; in ice_dpll_output_esync_get()
1935 esync->range = ice_esync_range; in ice_dpll_output_esync_get()
1936 esync->range_num = ARRAY_SIZE(ice_esync_range); in ice_dpll_output_esync_get()
1937 if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) { in ice_dpll_output_esync_get()
1938 esync->freq = DPLL_PIN_FREQUENCY_1_HZ; in ice_dpll_output_esync_get()
1939 esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; in ice_dpll_output_esync_get()
1941 esync->freq = 0; in ice_dpll_output_esync_get()
1942 esync->pulse = 0; in ice_dpll_output_esync_get()
1944 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1950 * ice_dpll_input_esync_set - callback for setting embedded sync
1955 * @freq: requested embedded sync frequency
1958 * Dpll subsystem callback. Handler for setting embedded sync frequency value
1961 * Context: Acquires pf->dplls.lock
1963 * * 0 - success
1964 * * negative - error
1973 struct ice_pf *pf = d->pf; in ice_dpll_input_esync_set()
1978 return -EBUSY; in ice_dpll_input_esync_set()
1979 mutex_lock(&pf->dplls.lock); in ice_dpll_input_esync_set()
1980 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) in ice_dpll_input_esync_set()
1983 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { in ice_dpll_input_esync_set()
1987 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, in ice_dpll_input_esync_set()
1991 if (!(p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)) { in ice_dpll_input_esync_set()
1995 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, in ice_dpll_input_esync_set()
1999 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_set()
2005 * ice_dpll_input_esync_get - callback for getting embedded sync config
2010 * @esync: on success holds embedded sync pin properties
2013 * Dpll subsystem callback. Handler for getting embedded sync frequency value
2016 * Context: Acquires pf->dplls.lock
2018 * * 0 - success
2019 * * negative - error
2029 struct ice_pf *pf = d->pf; in ice_dpll_input_esync_get()
2032 return -EBUSY; in ice_dpll_input_esync_get()
2033 mutex_lock(&pf->dplls.lock); in ice_dpll_input_esync_get()
2034 if (!(p->status & ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP) || in ice_dpll_input_esync_get()
2035 p->freq != DPLL_PIN_FREQUENCY_10_MHZ) { in ice_dpll_input_esync_get()
2036 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_get()
2037 return -EOPNOTSUPP; in ice_dpll_input_esync_get()
2039 esync->range = ice_esync_range; in ice_dpll_input_esync_get()
2040 esync->range_num = ARRAY_SIZE(ice_esync_range); in ice_dpll_input_esync_get()
2041 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { in ice_dpll_input_esync_get()
2042 esync->freq = DPLL_PIN_FREQUENCY_1_HZ; in ice_dpll_input_esync_get()
2043 esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; in ice_dpll_input_esync_get()
2045 esync->freq = 0; in ice_dpll_input_esync_get()
2046 esync->pulse = 0; in ice_dpll_input_esync_get()
2048 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_get()
2054 * ice_dpll_sw_esync_set - callback for setting embedded sync on SW pin
2059 * @freq: requested embedded sync frequency
2062 * Dpll subsystem callback. Handler for setting embedded sync frequency value
2065 * Context: Calls a function which acquires and releases pf->dplls.lock
2067 * * 0 - success
2068 * * negative - error
2077 if (!p->active) { in ice_dpll_sw_esync_set()
2079 return -EINVAL; in ice_dpll_sw_esync_set()
2081 if (p->direction == DPLL_PIN_DIRECTION_INPUT) in ice_dpll_sw_esync_set()
2082 return ice_dpll_input_esync_set(p->input->pin, p->input, dpll, in ice_dpll_sw_esync_set()
2085 return ice_dpll_output_esync_set(p->output->pin, p->output, in ice_dpll_sw_esync_set()
2090 * ice_dpll_sw_esync_get - callback for getting embedded sync on SW pin
2095 * @esync: on success holds embedded sync frequency and properties
2098 * Dpll subsystem callback. Handler for getting embedded sync frequency value
2101 * Context: Calls a function which acquires and releases pf->dplls.lock
2103 * * 0 - success
2104 * * negative - error
2114 if (p->direction == DPLL_PIN_DIRECTION_INPUT) in ice_dpll_sw_esync_get()
2115 return ice_dpll_input_esync_get(p->input->pin, p->input, dpll, in ice_dpll_sw_esync_get()
2118 return ice_dpll_output_esync_get(p->output->pin, p->output, in ice_dpll_sw_esync_get()
2124 * ice_dpll_input_ref_sync_set - callback for setting reference sync feature
2127 * @ref_pin: pin pointer for reference sync pair
2129 * @state: requested state for reference sync for pin pair
2132 * Dpll subsystem callback. Handler for setting reference sync frequency
2135 * Context: Acquires and releases pf->dplls.lock
2137 * * 0 - success
2138 * * negative - error
2147 struct ice_pf *pf = p->pf; in ice_dpll_input_ref_sync_set()
2152 return -EBUSY; in ice_dpll_input_ref_sync_set()
2153 mutex_lock(&pf->dplls.lock); in ice_dpll_input_ref_sync_set()
2155 if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) in ice_dpll_input_ref_sync_set()
2159 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, flags_en, 0, 0); in ice_dpll_input_ref_sync_set()
2163 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_ref_sync_set()
2169 * ice_dpll_input_ref_sync_get - callback for getting reference sync config
2172 * @ref_pin: pin pointer for reference sync pair
2174 * @state: on success holds reference sync state for pin pair
2177 * Dpll subsystem callback. Handler for setting reference sync frequency
2180 * Context: Acquires and releases pf->dplls.lock
2182 * * 0 - success
2183 * * negative - error
2192 struct ice_pf *pf = p->pf; in ice_dpll_input_ref_sync_get()
2195 return -EBUSY; in ice_dpll_input_ref_sync_get()
2196 mutex_lock(&pf->dplls.lock); in ice_dpll_input_ref_sync_get()
2197 if (p->flags[0] & ICE_AQC_CGU_IN_CFG_FLG2_REFSYNC_EN) in ice_dpll_input_ref_sync_get()
2201 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_ref_sync_get()
2207 * ice_dpll_sw_input_ref_sync_set - callback for setting reference sync feature
2210 * @ref_pin: pin pointer for reference sync pair
2212 * @state: requested state for reference sync for pin pair
2215 * Dpll subsystem callback. Handler for setting reference sync
2216 * feature for input pins.
2218 * Context: Calls a function which acquires and releases pf->dplls.lock
2220 * * 0 - success
2221 * * negative - error
2232 return ice_dpll_input_ref_sync_set(pin, p->input, ref_pin, ref_pin_priv, in ice_dpll_sw_input_ref_sync_set()
2237 * ice_dpll_sw_input_ref_sync_get - callback for getting reference sync config
2240 * @ref_pin: pin pointer for reference sync pair
2242 * @state: on success holds reference sync state for pin pair
2245 * Dpll subsystem callback. Handler for setting reference sync feature for
2246 * input pins.
2248 * Context: Calls a function which acquires and releases pf->dplls.lock
2250 * * 0 - success
2251 * * negative - error
2262 return ice_dpll_input_ref_sync_get(pin, p->input, ref_pin, ref_pin_priv, in ice_dpll_sw_input_ref_sync_get()
2267 * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
2277 * Context: Acquires pf->dplls.lock
2279 * * 0 - success
2280 * * negative - failure
2291 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_set()
2292 int ret = -EINVAL; in ice_dpll_rclk_state_on_pin_set()
2296 return -EBUSY; in ice_dpll_rclk_state_on_pin_set()
2298 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
2299 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_set()
2300 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_set()
2303 if ((enable && p->state[hw_idx] == DPLL_PIN_STATE_CONNECTED) || in ice_dpll_rclk_state_on_pin_set()
2304 (!enable && p->state[hw_idx] == DPLL_PIN_STATE_DISCONNECTED)) { in ice_dpll_rclk_state_on_pin_set()
2307 p->idx, state, parent->idx); in ice_dpll_rclk_state_on_pin_set()
2310 ret = ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable, in ice_dpll_rclk_state_on_pin_set()
2311 &p->freq); in ice_dpll_rclk_state_on_pin_set()
2316 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_rclk_state_on_pin_set()
2317 state, p->idx, parent->idx); in ice_dpll_rclk_state_on_pin_set()
2319 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
2325 * ice_dpll_rclk_state_on_pin_get - get a state of rclk pin
2335 * Context: Acquires pf->dplls.lock
2337 * * 0 - success
2338 * * negative - failure
2348 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_get()
2349 int ret = -EINVAL; in ice_dpll_rclk_state_on_pin_get()
2353 return -EBUSY; in ice_dpll_rclk_state_on_pin_get()
2355 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
2356 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_get()
2357 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_get()
2365 *state = p->state[hw_idx]; in ice_dpll_rclk_state_on_pin_get()
2368 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
2452 * ice_generate_clock_id - generates unique clock_id for registering dpll.
2462 return pci_get_dsn(pf->pdev); in ice_generate_clock_id()
2466 * ice_dpll_notify_changes - notify dpll subsystem about changes
2475 if (d->prev_dpll_state != d->dpll_state) { in ice_dpll_notify_changes()
2476 d->prev_dpll_state = d->dpll_state; in ice_dpll_notify_changes()
2477 dpll_device_change_ntf(d->dpll); in ice_dpll_notify_changes()
2479 if (d->prev_input != d->active_input) { in ice_dpll_notify_changes()
2480 if (d->prev_input) in ice_dpll_notify_changes()
2481 dpll_pin_change_ntf(d->prev_input); in ice_dpll_notify_changes()
2482 d->prev_input = d->active_input; in ice_dpll_notify_changes()
2483 if (d->active_input) { in ice_dpll_notify_changes()
2484 dpll_pin_change_ntf(d->active_input); in ice_dpll_notify_changes()
2488 if (d->prev_phase_offset != d->phase_offset) { in ice_dpll_notify_changes()
2489 d->prev_phase_offset = d->phase_offset; in ice_dpll_notify_changes()
2490 if (!pin_notified && d->active_input) in ice_dpll_notify_changes()
2491 dpll_pin_change_ntf(d->active_input); in ice_dpll_notify_changes()
2496 * ice_dpll_is_pps_phase_monitor - check if dpll capable of phase offset monitor
2500 * phase offset monitoring on all the input pins on PPS dpll.
2503 * * true - PPS dpll phase offset monitoring is supported
2504 * * false - PPS dpll phase offset monitoring is not supported
2509 int ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas, in ice_dpll_is_pps_phase_monitor()
2512 if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_ESRCH) in ice_dpll_is_pps_phase_monitor()
2519 * ice_dpll_pins_notify_mask - notify dpll subsystem about bulk pin changes
2520 * @pins: array of ice_dpll_pin pointers registered within dpll subsystem
2521 * @pin_num: number of pins
2524 * Iterate over array of pins and call dpll subsystem pin notify if
2527 * Context: Must be called while pf->dplls.lock is released.
2529 static void ice_dpll_pins_notify_mask(struct ice_dpll_pin *pins, in ice_dpll_pins_notify_mask() argument
2537 dpll_pin_change_ntf(pins[i].pin); in ice_dpll_pins_notify_mask()
2541 * ice_dpll_pps_update_phase_offsets - update phase offset measurements
2546 * input pins array. On success phase_offset_pins_updated - fills bitmask of
2547 * updated input pin indexes, pins shall be notified.
2549 * Context: Shall be called with pf->dplls.lock being locked.
2551 * * 0 - success or no data available
2552 * * negative - AQ failure
2563 ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas, in ice_dpll_pps_update_phase_offsets()
2565 if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_EAGAIN) { in ice_dpll_pps_update_phase_offsets()
2571 libie_aq_str(pf->hw.adminq.sq_last_status)); in ice_dpll_pps_update_phase_offsets()
2574 for (i = 0; i < pf->dplls.num_inputs; i++) { in ice_dpll_pps_update_phase_offsets()
2575 p = &pf->dplls.inputs[i]; in ice_dpll_pps_update_phase_offsets()
2583 (ICE_CGU_INPUT_PHASE_OFFSET_BYTES - 1 - j); in ice_dpll_pps_update_phase_offsets()
2587 if (p->phase_offset != phase_offset) { in ice_dpll_pps_update_phase_offsets()
2590 p->idx, p->phase_offset, phase_offset); in ice_dpll_pps_update_phase_offsets()
2591 p->phase_offset = phase_offset; in ice_dpll_pps_update_phase_offsets()
2600 * ice_dpll_update_state - update dpll state
2607 * Context: Called by kworker under pf->dplls.lock
2609 * * 0 - success
2610 * * negative - AQ failure
2618 ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state, in ice_dpll_update_state()
2619 &d->input_idx, &d->ref_state, &d->eec_mode, in ice_dpll_update_state()
2620 &d->phase_offset, &d->dpll_state); in ice_dpll_update_state()
2624 d->dpll_idx, d->prev_input_idx, d->input_idx, in ice_dpll_update_state()
2625 d->dpll_state, d->prev_dpll_state, d->mode); in ice_dpll_update_state()
2629 d->dpll_idx, ret, in ice_dpll_update_state()
2630 libie_aq_str(pf->hw.adminq.sq_last_status)); in ice_dpll_update_state()
2634 if (d->dpll_state == DPLL_LOCK_STATUS_LOCKED || in ice_dpll_update_state()
2635 d->dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ) in ice_dpll_update_state()
2636 d->active_input = pf->dplls.inputs[d->input_idx].pin; in ice_dpll_update_state()
2637 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
2641 if (d->dpll_state == DPLL_LOCK_STATUS_HOLDOVER || in ice_dpll_update_state()
2642 d->dpll_state == DPLL_LOCK_STATUS_UNLOCKED) { in ice_dpll_update_state()
2643 d->active_input = NULL; in ice_dpll_update_state()
2644 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) in ice_dpll_update_state()
2645 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
2646 d->prev_input_idx = ICE_DPLL_PIN_IDX_INVALID; in ice_dpll_update_state()
2647 d->input_idx = ICE_DPLL_PIN_IDX_INVALID; in ice_dpll_update_state()
2652 } else if (d->input_idx != d->prev_input_idx) { in ice_dpll_update_state()
2653 if (d->prev_input_idx != ICE_DPLL_PIN_IDX_INVALID) { in ice_dpll_update_state()
2654 p = &pf->dplls.inputs[d->prev_input_idx]; in ice_dpll_update_state()
2659 if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) { in ice_dpll_update_state()
2660 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
2661 d->active_input = p->pin; in ice_dpll_update_state()
2666 d->prev_input_idx = d->input_idx; in ice_dpll_update_state()
2673 * ice_dpll_periodic_work - DPLLs periodic worker
2677 * Context: Holds pf->dplls.lock
2683 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_periodic_work()
2684 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_periodic_work()
2688 if (ice_is_reset_in_progress(pf->state)) in ice_dpll_periodic_work()
2690 mutex_lock(&pf->dplls.lock); in ice_dpll_periodic_work()
2691 d->periodic_counter++; in ice_dpll_periodic_work()
2695 if (!ret && dp->phase_offset_monitor_period && in ice_dpll_periodic_work()
2696 d->periodic_counter % dp->phase_offset_monitor_period == 0) in ice_dpll_periodic_work()
2699 d->cgu_state_acq_err_num++; in ice_dpll_periodic_work()
2701 if (d->cgu_state_acq_err_num > in ice_dpll_periodic_work()
2705 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
2709 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
2713 ice_dpll_pins_notify_mask(d->inputs, d->num_inputs, in ice_dpll_periodic_work()
2718 kthread_queue_delayed_work(d->kworker, &d->work, in ice_dpll_periodic_work()
2724 * ice_dpll_init_ref_sync_inputs - initialize reference sync pin pairs
2727 * Read DPLL TLV capabilities and initialize reference sync pin pairs in
2731 * * 0 - success or nothing to do (no ref-sync tlv are present)
2732 * * negative - AQ failure
2736 struct ice_dpll_pin *inputs = pf->dplls.inputs; in ice_dpll_init_ref_sync_inputs()
2737 struct ice_hw *hw = &pf->hw; in ice_dpll_init_ref_sync_inputs()
2791 if (hw->device_id == ICE_DEV_ID_E810C_SFP && in ice_dpll_init_ref_sync_inputs()
2793 offset = -ICE_DPLL_E810C_SFP_NC_PINS; in ice_dpll_init_ref_sync_inputs()
2797 return -ERANGE; in ice_dpll_init_ref_sync_inputs()
2806 * ice_dpll_release_pins - release pins resources from dpll subsystem
2807 * @pins: pointer to pins array
2808 * @count: number of pins
2810 * Release resources of given pins array in the dpll subsystem.
2812 static void ice_dpll_release_pins(struct ice_dpll_pin *pins, int count) in ice_dpll_release_pins() argument
2817 dpll_pin_put(pins[i].pin); in ice_dpll_release_pins()
2821 * ice_dpll_get_pins - get pins from dpll subsystem
2823 * @pins: pointer to pins array
2825 * @count: number of pins
2828 * Get pins - allocate - in dpll subsystem, store them in pin field of given
2829 * pins array.
2832 * * 0 - success
2833 * * negative - allocation failure reason
2836 ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, in ice_dpll_get_pins() argument
2842 pins[i].pin = dpll_pin_get(clock_id, i + start_idx, THIS_MODULE, in ice_dpll_get_pins()
2843 &pins[i].prop); in ice_dpll_get_pins()
2844 if (IS_ERR(pins[i].pin)) { in ice_dpll_get_pins()
2845 ret = PTR_ERR(pins[i].pin); in ice_dpll_get_pins()
2853 while (--i >= 0) in ice_dpll_get_pins()
2854 dpll_pin_put(pins[i].pin); in ice_dpll_get_pins()
2859 * ice_dpll_unregister_pins - unregister pins from a dpll
2861 * @pins: pointer to pins array
2862 * @ops: callback ops registered with the pins
2863 * @count: number of pins
2865 * Unregister pins of a given array of pins from given dpll device registered in
2869 ice_dpll_unregister_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins, in ice_dpll_unregister_pins() argument
2875 if (!pins[i].hidden) in ice_dpll_unregister_pins()
2876 dpll_pin_unregister(dpll, pins[i].pin, ops, &pins[i]); in ice_dpll_unregister_pins()
2880 * ice_dpll_pin_ref_sync_register - register reference sync pins
2881 * @pins: pointer to pins array
2882 * @count: number of pins
2884 * Register reference sync pins in dpll subsystem.
2887 * * 0 - success
2888 * * negative - registration failure reason
2891 ice_dpll_pin_ref_sync_register(struct ice_dpll_pin *pins, int count) in ice_dpll_pin_ref_sync_register() argument
2896 if (!pins[i].hidden && pins[i].ref_sync) { in ice_dpll_pin_ref_sync_register()
2897 int j = pins[i].ref_sync; in ice_dpll_pin_ref_sync_register()
2899 ret = dpll_pin_ref_sync_pair_add(pins[i].pin, in ice_dpll_pin_ref_sync_register()
2900 pins[j].pin); in ice_dpll_pin_ref_sync_register()
2910 * ice_dpll_register_pins - register pins with a dpll
2911 * @dpll: dpll pointer to register pins with
2912 * @pins: pointer to pins array
2913 * @ops: callback ops registered with the pins
2914 * @count: number of pins
2916 * Register pins of a given array with given dpll in dpll subsystem.
2919 * * 0 - success
2920 * * negative - registration failure reason
2923 ice_dpll_register_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins, in ice_dpll_register_pins() argument
2929 if (!pins[i].hidden) { in ice_dpll_register_pins()
2930 ret = dpll_pin_register(dpll, pins[i].pin, ops, &pins[i]); in ice_dpll_register_pins()
2939 while (--i >= 0) in ice_dpll_register_pins()
2940 if (!pins[i].hidden) in ice_dpll_register_pins()
2941 dpll_pin_unregister(dpll, pins[i].pin, ops, &pins[i]); in ice_dpll_register_pins()
2946 * ice_dpll_deinit_direct_pins - deinitialize direct pins
2948 * @pins: pointer to pins array
2949 * @count: number of pins
2950 * @ops: callback ops registered with the pins
2954 * If cgu is owned unregister pins from given dplls.
2955 * Release pins resources to the dpll subsystem.
2958 ice_dpll_deinit_direct_pins(bool cgu, struct ice_dpll_pin *pins, int count, in ice_dpll_deinit_direct_pins() argument
2964 ice_dpll_unregister_pins(first, pins, ops, count); in ice_dpll_deinit_direct_pins()
2965 ice_dpll_unregister_pins(second, pins, ops, count); in ice_dpll_deinit_direct_pins()
2967 ice_dpll_release_pins(pins, count); in ice_dpll_deinit_direct_pins()
2971 * ice_dpll_init_direct_pins - initialize direct pins
2974 * @pins: pointer to pins array
2976 * @count: number of pins
2977 * @ops: callback ops registered with the pins
2981 * Allocate directly connected pins of a given array in dpll subsystem.
2982 * If cgu is owned register allocated pins with given dplls.
2985 * * 0 - success
2986 * * negative - registration failure reason
2990 struct ice_dpll_pin *pins, int start_idx, int count, in ice_dpll_init_direct_pins() argument
2996 ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id); in ice_dpll_init_direct_pins()
3000 ret = ice_dpll_register_pins(first, pins, ops, count); in ice_dpll_init_direct_pins()
3003 ret = ice_dpll_register_pins(second, pins, ops, count); in ice_dpll_init_direct_pins()
3011 ice_dpll_unregister_pins(first, pins, ops, count); in ice_dpll_init_direct_pins()
3013 ice_dpll_release_pins(pins, count); in ice_dpll_init_direct_pins()
3018 * ice_dpll_deinit_rclk_pin - release rclk pin resources
3021 * Deregister rclk pin from parent pins and release resources in dpll subsystem.
3025 struct ice_dpll_pin *rclk = &pf->dplls.rclk; in ice_dpll_deinit_rclk_pin()
3030 for (i = 0; i < rclk->num_parents; i++) { in ice_dpll_deinit_rclk_pin()
3031 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin; in ice_dpll_deinit_rclk_pin()
3034 dpll_pin_on_pin_unregister(parent, rclk->pin, in ice_dpll_deinit_rclk_pin()
3037 if (WARN_ON_ONCE(!vsi || !vsi->netdev)) in ice_dpll_deinit_rclk_pin()
3039 dpll_netdev_pin_clear(vsi->netdev); in ice_dpll_deinit_rclk_pin()
3040 dpll_pin_put(rclk->pin); in ice_dpll_deinit_rclk_pin()
3044 * ice_dpll_init_rclk_pins - initialize recovered clock pin
3048 * @ops: callback ops registered with the pins
3055 * * 0 - success
3056 * * negative - registration failure reason
3066 if (WARN_ON((!vsi || !vsi->netdev))) in ice_dpll_init_rclk_pins()
3067 return -EINVAL; in ice_dpll_init_rclk_pins()
3069 pf->dplls.clock_id); in ice_dpll_init_rclk_pins()
3072 for (i = 0; i < pf->dplls.rclk.num_parents; i++) { in ice_dpll_init_rclk_pins()
3073 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin; in ice_dpll_init_rclk_pins()
3075 ret = -ENODEV; in ice_dpll_init_rclk_pins()
3078 ret = dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
3079 ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
3083 dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); in ice_dpll_init_rclk_pins()
3089 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin; in ice_dpll_init_rclk_pins()
3090 dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
3091 &ice_dpll_rclk_ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
3098 * ice_dpll_deinit_pins - deinitialize direct pins
3102 * If cgu is owned unregister directly connected pins from the dplls.
3103 * Release resources of directly connected pins from the dpll subsystem.
3107 struct ice_dpll_pin *outputs = pf->dplls.outputs; in ice_dpll_deinit_pins()
3108 struct ice_dpll_pin *inputs = pf->dplls.inputs; in ice_dpll_deinit_pins()
3109 int num_outputs = pf->dplls.num_outputs; in ice_dpll_deinit_pins()
3110 int num_inputs = pf->dplls.num_inputs; in ice_dpll_deinit_pins()
3111 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_pins()
3112 struct ice_dpll *de = &d->eec; in ice_dpll_deinit_pins()
3113 struct ice_dpll *dp = &d->pps; in ice_dpll_deinit_pins()
3117 ice_dpll_unregister_pins(dp->dpll, inputs, &ice_dpll_input_ops, in ice_dpll_deinit_pins()
3119 ice_dpll_unregister_pins(de->dpll, inputs, &ice_dpll_input_ops, in ice_dpll_deinit_pins()
3124 ice_dpll_unregister_pins(dp->dpll, outputs, in ice_dpll_deinit_pins()
3126 ice_dpll_unregister_pins(de->dpll, outputs, in ice_dpll_deinit_pins()
3129 if (!pf->dplls.generic) { in ice_dpll_deinit_pins()
3130 ice_dpll_deinit_direct_pins(cgu, pf->dplls.ufl, in ice_dpll_deinit_pins()
3133 pf->dplls.pps.dpll, in ice_dpll_deinit_pins()
3134 pf->dplls.eec.dpll); in ice_dpll_deinit_pins()
3135 ice_dpll_deinit_direct_pins(cgu, pf->dplls.sma, in ice_dpll_deinit_pins()
3138 pf->dplls.pps.dpll, in ice_dpll_deinit_pins()
3139 pf->dplls.eec.dpll); in ice_dpll_deinit_pins()
3145 * ice_dpll_init_pins - init pins and register pins with a dplls
3149 * Initialize directly connected pf's pins within pf's dplls in a Linux dpll
3153 * * 0 - success
3154 * * negative - initialization failure reason
3160 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, in ice_dpll_init_pins()
3161 pf->dplls.num_inputs, in ice_dpll_init_pins()
3163 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins()
3166 count = pf->dplls.num_inputs; in ice_dpll_init_pins()
3168 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, in ice_dpll_init_pins()
3170 pf->dplls.num_outputs, in ice_dpll_init_pins()
3172 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3173 pf->dplls.pps.dpll); in ice_dpll_init_pins()
3176 count += pf->dplls.num_outputs; in ice_dpll_init_pins()
3177 if (!pf->dplls.generic) { in ice_dpll_init_pins()
3178 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.sma, in ice_dpll_init_pins()
3182 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3183 pf->dplls.pps.dpll); in ice_dpll_init_pins()
3187 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.ufl, in ice_dpll_init_pins()
3191 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3192 pf->dplls.pps.dpll); in ice_dpll_init_pins()
3197 ret = ice_dpll_pin_ref_sync_register(pf->dplls.inputs, in ice_dpll_init_pins()
3198 pf->dplls.num_inputs); in ice_dpll_init_pins()
3201 ret = ice_dpll_pin_ref_sync_register(pf->dplls.sma, in ice_dpll_init_pins()
3206 count += pf->dplls.num_outputs + 2 * ICE_DPLL_PIN_SW_NUM; in ice_dpll_init_pins()
3208 ret = ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, count + pf->hw.pf_id, in ice_dpll_init_pins()
3215 ice_dpll_deinit_direct_pins(cgu, pf->dplls.ufl, in ice_dpll_init_pins()
3218 pf->dplls.pps.dpll, pf->dplls.eec.dpll); in ice_dpll_init_pins()
3220 ice_dpll_deinit_direct_pins(cgu, pf->dplls.sma, in ice_dpll_init_pins()
3223 pf->dplls.pps.dpll, pf->dplls.eec.dpll); in ice_dpll_init_pins()
3225 ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs, in ice_dpll_init_pins()
3226 pf->dplls.num_outputs, in ice_dpll_init_pins()
3227 &ice_dpll_output_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
3228 pf->dplls.eec.dpll); in ice_dpll_init_pins()
3230 ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs, in ice_dpll_init_pins()
3231 &ice_dpll_input_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
3232 pf->dplls.eec.dpll); in ice_dpll_init_pins()
3237 * ice_dpll_deinit_dpll - deinitialize dpll device
3249 dpll_device_unregister(d->dpll, d->ops, d); in ice_dpll_deinit_dpll()
3250 dpll_device_put(d->dpll); in ice_dpll_deinit_dpll()
3254 * ice_dpll_init_dpll - initialize dpll device in dpll subsystem
3264 * * 0 - success
3265 * * negative - initialization failure reason
3271 u64 clock_id = pf->dplls.clock_id; in ice_dpll_init_dpll()
3274 d->dpll = dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE); in ice_dpll_init_dpll()
3275 if (IS_ERR(d->dpll)) { in ice_dpll_init_dpll()
3276 ret = PTR_ERR(d->dpll); in ice_dpll_init_dpll()
3281 d->pf = pf; in ice_dpll_init_dpll()
3288 ret = dpll_device_register(d->dpll, type, ops, d); in ice_dpll_init_dpll()
3290 dpll_device_put(d->dpll); in ice_dpll_init_dpll()
3293 d->ops = ops; in ice_dpll_init_dpll()
3300 * ice_dpll_deinit_worker - deinitialize dpll kworker
3307 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_worker()
3309 kthread_cancel_delayed_work_sync(&d->work); in ice_dpll_deinit_worker()
3310 kthread_destroy_worker(d->kworker); in ice_dpll_deinit_worker()
3314 * ice_dpll_init_worker - Initialize DPLLs periodic worker
3319 * Context: Shall be called after pf->dplls.lock is initialized.
3321 * * 0 - success
3322 * * negative - create worker failure
3326 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_worker()
3329 kthread_init_delayed_work(&d->work, ice_dpll_periodic_work); in ice_dpll_init_worker()
3330 kworker = kthread_run_worker(0, "ice-dplls-%s", in ice_dpll_init_worker()
3334 d->kworker = kworker; in ice_dpll_init_worker()
3335 d->cgu_state_acq_err_num = 0; in ice_dpll_init_worker()
3336 kthread_queue_delayed_work(d->kworker, &d->work, 0); in ice_dpll_init_worker()
3342 * ice_dpll_phase_range_set - initialize phase adjust range helper
3344 * @phase_adj: a value to be used as min(-)/max(+) boundary
3349 range->min = -phase_adj; in ice_dpll_phase_range_set()
3350 range->max = phase_adj; in ice_dpll_phase_range_set()
3354 * ice_dpll_init_info_pins_generic - initializes generic pins info
3356 * @input: if input pins initialized
3358 * Init information for generic pins, cache them in PF's pins structures.
3361 * * 0 - success
3362 * * negative - init failure reason
3366 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_pins_generic()
3372 int i, pin_num, ret = -EINVAL; in ice_dpll_init_info_pins_generic()
3373 struct ice_dpll_pin *pins; in ice_dpll_init_info_pins_generic() local
3377 pin_num = pf->dplls.num_inputs; in ice_dpll_init_info_pins_generic()
3378 pins = pf->dplls.inputs; in ice_dpll_init_info_pins_generic()
3379 phase_adj_max = pf->dplls.input_phase_adj_max; in ice_dpll_init_info_pins_generic()
3383 pin_num = pf->dplls.num_outputs; in ice_dpll_init_info_pins_generic()
3384 pins = pf->dplls.outputs; in ice_dpll_init_info_pins_generic()
3385 phase_adj_max = pf->dplls.output_phase_adj_max; in ice_dpll_init_info_pins_generic()
3392 pins[i].idx = i; in ice_dpll_init_info_pins_generic()
3393 pins[i].prop.board_label = labels[i]; in ice_dpll_init_info_pins_generic()
3394 ice_dpll_phase_range_set(&pins[i].prop.phase_range, in ice_dpll_init_info_pins_generic()
3396 pins[i].prop.capabilities = cap; in ice_dpll_init_info_pins_generic()
3397 pins[i].pf = pf; in ice_dpll_init_info_pins_generic()
3398 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); in ice_dpll_init_info_pins_generic()
3401 if (input && pins[i].freq == ICE_DPLL_PIN_GEN_RCLK_FREQ) in ice_dpll_init_info_pins_generic()
3402 pins[i].prop.type = DPLL_PIN_TYPE_MUX; in ice_dpll_init_info_pins_generic()
3404 pins[i].prop.type = DPLL_PIN_TYPE_EXT; in ice_dpll_init_info_pins_generic()
3407 ret = ice_aq_get_cgu_ref_prio(&pf->hw, de->dpll_idx, i, in ice_dpll_init_info_pins_generic()
3408 &de->input_prio[i]); in ice_dpll_init_info_pins_generic()
3411 ret = ice_aq_get_cgu_ref_prio(&pf->hw, dp->dpll_idx, i, in ice_dpll_init_info_pins_generic()
3412 &dp->input_prio[i]); in ice_dpll_init_info_pins_generic()
3421 * ice_dpll_init_info_direct_pins - initializes direct pins info
3423 * @pin_type: type of pins being initialized
3425 * Init information for directly connected pins, cache them in pf's pins
3429 * * 0 - success
3430 * * negative - init failure reason
3436 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_direct_pins()
3437 int num_pins, i, ret = -EINVAL; in ice_dpll_init_info_direct_pins()
3438 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info_direct_pins()
3439 struct ice_dpll_pin *pins; in ice_dpll_init_info_direct_pins() local
3447 pins = pf->dplls.inputs; in ice_dpll_init_info_direct_pins()
3448 num_pins = pf->dplls.num_inputs; in ice_dpll_init_info_direct_pins()
3449 phase_adj_max = pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
3453 pins = pf->dplls.outputs; in ice_dpll_init_info_direct_pins()
3454 num_pins = pf->dplls.num_outputs; in ice_dpll_init_info_direct_pins()
3455 phase_adj_max = pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
3459 return -EINVAL; in ice_dpll_init_info_direct_pins()
3462 pf->dplls.generic = true; in ice_dpll_init_info_direct_pins()
3468 pins[i].idx = i; in ice_dpll_init_info_direct_pins()
3469 pins[i].prop.board_label = ice_cgu_get_pin_name(hw, i, input); in ice_dpll_init_info_direct_pins()
3470 pins[i].prop.type = ice_cgu_get_pin_type(hw, i, input); in ice_dpll_init_info_direct_pins()
3472 ret = ice_aq_get_cgu_ref_prio(hw, de->dpll_idx, i, in ice_dpll_init_info_direct_pins()
3473 &de->input_prio[i]); in ice_dpll_init_info_direct_pins()
3476 ret = ice_aq_get_cgu_ref_prio(hw, dp->dpll_idx, i, in ice_dpll_init_info_direct_pins()
3477 &dp->input_prio[i]); in ice_dpll_init_info_direct_pins()
3483 pins[i].hidden = true; in ice_dpll_init_info_direct_pins()
3489 pins[i].hidden = true; in ice_dpll_init_info_direct_pins()
3491 ice_dpll_phase_range_set(&pins[i].prop.phase_range, in ice_dpll_init_info_direct_pins()
3493 pins[i].prop.capabilities = caps; in ice_dpll_init_info_direct_pins()
3494 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); in ice_dpll_init_info_direct_pins()
3497 pins[i].prop.freq_supported = in ice_dpll_init_info_direct_pins()
3499 pins[i].prop.freq_supported_num = freq_supp_num; in ice_dpll_init_info_direct_pins()
3500 pins[i].pf = pf; in ice_dpll_init_info_direct_pins()
3509 * ice_dpll_init_info_rclk_pin - initializes rclk pin information
3512 * Init information for rclk pin, cache them in pf->dplls.rclk.
3515 * * 0 - success
3516 * * negative - init failure reason
3520 struct ice_dpll_pin *pin = &pf->dplls.rclk; in ice_dpll_init_info_rclk_pin()
3522 pin->prop.type = DPLL_PIN_TYPE_SYNCE_ETH_PORT; in ice_dpll_init_info_rclk_pin()
3523 pin->prop.capabilities |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; in ice_dpll_init_info_rclk_pin()
3524 pin->pf = pf; in ice_dpll_init_info_rclk_pin()
3531 * ice_dpll_init_info_sw_pins - initializes software controlled pin information
3534 * Init information for software controlled pins, cache them in
3535 * pf->dplls.sma and pf->dplls.ufl.
3538 * * 0 - success
3539 * * negative - init failure reason
3544 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_info_sw_pins()
3549 if (pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) in ice_dpll_init_info_sw_pins()
3551 phase_adj_max = max(d->input_phase_adj_max, d->output_phase_adj_max); in ice_dpll_init_info_sw_pins()
3554 pin = &d->sma[i]; in ice_dpll_init_info_sw_pins()
3555 pin->idx = i; in ice_dpll_init_info_sw_pins()
3556 pin->prop.type = DPLL_PIN_TYPE_EXT; in ice_dpll_init_info_sw_pins()
3558 pin->prop.freq_supported = in ice_dpll_init_info_sw_pins()
3559 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, in ice_dpll_init_info_sw_pins()
3561 pin->prop.freq_supported_num = freq_supp_num; in ice_dpll_init_info_sw_pins()
3562 pin->prop.capabilities = in ice_dpll_init_info_sw_pins()
3566 pin->pf = pf; in ice_dpll_init_info_sw_pins()
3567 pin->prop.board_label = ice_dpll_sw_pin_sma[i]; in ice_dpll_init_info_sw_pins()
3568 pin->input = &d->inputs[pin_abs_idx]; in ice_dpll_init_info_sw_pins()
3569 if (pin->input->ref_sync) in ice_dpll_init_info_sw_pins()
3570 pin->ref_sync = pin->input->ref_sync - pin_abs_idx; in ice_dpll_init_info_sw_pins()
3571 pin->output = &d->outputs[ICE_DPLL_PIN_SW_OUTPUT_ABS(i)]; in ice_dpll_init_info_sw_pins()
3572 ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); in ice_dpll_init_info_sw_pins()
3575 pin = &d->ufl[i]; in ice_dpll_init_info_sw_pins()
3576 pin->idx = i; in ice_dpll_init_info_sw_pins()
3577 pin->prop.type = DPLL_PIN_TYPE_EXT; in ice_dpll_init_info_sw_pins()
3578 pin->prop.capabilities = caps; in ice_dpll_init_info_sw_pins()
3579 pin->pf = pf; in ice_dpll_init_info_sw_pins()
3580 pin->prop.board_label = ice_dpll_sw_pin_ufl[i]; in ice_dpll_init_info_sw_pins()
3582 pin->direction = DPLL_PIN_DIRECTION_OUTPUT; in ice_dpll_init_info_sw_pins()
3584 pin->prop.freq_supported = in ice_dpll_init_info_sw_pins()
3585 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, in ice_dpll_init_info_sw_pins()
3588 pin->prop.freq_supported_num = freq_supp_num; in ice_dpll_init_info_sw_pins()
3589 pin->input = NULL; in ice_dpll_init_info_sw_pins()
3590 pin->output = &d->outputs[pin_abs_idx]; in ice_dpll_init_info_sw_pins()
3592 pin->direction = DPLL_PIN_DIRECTION_INPUT; in ice_dpll_init_info_sw_pins()
3595 pin->output = NULL; in ice_dpll_init_info_sw_pins()
3596 pin->input = &d->inputs[pin_abs_idx]; in ice_dpll_init_info_sw_pins()
3597 pin->prop.freq_supported = in ice_dpll_init_info_sw_pins()
3598 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, in ice_dpll_init_info_sw_pins()
3600 pin->prop.freq_supported_num = freq_supp_num; in ice_dpll_init_info_sw_pins()
3601 pin->prop.capabilities = in ice_dpll_init_info_sw_pins()
3605 ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max); in ice_dpll_init_info_sw_pins()
3616 * ice_dpll_init_pins_info - init pins info wrapper
3618 * @pin_type: type of pins being initialized
3623 * * 0 - success
3624 * * negative - init failure reason
3638 return -EINVAL; in ice_dpll_init_pins_info()
3643 * ice_dpll_deinit_info - release memory allocated for pins info
3646 * Release memory allocated for pins by ice_dpll_init_info function.
3650 kfree(pf->dplls.inputs); in ice_dpll_deinit_info()
3651 kfree(pf->dplls.outputs); in ice_dpll_deinit_info()
3652 kfree(pf->dplls.eec.input_prio); in ice_dpll_deinit_info()
3653 kfree(pf->dplls.pps.input_prio); in ice_dpll_deinit_info()
3657 * ice_dpll_init_info - prepare pf's dpll information structure
3661 * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
3664 * * 0 - success
3665 * * negative - init failure reason
3670 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_init_info()
3671 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_init_info()
3672 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_info()
3673 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info()
3676 d->clock_id = ice_generate_clock_id(pf); in ice_dpll_init_info()
3681 ret, libie_aq_str(hw->adminq.sq_last_status)); in ice_dpll_init_info()
3685 de->dpll_idx = abilities.eec_dpll_idx; in ice_dpll_init_info()
3686 dp->dpll_idx = abilities.pps_dpll_idx; in ice_dpll_init_info()
3687 d->num_inputs = abilities.num_inputs; in ice_dpll_init_info()
3688 d->num_outputs = abilities.num_outputs; in ice_dpll_init_info()
3689 d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj) & in ice_dpll_init_info()
3691 d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj) & in ice_dpll_init_info()
3694 alloc_size = sizeof(*d->inputs) * d->num_inputs; in ice_dpll_init_info()
3695 d->inputs = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
3696 if (!d->inputs) in ice_dpll_init_info()
3697 return -ENOMEM; in ice_dpll_init_info()
3699 alloc_size = sizeof(*de->input_prio) * d->num_inputs; in ice_dpll_init_info()
3700 de->input_prio = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
3701 if (!de->input_prio) in ice_dpll_init_info()
3702 return -ENOMEM; in ice_dpll_init_info()
3704 dp->input_prio = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
3705 if (!dp->input_prio) in ice_dpll_init_info()
3706 return -ENOMEM; in ice_dpll_init_info()
3713 alloc_size = sizeof(*d->outputs) * d->num_outputs; in ice_dpll_init_info()
3714 d->outputs = kzalloc(alloc_size, GFP_KERNEL); in ice_dpll_init_info()
3715 if (!d->outputs) { in ice_dpll_init_info()
3716 ret = -ENOMEM; in ice_dpll_init_info()
3728 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, in ice_dpll_init_info()
3729 &pf->dplls.rclk.num_parents); in ice_dpll_init_info()
3732 for (i = 0; i < pf->dplls.rclk.num_parents; i++) in ice_dpll_init_info()
3733 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; in ice_dpll_init_info()
3737 de->mode = DPLL_MODE_AUTOMATIC; in ice_dpll_init_info()
3738 dp->mode = DPLL_MODE_AUTOMATIC; in ice_dpll_init_info()
3741 "%s - success, inputs:%u, outputs:%u rclk-parents:%u\n", in ice_dpll_init_info()
3742 __func__, d->num_inputs, d->num_outputs, d->rclk.num_parents); in ice_dpll_init_info()
3748 "%s - fail: d->inputs:%p, de->input_prio:%p, dp->input_prio:%p, d->outputs:%p\n", in ice_dpll_init_info()
3749 __func__, d->inputs, de->input_prio, in ice_dpll_init_info()
3750 dp->input_prio, d->outputs); in ice_dpll_init_info()
3756 * ice_dpll_deinit - Disable the driver/HW support for dpll subsystem
3764 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
3770 clear_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_deinit()
3775 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_deinit()
3776 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_deinit()
3778 mutex_destroy(&pf->dplls.lock); in ice_dpll_deinit()
3782 * ice_dpll_init - initialize support for dpll subsystem
3785 * Set up the device dplls, register them and pins connected within Linux dpll
3789 * Context: Initializes pf->dplls.lock mutex.
3794 struct ice_dplls *d = &pf->dplls; in ice_dpll_init()
3797 mutex_init(&d->lock); in ice_dpll_init()
3801 err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC); in ice_dpll_init()
3804 err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS); in ice_dpll_init()
3815 set_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_init()
3822 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_init()
3824 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_init()
3828 mutex_destroy(&d->lock); in ice_dpll_init()