Lines Matching full:pf
41 * @pf: private board structure
50 static bool ice_dpll_is_reset(struct ice_pf *pf, struct netlink_ext_ack *extack) in ice_dpll_is_reset() argument
52 if (ice_is_reset_in_progress(pf->state)) { in ice_dpll_is_reset()
53 NL_SET_ERR_MSG(extack, "PF reset in progress"); in ice_dpll_is_reset()
61 * @pf: private board structure
69 * Context: Called under pf->dplls.lock
75 ice_dpll_pin_freq_set(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_pin_freq_set() argument
85 ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
90 ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
100 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_freq_set()
121 * Context: Acquires pf->dplls.lock
135 struct ice_pf *pf = d->pf; in ice_dpll_frequency_set() local
138 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_frequency_set()
141 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
142 ret = ice_dpll_pin_freq_set(pf, p, pin_type, frequency, extack); in ice_dpll_frequency_set()
143 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
159 * Context: Calls a function which acquires pf->dplls.lock
184 * Context: Calls a function which acquires pf->dplls.lock
210 * Context: Acquires pf->dplls.lock
223 struct ice_pf *pf = d->pf; in ice_dpll_frequency_get() local
225 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
227 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
243 * Context: Calls a function which acquires pf->dplls.lock
268 * Context: Calls a function which acquires pf->dplls.lock
292 * Context: Called under pf->dplls.lock
341 * Context: Called under pf->dplls.lock
379 * @pf: private board struct
388 * Context: Called under pf->dplls.lock
394 ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_pin_state_update() argument
403 ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, &pin->status, in ice_dpll_pin_state_update()
410 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
411 pin->pin == pf->dplls.eec.active_input ? in ice_dpll_pin_state_update()
414 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
415 pin->pin == pf->dplls.pps.active_input ? in ice_dpll_pin_state_update()
419 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
421 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
425 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
427 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
432 ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx, in ice_dpll_pin_state_update()
440 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
441 parent == pf->dplls.eec.dpll_idx ? in ice_dpll_pin_state_update()
444 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
445 parent == pf->dplls.pps.dpll_idx ? in ice_dpll_pin_state_update()
449 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
451 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
456 for (parent = 0; parent < pf->dplls.rclk.num_parents; in ice_dpll_pin_state_update()
460 ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p, in ice_dpll_pin_state_update()
484 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
487 dev_err_ratelimited(ice_pf_to_dev(pf), in ice_dpll_pin_state_update()
490 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
497 * @pf: board private structure
505 * Context: Called under pf->dplls.lock
511 ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll, in ice_dpll_hw_input_prio_set() argument
517 ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx, in ice_dpll_hw_input_prio_set()
523 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_hw_input_prio_set()
541 * Context: Acquires pf->dplls.lock
553 struct ice_pf *pf = d->pf; in ice_dpll_lock_status_get() local
555 mutex_lock(&pf->dplls.lock); in ice_dpll_lock_status_get()
557 mutex_unlock(&pf->dplls.lock); in ice_dpll_lock_status_get()
571 * Context: Acquires pf->dplls.lock
581 struct ice_pf *pf = d->pf; in ice_dpll_mode_get() local
583 mutex_lock(&pf->dplls.lock); in ice_dpll_mode_get()
585 mutex_unlock(&pf->dplls.lock); in ice_dpll_mode_get()
602 * Context: Acquires pf->dplls.lock
615 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_set() local
618 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_state_set()
621 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_set()
623 ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type, in ice_dpll_pin_state_set()
626 ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack); in ice_dpll_pin_state_set()
628 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack); in ice_dpll_pin_state_set()
629 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_set()
645 * Context: Calls a function which acquires pf->dplls.lock
680 * Context: Calls a function which acquires pf->dplls.lock
709 * Context: Acquires pf->dplls.lock
723 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_get() local
726 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_state_get()
729 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_get()
730 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack); in ice_dpll_pin_state_get()
738 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_get()
754 * Context: Calls a function which acquires pf->dplls.lock
780 * Context: Calls a function which acquires pf->dplls.lock
806 * Context: Acquires pf->dplls.lock
818 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_get() local
820 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_get()
822 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_get()
838 * Context: Acquires pf->dplls.lock
850 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_set() local
853 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_prio_set()
856 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_set()
857 ret = ice_dpll_hw_input_prio_set(pf, d, p, prio, extack); in ice_dpll_input_prio_set()
858 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_set()
924 * Context: Acquires pf->dplls.lock
936 struct ice_pf *pf = p->pf; in ice_dpll_pin_phase_adjust_get() local
938 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
940 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
958 * Context: Acquires pf->dplls.lock
972 struct ice_pf *pf = d->pf; in ice_dpll_pin_phase_adjust_set() local
976 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_phase_adjust_set()
979 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
987 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en, in ice_dpll_pin_phase_adjust_set()
996 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0, in ice_dpll_pin_phase_adjust_set()
1004 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
1009 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_phase_adjust_set()
1027 * Context: Calls a function which acquires pf->dplls.lock
1055 * Context: Calls a function which acquires pf->dplls.lock
1086 * Context: Acquires pf->dplls.lock
1097 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_get() local
1099 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1104 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1121 * Context: Acquires pf->dplls.lock
1133 struct ice_pf *pf = d->pf; in ice_dpll_output_esync_set() local
1137 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_output_esync_set()
1139 mutex_lock(&pf->dplls.lock); in ice_dpll_output_esync_set()
1147 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, in ice_dpll_output_esync_set()
1155 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, in ice_dpll_output_esync_set()
1159 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_set()
1176 * Context: Acquires pf->dplls.lock
1189 struct ice_pf *pf = d->pf; in ice_dpll_output_esync_get() local
1191 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_output_esync_get()
1193 mutex_lock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1196 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1208 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1225 * Context: Acquires pf->dplls.lock
1237 struct ice_pf *pf = d->pf; in ice_dpll_input_esync_set() local
1241 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_esync_set()
1243 mutex_lock(&pf->dplls.lock); in ice_dpll_input_esync_set()
1251 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, in ice_dpll_input_esync_set()
1259 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, in ice_dpll_input_esync_set()
1263 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_set()
1280 * Context: Acquires pf->dplls.lock
1293 struct ice_pf *pf = d->pf; in ice_dpll_input_esync_get() local
1295 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_esync_get()
1297 mutex_lock(&pf->dplls.lock); in ice_dpll_input_esync_get()
1300 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_get()
1312 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_get()
1328 * Context: Acquires pf->dplls.lock
1342 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_set() local
1346 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_rclk_state_on_pin_set()
1349 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
1350 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_set()
1351 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_set()
1361 ret = ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable, in ice_dpll_rclk_state_on_pin_set()
1367 ice_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_rclk_state_on_pin_set()
1370 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
1386 * Context: Acquires pf->dplls.lock
1399 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_get() local
1403 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_rclk_state_on_pin_get()
1406 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
1407 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_get()
1408 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_get()
1411 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_RCLK_INPUT, in ice_dpll_rclk_state_on_pin_get()
1419 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
1464 * @pf: board private structure
1471 static u64 ice_generate_clock_id(struct ice_pf *pf) in ice_generate_clock_id() argument
1473 return pci_get_dsn(pf->pdev); in ice_generate_clock_id()
1508 * @pf: pf private structure
1514 * Context: Called by kworker under pf->dplls.lock
1520 ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init) in ice_dpll_update_state() argument
1525 ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state, in ice_dpll_update_state()
1529 dev_dbg(ice_pf_to_dev(pf), in ice_dpll_update_state()
1534 dev_err(ice_pf_to_dev(pf), in ice_dpll_update_state()
1537 ice_aq_str(pf->hw.adminq.sq_last_status)); in ice_dpll_update_state()
1543 d->active_input = pf->dplls.inputs[d->input_idx].pin; in ice_dpll_update_state()
1544 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1545 return ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
1552 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1557 ret = ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
1561 p = &pf->dplls.inputs[d->prev_input_idx]; in ice_dpll_update_state()
1562 ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
1567 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
1569 ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
1584 * Context: Holds pf->dplls.lock
1589 struct ice_pf *pf = container_of(d, struct ice_pf, dplls); in ice_dpll_periodic_work() local
1590 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_periodic_work()
1591 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_periodic_work()
1594 if (ice_is_reset_in_progress(pf->state)) in ice_dpll_periodic_work()
1596 mutex_lock(&pf->dplls.lock); in ice_dpll_periodic_work()
1597 ret = ice_dpll_update_state(pf, de, false); in ice_dpll_periodic_work()
1599 ret = ice_dpll_update_state(pf, dp, false); in ice_dpll_periodic_work()
1605 dev_err(ice_pf_to_dev(pf), in ice_dpll_periodic_work()
1607 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
1611 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
1639 * @pf: board private structure
1653 ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, in ice_dpll_get_pins() argument
1755 * @pf: board private structure
1772 ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu, in ice_dpll_init_direct_pins() argument
1779 ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id); in ice_dpll_init_direct_pins()
1802 * @pf: board private structure
1806 static void ice_dpll_deinit_rclk_pin(struct ice_pf *pf) in ice_dpll_deinit_rclk_pin() argument
1808 struct ice_dpll_pin *rclk = &pf->dplls.rclk; in ice_dpll_deinit_rclk_pin()
1809 struct ice_vsi *vsi = ice_get_main_vsi(pf); in ice_dpll_deinit_rclk_pin()
1814 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin; in ice_dpll_deinit_rclk_pin()
1828 * @pf: board private structure
1834 * pin with the parents it has in the info. Register pin with the pf's main vsi
1842 ice_dpll_init_rclk_pins(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_init_rclk_pins() argument
1845 struct ice_vsi *vsi = ice_get_main_vsi(pf); in ice_dpll_init_rclk_pins()
1851 ret = ice_dpll_get_pins(pf, pin, start_idx, ICE_DPLL_RCLK_NUM_PER_PF, in ice_dpll_init_rclk_pins()
1852 pf->dplls.clock_id); in ice_dpll_init_rclk_pins()
1855 for (i = 0; i < pf->dplls.rclk.num_parents; i++) { in ice_dpll_init_rclk_pins()
1856 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin; in ice_dpll_init_rclk_pins()
1861 ret = dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
1862 ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
1866 dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); in ice_dpll_init_rclk_pins()
1872 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin; in ice_dpll_init_rclk_pins()
1873 dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
1874 &ice_dpll_rclk_ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
1882 * @pf: board private structure
1883 * @cgu: if cgu is controlled by this pf
1888 static void ice_dpll_deinit_pins(struct ice_pf *pf, bool cgu) in ice_dpll_deinit_pins() argument
1890 struct ice_dpll_pin *outputs = pf->dplls.outputs; in ice_dpll_deinit_pins()
1891 struct ice_dpll_pin *inputs = pf->dplls.inputs; in ice_dpll_deinit_pins()
1892 int num_outputs = pf->dplls.num_outputs; in ice_dpll_deinit_pins()
1893 int num_inputs = pf->dplls.num_inputs; in ice_dpll_deinit_pins()
1894 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_pins()
1898 ice_dpll_deinit_rclk_pin(pf); in ice_dpll_deinit_pins()
1917 * @pf: board private structure
1920 * Initialize directly connected pf's pins within pf's dplls in a Linux dpll
1927 static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu) in ice_dpll_init_pins() argument
1932 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, in ice_dpll_init_pins()
1933 pf->dplls.num_inputs, in ice_dpll_init_pins()
1935 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins()
1939 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, in ice_dpll_init_pins()
1940 pf->dplls.num_inputs, in ice_dpll_init_pins()
1941 pf->dplls.num_outputs, in ice_dpll_init_pins()
1943 pf->dplls.eec.dpll, in ice_dpll_init_pins()
1944 pf->dplls.pps.dpll); in ice_dpll_init_pins()
1948 rclk_idx = pf->dplls.num_inputs + pf->dplls.num_outputs + pf->hw.pf_id; in ice_dpll_init_pins()
1949 ret = ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, rclk_idx, in ice_dpll_init_pins()
1956 ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs, in ice_dpll_init_pins()
1957 pf->dplls.num_outputs, in ice_dpll_init_pins()
1958 &ice_dpll_output_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
1959 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1961 ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs, in ice_dpll_init_pins()
1962 &ice_dpll_input_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
1963 pf->dplls.eec.dpll); in ice_dpll_init_pins()
1969 * @pf: board private structure
1977 ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu) in ice_dpll_deinit_dpll() argument
1986 * @pf: board private structure
1999 ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu, in ice_dpll_init_dpll() argument
2002 u64 clock_id = pf->dplls.clock_id; in ice_dpll_init_dpll()
2008 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_dpll()
2012 d->pf = pf; in ice_dpll_init_dpll()
2014 ice_dpll_update_state(pf, d, true); in ice_dpll_init_dpll()
2027 * @pf: board private structure
2031 static void ice_dpll_deinit_worker(struct ice_pf *pf) in ice_dpll_deinit_worker() argument
2033 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_worker()
2041 * @pf: board private structure
2045 * Context: Shall be called after pf->dplls.lock is initialized.
2050 static int ice_dpll_init_worker(struct ice_pf *pf) in ice_dpll_init_worker() argument
2052 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_worker()
2057 dev_name(ice_pf_to_dev(pf))); in ice_dpll_init_worker()
2069 * @pf: board private structure
2072 * Init information for generic pins, cache them in PF's pins structures.
2078 static int ice_dpll_init_info_pins_generic(struct ice_pf *pf, bool input) in ice_dpll_init_info_pins_generic() argument
2080 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_pins_generic()
2091 pin_num = pf->dplls.num_inputs; in ice_dpll_init_info_pins_generic()
2092 pins = pf->dplls.inputs; in ice_dpll_init_info_pins_generic()
2093 phase_adj_max = pf->dplls.input_phase_adj_max; in ice_dpll_init_info_pins_generic()
2097 pin_num = pf->dplls.num_outputs; in ice_dpll_init_info_pins_generic()
2098 pins = pf->dplls.outputs; in ice_dpll_init_info_pins_generic()
2099 phase_adj_max = pf->dplls.output_phase_adj_max; in ice_dpll_init_info_pins_generic()
2111 pins[i].pf = pf; in ice_dpll_init_info_pins_generic()
2112 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); in ice_dpll_init_info_pins_generic()
2121 ret = ice_aq_get_cgu_ref_prio(&pf->hw, de->dpll_idx, i, in ice_dpll_init_info_pins_generic()
2125 ret = ice_aq_get_cgu_ref_prio(&pf->hw, dp->dpll_idx, i, in ice_dpll_init_info_pins_generic()
2136 * @pf: board private structure
2139 * Init information for directly connected pins, cache them in pf's pins
2147 ice_dpll_init_info_direct_pins(struct ice_pf *pf, in ice_dpll_init_info_direct_pins() argument
2150 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_direct_pins()
2152 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info_direct_pins()
2160 pins = pf->dplls.inputs; in ice_dpll_init_info_direct_pins()
2161 num_pins = pf->dplls.num_inputs; in ice_dpll_init_info_direct_pins()
2165 pins = pf->dplls.outputs; in ice_dpll_init_info_direct_pins()
2166 num_pins = pf->dplls.num_outputs; in ice_dpll_init_info_direct_pins()
2173 return ice_dpll_init_info_pins_generic(pf, input); in ice_dpll_init_info_direct_pins()
2192 pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
2194 -pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
2197 pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
2199 -pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
2205 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); in ice_dpll_init_info_direct_pins()
2211 pins[i].pf = pf; in ice_dpll_init_info_direct_pins()
2219 * @pf: board private structure
2221 * Init information for rclk pin, cache them in pf->dplls.rclk.
2227 static int ice_dpll_init_info_rclk_pin(struct ice_pf *pf) in ice_dpll_init_info_rclk_pin() argument
2229 struct ice_dpll_pin *pin = &pf->dplls.rclk; in ice_dpll_init_info_rclk_pin()
2233 pin->pf = pf; in ice_dpll_init_info_rclk_pin()
2235 return ice_dpll_pin_state_update(pf, pin, in ice_dpll_init_info_rclk_pin()
2241 * @pf: board private structure
2251 ice_dpll_init_pins_info(struct ice_pf *pf, enum ice_dpll_pin_type pin_type) in ice_dpll_init_pins_info() argument
2256 return ice_dpll_init_info_direct_pins(pf, pin_type); in ice_dpll_init_pins_info()
2258 return ice_dpll_init_info_rclk_pin(pf); in ice_dpll_init_pins_info()
2266 * @pf: board private structure
2270 static void ice_dpll_deinit_info(struct ice_pf *pf) in ice_dpll_deinit_info() argument
2272 kfree(pf->dplls.inputs); in ice_dpll_deinit_info()
2273 kfree(pf->dplls.outputs); in ice_dpll_deinit_info()
2274 kfree(pf->dplls.eec.input_prio); in ice_dpll_deinit_info()
2275 kfree(pf->dplls.pps.input_prio); in ice_dpll_deinit_info()
2279 * ice_dpll_init_info - prepare pf's dpll information structure
2280 * @pf: board private structure
2283 * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
2289 static int ice_dpll_init_info(struct ice_pf *pf, bool cgu) in ice_dpll_init_info() argument
2292 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_init_info()
2293 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_init_info()
2294 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_info()
2295 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info()
2298 d->clock_id = ice_generate_clock_id(pf); in ice_dpll_init_info()
2301 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_info()
2328 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_INPUT); in ice_dpll_init_info()
2340 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_OUTPUT); in ice_dpll_init_info()
2345 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, in ice_dpll_init_info()
2346 &pf->dplls.rclk.num_parents); in ice_dpll_init_info()
2349 for (i = 0; i < pf->dplls.rclk.num_parents; i++) in ice_dpll_init_info()
2350 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; in ice_dpll_init_info()
2351 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_RCLK_INPUT); in ice_dpll_init_info()
2357 dev_dbg(ice_pf_to_dev(pf), in ice_dpll_init_info()
2364 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_info()
2368 ice_dpll_deinit_info(pf); in ice_dpll_init_info()
2375 * @pf: board private structure
2381 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
2383 void ice_dpll_deinit(struct ice_pf *pf) in ice_dpll_deinit() argument
2385 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU); in ice_dpll_deinit()
2387 clear_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_deinit()
2389 ice_dpll_deinit_worker(pf); in ice_dpll_deinit()
2391 ice_dpll_deinit_pins(pf, cgu); in ice_dpll_deinit()
2392 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_deinit()
2393 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_deinit()
2394 ice_dpll_deinit_info(pf); in ice_dpll_deinit()
2395 mutex_destroy(&pf->dplls.lock); in ice_dpll_deinit()
2400 * @pf: board private structure
2406 * Context: Initializes pf->dplls.lock mutex.
2408 void ice_dpll_init(struct ice_pf *pf) in ice_dpll_init() argument
2410 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU); in ice_dpll_init()
2411 struct ice_dplls *d = &pf->dplls; in ice_dpll_init()
2415 err = ice_dpll_init_info(pf, cgu); in ice_dpll_init()
2418 err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC); in ice_dpll_init()
2421 err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS); in ice_dpll_init()
2424 err = ice_dpll_init_pins(pf, cgu); in ice_dpll_init()
2428 err = ice_dpll_init_worker(pf); in ice_dpll_init()
2432 set_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_init()
2437 ice_dpll_deinit_pins(pf, cgu); in ice_dpll_init()
2439 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_init()
2441 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_init()
2443 ice_dpll_deinit_info(pf); in ice_dpll_init()
2446 dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); in ice_dpll_init()