Lines Matching full:pf
84 * @pf: private board structure
98 static bool ice_dpll_is_sw_pin(struct ice_pf *pf, u8 index, bool input) in ice_dpll_is_sw_pin() argument
100 if (input && pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) in ice_dpll_is_sw_pin()
114 * @pf: private board structure
123 static bool ice_dpll_is_reset(struct ice_pf *pf, struct netlink_ext_ack *extack) in ice_dpll_is_reset() argument
125 if (ice_is_reset_in_progress(pf->state)) { in ice_dpll_is_reset()
126 NL_SET_ERR_MSG(extack, "PF reset in progress"); in ice_dpll_is_reset()
134 * @pf: private board structure
142 * Context: Called under pf->dplls.lock
148 ice_dpll_pin_freq_set(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_pin_freq_set() argument
158 ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
163 ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags, in ice_dpll_pin_freq_set()
173 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_freq_set()
194 * Context: Acquires pf->dplls.lock
208 struct ice_pf *pf = d->pf; in ice_dpll_frequency_set() local
211 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_frequency_set()
214 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_set()
215 ret = ice_dpll_pin_freq_set(pf, p, pin_type, frequency, extack); in ice_dpll_frequency_set()
216 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_set()
232 * Context: Calls a function which acquires pf->dplls.lock
257 * Context: Calls a function which acquires pf->dplls.lock
283 * Context: Acquires pf->dplls.lock
296 struct ice_pf *pf = d->pf; in ice_dpll_frequency_get() local
298 mutex_lock(&pf->dplls.lock); in ice_dpll_frequency_get()
300 mutex_unlock(&pf->dplls.lock); in ice_dpll_frequency_get()
316 * Context: Calls a function which acquires pf->dplls.lock
341 * Context: Calls a function which acquires pf->dplls.lock
366 * Context: Calls a function which acquires and releases pf->dplls.lock
406 * Context: Calls a function which acquires and releases pf->dplls.lock
446 * Context: Called under pf->dplls.lock
495 * Context: Called under pf->dplls.lock
533 * @pf: private board struct
538 * Context: Call with pf->dplls.lock held
544 ice_dpll_sw_pins_update(struct ice_pf *pf) in ice_dpll_sw_pins_update() argument
546 struct ice_dplls *d = &pf->dplls; in ice_dpll_sw_pins_update()
551 ret = ice_read_sma_ctrl(&pf->hw, &data); in ice_dpll_sw_pins_update()
594 * @pf: private board struct
603 * Context: Called under pf->dplls.lock
609 ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_pin_state_update() argument
618 ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, &pin->status, in ice_dpll_pin_state_update()
625 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
626 pin->pin == pf->dplls.eec.active_input ? in ice_dpll_pin_state_update()
629 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
630 pin->pin == pf->dplls.pps.active_input ? in ice_dpll_pin_state_update()
634 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
636 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
640 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
642 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
647 ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx, in ice_dpll_pin_state_update()
655 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
656 parent == pf->dplls.eec.dpll_idx ? in ice_dpll_pin_state_update()
659 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
660 parent == pf->dplls.pps.dpll_idx ? in ice_dpll_pin_state_update()
664 pin->state[pf->dplls.eec.dpll_idx] = in ice_dpll_pin_state_update()
666 pin->state[pf->dplls.pps.dpll_idx] = in ice_dpll_pin_state_update()
671 for (parent = 0; parent < pf->dplls.rclk.num_parents; in ice_dpll_pin_state_update()
675 ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p, in ice_dpll_pin_state_update()
690 ret = ice_dpll_sw_pins_update(pf); in ice_dpll_pin_state_update()
704 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
707 dev_err_ratelimited(ice_pf_to_dev(pf), in ice_dpll_pin_state_update()
710 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_state_update()
717 * @pf: board private structure
725 * Context: Called under pf->dplls.lock
731 ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll, in ice_dpll_hw_input_prio_set() argument
737 ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx, in ice_dpll_hw_input_prio_set()
743 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_hw_input_prio_set()
761 * Context: Acquires pf->dplls.lock
773 struct ice_pf *pf = d->pf; in ice_dpll_lock_status_get() local
775 mutex_lock(&pf->dplls.lock); in ice_dpll_lock_status_get()
777 mutex_unlock(&pf->dplls.lock); in ice_dpll_lock_status_get()
791 * Context: Acquires pf->dplls.lock
801 struct ice_pf *pf = d->pf; in ice_dpll_mode_get() local
803 mutex_lock(&pf->dplls.lock); in ice_dpll_mode_get()
805 mutex_unlock(&pf->dplls.lock); in ice_dpll_mode_get()
819 * Context: Acquires and releases pf->dplls.lock
828 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_monitor_set() local
830 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_monitor_set()
835 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_monitor_set()
850 * Context: Acquires and releases pf->dplls.lock
859 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_monitor_get() local
861 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_monitor_get()
866 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_monitor_get()
883 * Context: Acquires pf->dplls.lock
896 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_set() local
899 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_state_set()
902 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_set()
904 ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type, in ice_dpll_pin_state_set()
907 ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack); in ice_dpll_pin_state_set()
909 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack); in ice_dpll_pin_state_set()
910 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_set()
926 * Context: Calls a function which acquires pf->dplls.lock
961 * Context: Calls a function which acquires pf->dplls.lock
990 * Context: Acquires pf->dplls.lock
1004 struct ice_pf *pf = d->pf; in ice_dpll_pin_state_get() local
1007 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_state_get()
1010 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_state_get()
1011 ret = ice_dpll_pin_state_update(pf, p, pin_type, extack); in ice_dpll_pin_state_get()
1019 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_state_get()
1035 * Context: Calls a function which acquires pf->dplls.lock
1061 * Context: Calls a function which acquires pf->dplls.lock
1084 * Context: Call with pf->dplls.lock held
1098 ret = ice_read_sma_ctrl(&p->pf->hw, &data); in ice_dpll_sma_direction_set()
1119 ret = ice_write_sma_ctrl(&p->pf->hw, data); in ice_dpll_sma_direction_set()
1121 ret = ice_dpll_pin_state_update(p->pf, p, in ice_dpll_sma_direction_set()
1139 * Context: Acquires and releases pf->dplls.lock
1153 struct ice_pf *pf = p->pf; in ice_dpll_ufl_pin_state_set() local
1159 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_ufl_pin_state_set()
1162 mutex_lock(&pf->dplls.lock); in ice_dpll_ufl_pin_state_set()
1163 hw = &pf->hw; in ice_dpll_ufl_pin_state_set()
1204 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_SOFTWARE, in ice_dpll_ufl_pin_state_set()
1214 ret = ice_dpll_pin_state_update(pf, target, type, extack); in ice_dpll_ufl_pin_state_set()
1217 mutex_unlock(&pf->dplls.lock); in ice_dpll_ufl_pin_state_set()
1233 * Context: Acquires and releases pf->dplls.lock
1246 struct ice_pf *pf = p->pf; in ice_dpll_sw_pin_state_get() local
1249 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_sw_pin_state_get()
1251 mutex_lock(&pf->dplls.lock); in ice_dpll_sw_pin_state_get()
1258 ret = ice_dpll_pin_state_update(pf, p->input, in ice_dpll_sw_pin_state_get()
1265 ret = ice_dpll_pin_state_update(pf, p->output, in ice_dpll_sw_pin_state_get()
1273 mutex_unlock(&pf->dplls.lock); in ice_dpll_sw_pin_state_get()
1289 * Context: Acquires and releases pf->dplls.lock
1302 struct ice_pf *pf = sma->pf; in ice_dpll_sma_pin_state_set() local
1307 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_sma_pin_state_set()
1310 mutex_lock(&pf->dplls.lock); in ice_dpll_sma_pin_state_set()
1327 ret = ice_dpll_pin_enable(&pf->hw, target, d->dpll_idx, type, in ice_dpll_sma_pin_state_set()
1330 ret = ice_dpll_pin_disable(&pf->hw, target, type, extack); in ice_dpll_sma_pin_state_set()
1332 ret = ice_dpll_pin_state_update(pf, target, type, extack); in ice_dpll_sma_pin_state_set()
1335 mutex_unlock(&pf->dplls.lock); in ice_dpll_sma_pin_state_set()
1351 * Context: Acquires pf->dplls.lock
1363 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_get() local
1365 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_get()
1367 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_get()
1383 * Context: Acquires pf->dplls.lock
1395 struct ice_pf *pf = d->pf; in ice_dpll_input_prio_set() local
1398 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_prio_set()
1401 mutex_lock(&pf->dplls.lock); in ice_dpll_input_prio_set()
1402 ret = ice_dpll_hw_input_prio_set(pf, d, p, prio, extack); in ice_dpll_input_prio_set()
1403 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_prio_set()
1415 struct ice_pf *pf = d->pf; in ice_dpll_sw_input_prio_get() local
1417 mutex_lock(&pf->dplls.lock); in ice_dpll_sw_input_prio_get()
1422 mutex_unlock(&pf->dplls.lock); in ice_dpll_sw_input_prio_get()
1434 struct ice_pf *pf = d->pf; in ice_dpll_sw_input_prio_set() local
1439 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_sw_input_prio_set()
1442 mutex_lock(&pf->dplls.lock); in ice_dpll_sw_input_prio_set()
1443 ret = ice_dpll_hw_input_prio_set(pf, d, p->input, prio, extack); in ice_dpll_sw_input_prio_set()
1444 mutex_unlock(&pf->dplls.lock); in ice_dpll_sw_input_prio_set()
1510 * Context: Acquires and releases pf->dplls.lock
1522 struct ice_pf *pf = p->pf; in ice_dpll_pin_sma_direction_set() local
1525 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_sma_direction_set()
1528 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_sma_direction_set()
1530 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_sma_direction_set()
1546 * Context: Acquires and releases pf->dplls.lock
1558 struct ice_pf *pf = p->pf; in ice_dpll_pin_sw_direction_get() local
1560 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_sw_direction_get()
1562 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_sw_direction_get()
1564 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_sw_direction_get()
1580 * Context: Acquires pf->dplls.lock
1592 struct ice_pf *pf = p->pf; in ice_dpll_pin_phase_adjust_get() local
1594 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
1596 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_get()
1614 * Context: Acquires pf->dplls.lock
1628 struct ice_pf *pf = d->pf; in ice_dpll_pin_phase_adjust_set() local
1632 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_pin_phase_adjust_set()
1635 mutex_lock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
1643 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en, in ice_dpll_pin_phase_adjust_set()
1652 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0, in ice_dpll_pin_phase_adjust_set()
1660 mutex_unlock(&pf->dplls.lock); in ice_dpll_pin_phase_adjust_set()
1665 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_pin_phase_adjust_set()
1683 * Context: Calls a function which acquires and releases pf->dplls.lock
1711 * Context: Calls a function which acquires pf->dplls.lock
1739 * Context: Calls a function which acquires and releases pf->dplls.lock
1774 * Context: Calls a function which acquires and releases pf->dplls.lock
1818 * Context: Acquires pf->dplls.lock
1830 struct ice_pf *pf = d->pf; in ice_dpll_phase_offset_get() local
1832 mutex_lock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1840 mutex_unlock(&pf->dplls.lock); in ice_dpll_phase_offset_get()
1857 * Context: Acquires pf->dplls.lock
1869 struct ice_pf *pf = d->pf; in ice_dpll_output_esync_set() local
1873 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_output_esync_set()
1875 mutex_lock(&pf->dplls.lock); in ice_dpll_output_esync_set()
1883 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, in ice_dpll_output_esync_set()
1891 ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, in ice_dpll_output_esync_set()
1895 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_set()
1912 * Context: Acquires pf->dplls.lock
1925 struct ice_pf *pf = d->pf; in ice_dpll_output_esync_get() local
1927 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_output_esync_get()
1929 mutex_lock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1932 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1944 mutex_unlock(&pf->dplls.lock); in ice_dpll_output_esync_get()
1961 * Context: Acquires pf->dplls.lock
1973 struct ice_pf *pf = d->pf; in ice_dpll_input_esync_set() local
1977 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_esync_set()
1979 mutex_lock(&pf->dplls.lock); in ice_dpll_input_esync_set()
1987 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, in ice_dpll_input_esync_set()
1995 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, in ice_dpll_input_esync_set()
1999 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_set()
2016 * Context: Acquires pf->dplls.lock
2029 struct ice_pf *pf = d->pf; in ice_dpll_input_esync_get() local
2031 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_esync_get()
2033 mutex_lock(&pf->dplls.lock); in ice_dpll_input_esync_get()
2036 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_get()
2048 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_esync_get()
2065 * Context: Calls a function which acquires and releases pf->dplls.lock
2101 * Context: Calls a function which acquires and releases pf->dplls.lock
2135 * Context: Acquires and releases pf->dplls.lock
2147 struct ice_pf *pf = p->pf; in ice_dpll_input_ref_sync_set() local
2151 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_ref_sync_set()
2153 mutex_lock(&pf->dplls.lock); in ice_dpll_input_ref_sync_set()
2159 ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, flags_en, 0, 0); in ice_dpll_input_ref_sync_set()
2161 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_INPUT, in ice_dpll_input_ref_sync_set()
2163 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_ref_sync_set()
2180 * Context: Acquires and releases pf->dplls.lock
2192 struct ice_pf *pf = p->pf; in ice_dpll_input_ref_sync_get() local
2194 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_input_ref_sync_get()
2196 mutex_lock(&pf->dplls.lock); in ice_dpll_input_ref_sync_get()
2201 mutex_unlock(&pf->dplls.lock); in ice_dpll_input_ref_sync_get()
2218 * Context: Calls a function which acquires and releases pf->dplls.lock
2248 * Context: Calls a function which acquires and releases pf->dplls.lock
2277 * Context: Acquires pf->dplls.lock
2291 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_set() local
2295 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_rclk_state_on_pin_set()
2298 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
2299 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_set()
2300 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_set()
2310 ret = ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable, in ice_dpll_rclk_state_on_pin_set()
2316 libie_aq_str(pf->hw.adminq.sq_last_status), in ice_dpll_rclk_state_on_pin_set()
2319 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_set()
2335 * Context: Acquires pf->dplls.lock
2348 struct ice_pf *pf = p->pf; in ice_dpll_rclk_state_on_pin_get() local
2352 if (ice_dpll_is_reset(pf, extack)) in ice_dpll_rclk_state_on_pin_get()
2355 mutex_lock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
2356 hw_idx = parent->idx - pf->dplls.base_rclk_idx; in ice_dpll_rclk_state_on_pin_get()
2357 if (hw_idx >= pf->dplls.num_inputs) in ice_dpll_rclk_state_on_pin_get()
2360 ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_RCLK_INPUT, in ice_dpll_rclk_state_on_pin_get()
2368 mutex_unlock(&pf->dplls.lock); in ice_dpll_rclk_state_on_pin_get()
2453 * @pf: board private structure
2460 static u64 ice_generate_clock_id(struct ice_pf *pf) in ice_generate_clock_id() argument
2462 return pci_get_dsn(pf->pdev); in ice_generate_clock_id()
2497 * @pf: pf private structure
2506 static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf) in ice_dpll_is_pps_phase_monitor() argument
2509 int ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas, in ice_dpll_is_pps_phase_monitor()
2512 if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_ESRCH) in ice_dpll_is_pps_phase_monitor()
2527 * Context: Must be called while pf->dplls.lock is released.
2542 * @pf: pf private structure
2549 * Context: Shall be called with pf->dplls.lock being locked.
2554 static int ice_dpll_pps_update_phase_offsets(struct ice_pf *pf, in ice_dpll_pps_update_phase_offsets() argument
2563 ret = ice_aq_get_cgu_input_pin_measure(&pf->hw, DPLL_TYPE_PPS, meas, in ice_dpll_pps_update_phase_offsets()
2565 if (ret && pf->hw.adminq.sq_last_status == LIBIE_AQ_RC_EAGAIN) { in ice_dpll_pps_update_phase_offsets()
2568 dev_err(ice_pf_to_dev(pf), in ice_dpll_pps_update_phase_offsets()
2571 libie_aq_str(pf->hw.adminq.sq_last_status)); in ice_dpll_pps_update_phase_offsets()
2574 for (i = 0; i < pf->dplls.num_inputs; i++) { in ice_dpll_pps_update_phase_offsets()
2575 p = &pf->dplls.inputs[i]; in ice_dpll_pps_update_phase_offsets()
2588 dev_dbg(ice_pf_to_dev(pf), in ice_dpll_pps_update_phase_offsets()
2601 * @pf: pf private structure
2607 * Context: Called by kworker under pf->dplls.lock
2613 ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init) in ice_dpll_update_state() argument
2618 ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state, in ice_dpll_update_state()
2622 dev_dbg(ice_pf_to_dev(pf), in ice_dpll_update_state()
2627 dev_err(ice_pf_to_dev(pf), in ice_dpll_update_state()
2630 libie_aq_str(pf->hw.adminq.sq_last_status)); in ice_dpll_update_state()
2636 d->active_input = pf->dplls.inputs[d->input_idx].pin; in ice_dpll_update_state()
2637 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
2638 return ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
2645 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
2650 ret = ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
2654 p = &pf->dplls.inputs[d->prev_input_idx]; in ice_dpll_update_state()
2655 ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
2660 p = &pf->dplls.inputs[d->input_idx]; in ice_dpll_update_state()
2662 ice_dpll_pin_state_update(pf, p, in ice_dpll_update_state()
2677 * Context: Holds pf->dplls.lock
2682 struct ice_pf *pf = container_of(d, struct ice_pf, dplls); in ice_dpll_periodic_work() local
2683 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_periodic_work()
2684 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_periodic_work()
2688 if (ice_is_reset_in_progress(pf->state)) in ice_dpll_periodic_work()
2690 mutex_lock(&pf->dplls.lock); in ice_dpll_periodic_work()
2692 ret = ice_dpll_update_state(pf, de, false); in ice_dpll_periodic_work()
2694 ret = ice_dpll_update_state(pf, dp, false); in ice_dpll_periodic_work()
2697 ret = ice_dpll_pps_update_phase_offsets(pf, &phase_offset_ntf); in ice_dpll_periodic_work()
2703 dev_err(ice_pf_to_dev(pf), in ice_dpll_periodic_work()
2705 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
2709 mutex_unlock(&pf->dplls.lock); in ice_dpll_periodic_work()
2725 * @pf: pf private structure
2734 static int ice_dpll_init_ref_sync_inputs(struct ice_pf *pf) in ice_dpll_init_ref_sync_inputs() argument
2736 struct ice_dpll_pin *inputs = pf->dplls.inputs; in ice_dpll_init_ref_sync_inputs()
2737 struct ice_hw *hw = &pf->hw; in ice_dpll_init_ref_sync_inputs()
2743 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_ref_sync_inputs()
2822 * @pf: board private structure
2836 ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins, in ice_dpll_get_pins() argument
2972 * @pf: board private structure
2989 ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu, in ice_dpll_init_direct_pins() argument
2996 ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id); in ice_dpll_init_direct_pins()
3019 * @pf: board private structure
3023 static void ice_dpll_deinit_rclk_pin(struct ice_pf *pf) in ice_dpll_deinit_rclk_pin() argument
3025 struct ice_dpll_pin *rclk = &pf->dplls.rclk; in ice_dpll_deinit_rclk_pin()
3026 struct ice_vsi *vsi = ice_get_main_vsi(pf); in ice_dpll_deinit_rclk_pin()
3031 parent = pf->dplls.inputs[rclk->parent_idx[i]].pin; in ice_dpll_deinit_rclk_pin()
3045 * @pf: board private structure
3051 * pin with the parents it has in the info. Register pin with the pf's main vsi
3059 ice_dpll_init_rclk_pins(struct ice_pf *pf, struct ice_dpll_pin *pin, in ice_dpll_init_rclk_pins() argument
3062 struct ice_vsi *vsi = ice_get_main_vsi(pf); in ice_dpll_init_rclk_pins()
3068 ret = ice_dpll_get_pins(pf, pin, start_idx, ICE_DPLL_RCLK_NUM_PER_PF, in ice_dpll_init_rclk_pins()
3069 pf->dplls.clock_id); in ice_dpll_init_rclk_pins()
3072 for (i = 0; i < pf->dplls.rclk.num_parents; i++) { in ice_dpll_init_rclk_pins()
3073 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin; in ice_dpll_init_rclk_pins()
3078 ret = dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
3079 ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
3083 dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin); in ice_dpll_init_rclk_pins()
3089 parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin; in ice_dpll_init_rclk_pins()
3090 dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin, in ice_dpll_init_rclk_pins()
3091 &ice_dpll_rclk_ops, &pf->dplls.rclk); in ice_dpll_init_rclk_pins()
3099 * @pf: board private structure
3100 * @cgu: if cgu is controlled by this pf
3105 static void ice_dpll_deinit_pins(struct ice_pf *pf, bool cgu) in ice_dpll_deinit_pins() argument
3107 struct ice_dpll_pin *outputs = pf->dplls.outputs; in ice_dpll_deinit_pins()
3108 struct ice_dpll_pin *inputs = pf->dplls.inputs; in ice_dpll_deinit_pins()
3109 int num_outputs = pf->dplls.num_outputs; in ice_dpll_deinit_pins()
3110 int num_inputs = pf->dplls.num_inputs; in ice_dpll_deinit_pins()
3111 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_pins()
3115 ice_dpll_deinit_rclk_pin(pf); in ice_dpll_deinit_pins()
3129 if (!pf->dplls.generic) { in ice_dpll_deinit_pins()
3130 ice_dpll_deinit_direct_pins(cgu, pf->dplls.ufl, in ice_dpll_deinit_pins()
3133 pf->dplls.pps.dpll, in ice_dpll_deinit_pins()
3134 pf->dplls.eec.dpll); in ice_dpll_deinit_pins()
3135 ice_dpll_deinit_direct_pins(cgu, pf->dplls.sma, in ice_dpll_deinit_pins()
3138 pf->dplls.pps.dpll, in ice_dpll_deinit_pins()
3139 pf->dplls.eec.dpll); in ice_dpll_deinit_pins()
3146 * @pf: board private structure
3149 * Initialize directly connected pf's pins within pf's dplls in a Linux dpll
3156 static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu) in ice_dpll_init_pins() argument
3160 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0, in ice_dpll_init_pins()
3161 pf->dplls.num_inputs, in ice_dpll_init_pins()
3163 pf->dplls.eec.dpll, pf->dplls.pps.dpll); in ice_dpll_init_pins()
3166 count = pf->dplls.num_inputs; in ice_dpll_init_pins()
3168 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs, in ice_dpll_init_pins()
3170 pf->dplls.num_outputs, in ice_dpll_init_pins()
3172 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3173 pf->dplls.pps.dpll); in ice_dpll_init_pins()
3176 count += pf->dplls.num_outputs; in ice_dpll_init_pins()
3177 if (!pf->dplls.generic) { in ice_dpll_init_pins()
3178 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.sma, in ice_dpll_init_pins()
3182 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3183 pf->dplls.pps.dpll); in ice_dpll_init_pins()
3187 ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.ufl, in ice_dpll_init_pins()
3191 pf->dplls.eec.dpll, in ice_dpll_init_pins()
3192 pf->dplls.pps.dpll); in ice_dpll_init_pins()
3197 ret = ice_dpll_pin_ref_sync_register(pf->dplls.inputs, in ice_dpll_init_pins()
3198 pf->dplls.num_inputs); in ice_dpll_init_pins()
3201 ret = ice_dpll_pin_ref_sync_register(pf->dplls.sma, in ice_dpll_init_pins()
3206 count += pf->dplls.num_outputs + 2 * ICE_DPLL_PIN_SW_NUM; in ice_dpll_init_pins()
3208 ret = ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, count + pf->hw.pf_id, in ice_dpll_init_pins()
3215 ice_dpll_deinit_direct_pins(cgu, pf->dplls.ufl, in ice_dpll_init_pins()
3218 pf->dplls.pps.dpll, pf->dplls.eec.dpll); in ice_dpll_init_pins()
3220 ice_dpll_deinit_direct_pins(cgu, pf->dplls.sma, in ice_dpll_init_pins()
3223 pf->dplls.pps.dpll, pf->dplls.eec.dpll); in ice_dpll_init_pins()
3225 ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs, in ice_dpll_init_pins()
3226 pf->dplls.num_outputs, in ice_dpll_init_pins()
3227 &ice_dpll_output_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
3228 pf->dplls.eec.dpll); in ice_dpll_init_pins()
3230 ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs, in ice_dpll_init_pins()
3231 &ice_dpll_input_ops, pf->dplls.pps.dpll, in ice_dpll_init_pins()
3232 pf->dplls.eec.dpll); in ice_dpll_init_pins()
3238 * @pf: board private structure
3246 ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu) in ice_dpll_deinit_dpll() argument
3255 * @pf: board private structure
3268 ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu, in ice_dpll_init_dpll() argument
3271 u64 clock_id = pf->dplls.clock_id; in ice_dpll_init_dpll()
3277 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_dpll()
3281 d->pf = pf; in ice_dpll_init_dpll()
3285 if (type == DPLL_TYPE_PPS && ice_dpll_is_pps_phase_monitor(pf)) in ice_dpll_init_dpll()
3287 ice_dpll_update_state(pf, d, true); in ice_dpll_init_dpll()
3301 * @pf: board private structure
3305 static void ice_dpll_deinit_worker(struct ice_pf *pf) in ice_dpll_deinit_worker() argument
3307 struct ice_dplls *d = &pf->dplls; in ice_dpll_deinit_worker()
3315 * @pf: board private structure
3319 * Context: Shall be called after pf->dplls.lock is initialized.
3324 static int ice_dpll_init_worker(struct ice_pf *pf) in ice_dpll_init_worker() argument
3326 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_worker()
3331 dev_name(ice_pf_to_dev(pf))); in ice_dpll_init_worker()
3355 * @pf: board private structure
3358 * Init information for generic pins, cache them in PF's pins structures.
3364 static int ice_dpll_init_info_pins_generic(struct ice_pf *pf, bool input) in ice_dpll_init_info_pins_generic() argument
3366 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_pins_generic()
3377 pin_num = pf->dplls.num_inputs; in ice_dpll_init_info_pins_generic()
3378 pins = pf->dplls.inputs; in ice_dpll_init_info_pins_generic()
3379 phase_adj_max = pf->dplls.input_phase_adj_max; in ice_dpll_init_info_pins_generic()
3383 pin_num = pf->dplls.num_outputs; in ice_dpll_init_info_pins_generic()
3384 pins = pf->dplls.outputs; in ice_dpll_init_info_pins_generic()
3385 phase_adj_max = pf->dplls.output_phase_adj_max; in ice_dpll_init_info_pins_generic()
3397 pins[i].pf = pf; in ice_dpll_init_info_pins_generic()
3398 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); in ice_dpll_init_info_pins_generic()
3407 ret = ice_aq_get_cgu_ref_prio(&pf->hw, de->dpll_idx, i, in ice_dpll_init_info_pins_generic()
3411 ret = ice_aq_get_cgu_ref_prio(&pf->hw, dp->dpll_idx, i, in ice_dpll_init_info_pins_generic()
3422 * @pf: board private structure
3425 * Init information for directly connected pins, cache them in pf's pins
3433 ice_dpll_init_info_direct_pins(struct ice_pf *pf, in ice_dpll_init_info_direct_pins() argument
3436 struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps; in ice_dpll_init_info_direct_pins()
3438 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info_direct_pins()
3447 pins = pf->dplls.inputs; in ice_dpll_init_info_direct_pins()
3448 num_pins = pf->dplls.num_inputs; in ice_dpll_init_info_direct_pins()
3449 phase_adj_max = pf->dplls.input_phase_adj_max; in ice_dpll_init_info_direct_pins()
3453 pins = pf->dplls.outputs; in ice_dpll_init_info_direct_pins()
3454 num_pins = pf->dplls.num_outputs; in ice_dpll_init_info_direct_pins()
3455 phase_adj_max = pf->dplls.output_phase_adj_max; in ice_dpll_init_info_direct_pins()
3462 pf->dplls.generic = true; in ice_dpll_init_info_direct_pins()
3463 return ice_dpll_init_info_pins_generic(pf, input); in ice_dpll_init_info_direct_pins()
3482 if (ice_dpll_is_sw_pin(pf, i, true)) in ice_dpll_init_info_direct_pins()
3488 if (ice_dpll_is_sw_pin(pf, i, false)) in ice_dpll_init_info_direct_pins()
3494 ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL); in ice_dpll_init_info_direct_pins()
3500 pins[i].pf = pf; in ice_dpll_init_info_direct_pins()
3503 ret = ice_dpll_init_ref_sync_inputs(pf); in ice_dpll_init_info_direct_pins()
3510 * @pf: board private structure
3512 * Init information for rclk pin, cache them in pf->dplls.rclk.
3518 static int ice_dpll_init_info_rclk_pin(struct ice_pf *pf) in ice_dpll_init_info_rclk_pin() argument
3520 struct ice_dpll_pin *pin = &pf->dplls.rclk; in ice_dpll_init_info_rclk_pin()
3524 pin->pf = pf; in ice_dpll_init_info_rclk_pin()
3526 return ice_dpll_pin_state_update(pf, pin, in ice_dpll_init_info_rclk_pin()
3532 * @pf: board private structure
3535 * pf->dplls.sma and pf->dplls.ufl.
3541 static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) in ice_dpll_init_info_sw_pins() argument
3544 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_info_sw_pins()
3549 if (pf->hw.device_id == ICE_DEV_ID_E810C_QSFP) in ice_dpll_init_info_sw_pins()
3559 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, in ice_dpll_init_info_sw_pins()
3566 pin->pf = pf; in ice_dpll_init_info_sw_pins()
3579 pin->pf = pf; in ice_dpll_init_info_sw_pins()
3585 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, in ice_dpll_init_info_sw_pins()
3598 ice_cgu_get_pin_freq_supp(&pf->hw, pin_abs_idx, in ice_dpll_init_info_sw_pins()
3607 ret = ice_dpll_pin_state_update(pf, pin, ICE_DPLL_PIN_TYPE_SOFTWARE, in ice_dpll_init_info_sw_pins()
3617 * @pf: board private structure
3627 ice_dpll_init_pins_info(struct ice_pf *pf, enum ice_dpll_pin_type pin_type) in ice_dpll_init_pins_info() argument
3632 return ice_dpll_init_info_direct_pins(pf, pin_type); in ice_dpll_init_pins_info()
3634 return ice_dpll_init_info_rclk_pin(pf); in ice_dpll_init_pins_info()
3636 return ice_dpll_init_info_sw_pins(pf); in ice_dpll_init_pins_info()
3644 * @pf: board private structure
3648 static void ice_dpll_deinit_info(struct ice_pf *pf) in ice_dpll_deinit_info() argument
3650 kfree(pf->dplls.inputs); in ice_dpll_deinit_info()
3651 kfree(pf->dplls.outputs); in ice_dpll_deinit_info()
3652 kfree(pf->dplls.eec.input_prio); in ice_dpll_deinit_info()
3653 kfree(pf->dplls.pps.input_prio); in ice_dpll_deinit_info()
3657 * ice_dpll_init_info - prepare pf's dpll information structure
3658 * @pf: board private structure
3661 * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
3667 static int ice_dpll_init_info(struct ice_pf *pf, bool cgu) in ice_dpll_init_info() argument
3670 struct ice_dpll *de = &pf->dplls.eec; in ice_dpll_init_info()
3671 struct ice_dpll *dp = &pf->dplls.pps; in ice_dpll_init_info()
3672 struct ice_dplls *d = &pf->dplls; in ice_dpll_init_info()
3673 struct ice_hw *hw = &pf->hw; in ice_dpll_init_info()
3676 d->clock_id = ice_generate_clock_id(pf); in ice_dpll_init_info()
3679 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_info()
3708 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_INPUT); in ice_dpll_init_info()
3720 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_OUTPUT); in ice_dpll_init_info()
3723 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_SOFTWARE); in ice_dpll_init_info()
3728 ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx, in ice_dpll_init_info()
3729 &pf->dplls.rclk.num_parents); in ice_dpll_init_info()
3732 for (i = 0; i < pf->dplls.rclk.num_parents; i++) in ice_dpll_init_info()
3733 pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i; in ice_dpll_init_info()
3734 ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_RCLK_INPUT); in ice_dpll_init_info()
3740 dev_dbg(ice_pf_to_dev(pf), in ice_dpll_init_info()
3747 dev_err(ice_pf_to_dev(pf), in ice_dpll_init_info()
3751 ice_dpll_deinit_info(pf); in ice_dpll_init_info()
3758 * @pf: board private structure
3764 * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
3766 void ice_dpll_deinit(struct ice_pf *pf) in ice_dpll_deinit() argument
3768 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU); in ice_dpll_deinit()
3770 clear_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_deinit()
3772 ice_dpll_deinit_worker(pf); in ice_dpll_deinit()
3774 ice_dpll_deinit_pins(pf, cgu); in ice_dpll_deinit()
3775 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_deinit()
3776 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_deinit()
3777 ice_dpll_deinit_info(pf); in ice_dpll_deinit()
3778 mutex_destroy(&pf->dplls.lock); in ice_dpll_deinit()
3783 * @pf: board private structure
3789 * Context: Initializes pf->dplls.lock mutex.
3791 void ice_dpll_init(struct ice_pf *pf) in ice_dpll_init() argument
3793 bool cgu = ice_is_feature_supported(pf, ICE_F_CGU); in ice_dpll_init()
3794 struct ice_dplls *d = &pf->dplls; in ice_dpll_init()
3798 err = ice_dpll_init_info(pf, cgu); in ice_dpll_init()
3801 err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC); in ice_dpll_init()
3804 err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS); in ice_dpll_init()
3807 err = ice_dpll_init_pins(pf, cgu); in ice_dpll_init()
3811 err = ice_dpll_init_worker(pf); in ice_dpll_init()
3815 set_bit(ICE_FLAG_DPLL, pf->flags); in ice_dpll_init()
3820 ice_dpll_deinit_pins(pf, cgu); in ice_dpll_init()
3822 ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu); in ice_dpll_init()
3824 ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu); in ice_dpll_init()
3826 ice_dpll_deinit_info(pf); in ice_dpll_init()
3829 dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err); in ice_dpll_init()