22 	int ret_code = 0;  in i40e_init_nvm()
61 	u64 time_left = 0;  in i40e_acquire_nvm()
62 	int ret_code = 0;  in i40e_acquire_nvm()
68 					    0, &time_left, NULL);  in i40e_acquire_nvm()
88 							access, 0, &time_left,  in i40e_acquire_nvm()
97 			hw->nvm.hw_semaphore_timeout = 0;  in i40e_acquire_nvm()
116 	u32 total_delay = 0;  in i40e_release_nvm()
117 	int ret_code = 0;  in i40e_release_nvm()
122 	ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);  in i40e_release_nvm()
132 						    0, NULL);  in i40e_release_nvm()
149 	for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {  in i40e_poll_sr_srctl_done_bit()
152 			ret_code = 0;  in i40e_poll_sr_srctl_done_bit()
165  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
202 			   "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",  in i40e_read_nvm_word_srctl()
228 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_read_nvm_aq()
263  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
273 	ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);  in i40e_read_nvm_word_aq()
282  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
302  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
310 	int ret_code = 0;  in i40e_read_nvm_word()
341 	u16 specific_ptr = 0;  in i40e_read_nvm_module_data()
342 	u16 ptr_value = 0;  in i40e_read_nvm_module_data()
343 	u32 offset = 0;  in i40e_read_nvm_module_data()
346 	if (module_ptr != 0) {  in i40e_read_nvm_module_data()
355 #define I40E_NVM_INVALID_PTR_VAL 0x7FFF  in i40e_read_nvm_module_data()
356 #define I40E_NVM_INVALID_VAL 0xFFFF  in i40e_read_nvm_module_data()
402  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
413 	int ret_code = 0;  in i40e_read_nvm_buffer_srctl()
417 	for (word = 0; word < *words; word++) {  in i40e_read_nvm_buffer_srctl()
433  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
445 	u16 words_read = 0;  in i40e_read_nvm_buffer_aq()
448 	u16 i = 0;  in i40e_read_nvm_buffer_aq()
467 		ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,  in i40e_read_nvm_buffer_aq()
479 	for (i = 0; i < *words; i++)  in i40e_read_nvm_buffer_aq()
490  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
510  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
521 	int ret_code = 0;  in i40e_read_nvm_buffer()
555 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_write_nvm_aq()
582 					      data, last_command, 0,  in i40e_write_nvm_aq()
602 	u16 pcie_alt_module = 0;  in i40e_calc_nvm_checksum()
603 	u16 checksum_local = 0;  in i40e_calc_nvm_checksum()
604 	u16 vpd_module = 0;  in i40e_calc_nvm_checksum()
607 	u16 i = 0;  in i40e_calc_nvm_checksum()
633 	for (i = 0; i < hw->nvm.sr_size; i++) {  in i40e_calc_nvm_checksum()
635 		if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {  in i40e_calc_nvm_checksum()
688 		ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,  in i40e_update_nvm_checksum()
706 	u16 checksum_local = 0;  in i40e_validate_nvm_checksum()
707 	u16 checksum_sr = 0;  in i40e_validate_nvm_checksum()
708 	int ret_code = 0;  in i40e_validate_nvm_checksum()
816 			if (module == 0xf)  in i40e_nvmupd_validate_command()
818 			else if (module == 0)  in i40e_nvmupd_validate_command()
854 			if (module == 0)  in i40e_nvmupd_validate_command()
878 	int status = 0;  in i40e_nvmupd_nvm_erase()
885 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_nvmupd_nvm_erase()
892 			   "%s mod 0x%x  off 0x%x len 0x%x\n",  in i40e_nvmupd_nvm_erase()
919 	int status = 0;  in i40e_nvmupd_nvm_write()
927 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_nvmupd_nvm_write()
935 			   "%s mod 0x%x off 0x%x len 0x%x\n",  in i40e_nvmupd_nvm_write()
968 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_nvmupd_nvm_read()
975 			   "%s mod 0x%x  off 0x%x  len 0x%x\n",  in i40e_nvmupd_nvm_read()
1001 	u32 buff_size = 0;  in i40e_nvmupd_exec_aq()
1008 	if (cmd->offset == 0xffff)  in i40e_nvmupd_exec_aq()
1009 		return 0;  in i40e_nvmupd_exec_aq()
1011 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_nvmupd_exec_aq()
1015 	memset(&hw->nvm_wb_desc, 0, aq_desc_len);  in i40e_nvmupd_exec_aq()
1047 		memset(&hw->nvm_aq_event_desc, 0, aq_desc_len);  in i40e_nvmupd_exec_aq()
1128 	if (remainder > 0) {  in i40e_nvmupd_get_aq_result()
1136 	return 0;  in i40e_nvmupd_get_aq_result()
1170 	return 0;  in i40e_nvmupd_get_aq_event()
1188 	int status = 0;  in i40e_nvmupd_state_init()
1327 	int status = 0;  in i40e_nvmupd_state_reading()
1370 	int status = 0;  in i40e_nvmupd_state_writing()
1491 	*perrno = 0;  in i40e_nvmupd_command()
1496 …UG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data…  in i40e_nvmupd_command()
1518 		bytes[0] = hw->nvmupd_state;  in i40e_nvmupd_command()
1521 			bytes[1] = 0;  in i40e_nvmupd_command()
1529 		return 0;  in i40e_nvmupd_command()
1566 		if (cmd->offset == 0xffff) {  in i40e_nvmupd_command()
1568 			status = 0;  in i40e_nvmupd_command()
1596 		   "NVMUPD: clearing wait on opcode 0x%04x\n",  in i40e_nvmupd_clear_wait_state()
1603 	hw->nvm_wait_opcode = 0;  in i40e_nvmupd_clear_wait_state()